Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7406716 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
5126651 |
1 |
|
|
T24 |
21 |
|
T25 |
1196 |
|
T27 |
38 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11875629 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
657738 |
1 |
|
|
T24 |
1 |
|
T25 |
199 |
|
T27 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
7404721 |
1 |
|
|
T21 |
56149 |
|
T22 |
486 |
|
T23 |
69 |
| auto[1] |
5128646 |
1 |
|
|
T24 |
30 |
|
T25 |
1019 |
|
T27 |
45 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2237366 |
1 |
|
|
T24 |
23 |
|
T25 |
396 |
|
T27 |
21 |
| auto[1] |
auto[0] |
auto[1] |
329072 |
1 |
|
|
T24 |
1 |
|
T25 |
92 |
|
T30 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2233542 |
1 |
|
|
T24 |
6 |
|
T25 |
424 |
|
T27 |
23 |
| auto[1] |
auto[1] |
auto[1] |
328666 |
1 |
|
|
T25 |
107 |
|
T27 |
1 |
|
T30 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |