Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5356847	1			T21	55		T22	1		T23	19
all_pins[1]	5356847	1			T21	55		T22	1		T23	19
all_pins[2]	5356847	1			T21	55		T22	1		T23	19
all_pins[3]	5356847	1			T21	55		T22	1		T23	19
all_pins[4]	5356847	1			T21	55		T22	1		T23	19
all_pins[5]	5356847	1			T21	55		T22	1		T23	19
all_pins[6]	5356847	1			T21	55		T22	1		T23	19
all_pins[7]	5356847	1			T21	55		T22	1		T23	19
all_pins[8]	5356847	1			T21	55		T22	1		T23	19
all_pins[9]	5356847	1			T21	55		T22	1		T23	19
all_pins[10]	5356847	1			T21	55		T22	1		T23	19
all_pins[11]	5356847	1			T21	55		T22	1		T23	19
all_pins[12]	5356847	1			T21	55		T22	1		T23	19
all_pins[13]	5356847	1			T21	55		T22	1		T23	19
all_pins[14]	5356847	1			T21	55		T22	1		T23	19
all_pins[15]	5356847	1			T21	55		T22	1		T23	19
all_pins[16]	5356847	1			T21	55		T22	1		T23	19
all_pins[17]	5356847	1			T21	55		T22	1		T23	19
all_pins[18]	5356847	1			T21	55		T22	1		T23	19
all_pins[19]	5356847	1			T21	55		T22	1		T23	19
all_pins[20]	5356847	1			T21	55		T22	1		T23	19
all_pins[21]	5356847	1			T21	55		T22	1		T23	19
all_pins[22]	5356847	1			T21	55		T22	1		T23	19
all_pins[23]	5356847	1			T21	55		T22	1		T23	19
all_pins[24]	5356847	1			T21	55		T22	1		T23	19
all_pins[25]	5356847	1			T21	55		T22	1		T23	19
all_pins[26]	5356847	1			T21	55		T22	1		T23	19
all_pins[27]	5356847	1			T21	55		T22	1		T23	19
all_pins[28]	5356847	1			T21	55		T22	1		T23	19
all_pins[29]	5356847	1			T21	55		T22	1		T23	19
all_pins[30]	5356847	1			T21	55		T22	1		T23	19
all_pins[31]	5356847	1			T21	55		T22	1		T23	19

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	106591306	1			T21	868		T22	32		T23	345
values[0x1]	64827798	1			T21	892		T23	263		T24	3352
transitions[0x0=>0x1]	38900624	1			T21	423		T23	132		T24	2057
transitions[0x1=>0x0]	38900470	1			T21	423		T23	132		T24	2056

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3326935	1			T21	32		T22	1		T23	15
all_pins[0]	values[0x1]	2029912	1			T21	23		T23	4		T24	64
all_pins[0]	transitions[0x0=>0x1]	1259200	1			T21	14		T23	2		T24	32
all_pins[0]	transitions[0x1=>0x0]	1261335	1			T21	15		T23	3		T24	63
all_pins[1]	values[0x0]	3331317	1			T21	29		T22	1		T23	14
all_pins[1]	values[0x1]	2025530	1			T21	26		T23	5		T24	95
all_pins[1]	transitions[0x0=>0x1]	1212972	1			T21	12		T23	3		T24	70
all_pins[1]	transitions[0x1=>0x0]	1217354	1			T21	9		T23	2		T24	39
all_pins[2]	values[0x0]	3331255	1			T21	24		T22	1		T23	12
all_pins[2]	values[0x1]	2025592	1			T21	31		T23	7		T24	78
all_pins[2]	transitions[0x0=>0x1]	1212002	1			T21	17		T23	5		T24	46
all_pins[2]	transitions[0x1=>0x0]	1211940	1			T21	12		T23	3		T24	63
all_pins[3]	values[0x0]	3331082	1			T21	24		T22	1		T23	6
all_pins[3]	values[0x1]	2025765	1			T21	31		T23	13		T24	105
all_pins[3]	transitions[0x0=>0x1]	1214839	1			T21	17		T23	8		T24	64
all_pins[3]	transitions[0x1=>0x0]	1214666	1			T21	17		T23	2		T24	37
all_pins[4]	values[0x0]	3325451	1			T21	33		T22	1		T23	12
all_pins[4]	values[0x1]	2031396	1			T21	22		T23	7		T24	81
all_pins[4]	transitions[0x0=>0x1]	1216629	1			T21	6		T23	3		T24	55
all_pins[4]	transitions[0x1=>0x0]	1210998	1			T21	15		T23	9		T24	79
all_pins[5]	values[0x0]	3334909	1			T21	20		T22	1		T23	6
all_pins[5]	values[0x1]	2021938	1			T21	35		T23	13		T24	114
all_pins[5]	transitions[0x0=>0x1]	1207990	1			T21	18		T23	8		T24	78
all_pins[5]	transitions[0x1=>0x0]	1217448	1			T21	5		T23	2		T24	45
all_pins[6]	values[0x0]	3333997	1			T21	32		T22	1		T23	11
all_pins[6]	values[0x1]	2022850	1			T21	23		T23	8		T24	94
all_pins[6]	transitions[0x0=>0x1]	1217013	1			T21	6		T23	2		T24	68
all_pins[6]	transitions[0x1=>0x0]	1216101	1			T21	18		T23	7		T24	88
all_pins[7]	values[0x0]	3328867	1			T21	31		T22	1		T23	12
all_pins[7]	values[0x1]	2027980	1			T21	24		T23	7		T24	126
all_pins[7]	transitions[0x0=>0x1]	1216205	1			T21	14		T23	4		T24	79
all_pins[7]	transitions[0x1=>0x0]	1211075	1			T21	13		T23	5		T24	47
all_pins[8]	values[0x0]	3326375	1			T21	29		T22	1		T23	13
all_pins[8]	values[0x1]	2030472	1			T21	26		T23	6		T24	91
all_pins[8]	transitions[0x0=>0x1]	1216660	1			T21	11		T23	3		T24	49
all_pins[8]	transitions[0x1=>0x0]	1214168	1			T21	9		T23	4		T24	84
all_pins[9]	values[0x0]	3328602	1			T21	30		T22	1		T23	15
all_pins[9]	values[0x1]	2028245	1			T21	25		T23	4		T24	94
all_pins[9]	transitions[0x0=>0x1]	1215254	1			T21	14		T23	1		T24	44
all_pins[9]	transitions[0x1=>0x0]	1217481	1			T21	15		T23	3		T24	41
all_pins[10]	values[0x0]	3337834	1			T21	28		T22	1		T23	5
all_pins[10]	values[0x1]	2019013	1			T21	27		T23	14		T24	134
all_pins[10]	transitions[0x0=>0x1]	1210995	1			T21	13		T23	11		T24	63
all_pins[10]	transitions[0x1=>0x0]	1220227	1			T21	11		T23	1		T24	23
all_pins[11]	values[0x0]	3329076	1			T21	24		T22	1		T23	11
all_pins[11]	values[0x1]	2027771	1			T21	31		T23	8		T24	83
all_pins[11]	transitions[0x0=>0x1]	1219808	1			T21	14		T23	2		T24	38
all_pins[11]	transitions[0x1=>0x0]	1211050	1			T21	10		T23	8		T24	89
all_pins[12]	values[0x0]	3333081	1			T21	19		T22	1		T23	7
all_pins[12]	values[0x1]	2023766	1			T21	36		T23	12		T24	130
all_pins[12]	transitions[0x0=>0x1]	1211052	1			T21	15		T23	8		T24	107
all_pins[12]	transitions[0x1=>0x0]	1215057	1			T21	10		T23	4		T24	60
all_pins[13]	values[0x0]	3325420	1			T21	25		T22	1		T23	13
all_pins[13]	values[0x1]	2031427	1			T21	30		T23	6		T24	100
all_pins[13]	transitions[0x0=>0x1]	1217522	1			T21	9		T23	2		T24	57
all_pins[13]	transitions[0x1=>0x0]	1209861	1			T21	15		T23	8		T24	87
all_pins[14]	values[0x0]	3334540	1			T21	26		T22	1		T23	12
all_pins[14]	values[0x1]	2022307	1			T21	29		T23	7		T24	172
all_pins[14]	transitions[0x0=>0x1]	1209333	1			T21	12		T23	4		T24	116
all_pins[14]	transitions[0x1=>0x0]	1218453	1			T21	13		T23	3		T24	44
all_pins[15]	values[0x0]	3327836	1			T21	31		T22	1		T23	11
all_pins[15]	values[0x1]	2029011	1			T21	24		T23	8		T24	95
all_pins[15]	transitions[0x0=>0x1]	1216265	1			T21	10		T23	2		T24	38
all_pins[15]	transitions[0x1=>0x0]	1209561	1			T21	15		T23	1		T24	115
all_pins[16]	values[0x0]	3330671	1			T21	25		T22	1		T23	11
all_pins[16]	values[0x1]	2026176	1			T21	30		T23	8		T24	97
all_pins[16]	transitions[0x0=>0x1]	1213054	1			T21	17		T23	2		T24	63
all_pins[16]	transitions[0x1=>0x0]	1215889	1			T21	11		T23	2		T24	61
all_pins[17]	values[0x0]	3330303	1			T21	24		T22	1		T23	5
all_pins[17]	values[0x1]	2026544	1			T21	31		T23	14		T24	95
all_pins[17]	transitions[0x0=>0x1]	1214836	1			T21	12		T23	9		T24	60
all_pins[17]	transitions[0x1=>0x0]	1214468	1			T21	11		T23	3		T24	62
all_pins[18]	values[0x0]	3335222	1			T21	26		T22	1		T23	13
all_pins[18]	values[0x1]	2021625	1			T21	29		T23	6		T24	130
all_pins[18]	transitions[0x0=>0x1]	1212617	1			T21	13		T23	1		T24	75
all_pins[18]	transitions[0x1=>0x0]	1217536	1			T21	15		T23	9		T24	40
all_pins[19]	values[0x0]	3329212	1			T21	27		T22	1		T23	13
all_pins[19]	values[0x1]	2027635	1			T21	28		T23	6		T24	123
all_pins[19]	transitions[0x0=>0x1]	1216696	1			T21	15		T23	3		T24	76
all_pins[19]	transitions[0x1=>0x0]	1210686	1			T21	16		T23	3		T24	83
all_pins[20]	values[0x0]	3337229	1			T21	28		T22	1		T23	12
all_pins[20]	values[0x1]	2019618	1			T21	27		T23	7		T24	87
all_pins[20]	transitions[0x0=>0x1]	1211958	1			T21	18		T23	3		T24	71
all_pins[20]	transitions[0x1=>0x0]	1219975	1			T21	19		T23	2		T24	107
all_pins[21]	values[0x0]	3330636	1			T21	24		T22	1		T23	7
all_pins[21]	values[0x1]	2026211	1			T21	31		T23	12		T24	89
all_pins[21]	transitions[0x0=>0x1]	1217329	1			T21	14		T23	9		T24	70
all_pins[21]	transitions[0x1=>0x0]	1210736	1			T21	10		T23	4		T24	68
all_pins[22]	values[0x0]	3337450	1			T21	24		T22	1		T23	9
all_pins[22]	values[0x1]	2019397	1			T21	31		T23	10		T24	112
all_pins[22]	transitions[0x0=>0x1]	1210165	1			T21	14		T23	2		T24	73
all_pins[22]	transitions[0x1=>0x0]	1216979	1			T21	14		T23	4		T24	50
all_pins[23]	values[0x0]	3331506	1			T21	28		T22	1		T23	13
all_pins[23]	values[0x1]	2025341	1			T21	27		T23	6		T24	97
all_pins[23]	transitions[0x0=>0x1]	1217570	1			T21	12		T23	3		T24	50
all_pins[23]	transitions[0x1=>0x0]	1211626	1			T21	16		T23	7		T24	65
all_pins[24]	values[0x0]	3331046	1			T21	31		T22	1		T23	14
all_pins[24]	values[0x1]	2025801	1			T21	24		T23	5		T24	114
all_pins[24]	transitions[0x0=>0x1]	1213357	1			T21	10		T23	4		T24	92
all_pins[24]	transitions[0x1=>0x0]	1212897	1			T21	13		T23	5		T24	75
all_pins[25]	values[0x0]	3337756	1			T21	23		T22	1		T23	10
all_pins[25]	values[0x1]	2019091	1			T21	32		T23	9		T24	147
all_pins[25]	transitions[0x0=>0x1]	1210294	1			T21	19		T23	6		T24	68
all_pins[25]	transitions[0x1=>0x0]	1217004	1			T21	11		T23	2		T24	35
all_pins[26]	values[0x0]	3335977	1			T21	31		T22	1		T23	12
all_pins[26]	values[0x1]	2020870	1			T21	24		T23	7		T24	87
all_pins[26]	transitions[0x0=>0x1]	1213639	1			T21	11		T23	4		T24	38
all_pins[26]	transitions[0x1=>0x0]	1211860	1			T21	19		T23	6		T24	98
all_pins[27]	values[0x0]	3325473	1			T21	28		T22	1		T23	14
all_pins[27]	values[0x1]	2031374	1			T21	27		T23	5		T24	101
all_pins[27]	transitions[0x0=>0x1]	1218567	1			T21	16		T23	1		T24	61
all_pins[27]	transitions[0x1=>0x0]	1208063	1			T21	13		T23	3		T24	47
all_pins[28]	values[0x0]	3331192	1			T21	33		T22	1		T23	8
all_pins[28]	values[0x1]	2025655	1			T21	22		T23	11		T24	126
all_pins[28]	transitions[0x0=>0x1]	1211610	1			T21	12		T23	7		T24	72
all_pins[28]	transitions[0x1=>0x0]	1217329	1			T21	17		T23	1		T24	47
all_pins[29]	values[0x0]	3327175	1			T21	23		T22	1		T23	5
all_pins[29]	values[0x1]	2029672	1			T21	32		T23	14		T24	97
all_pins[29]	transitions[0x0=>0x1]	1215594	1			T21	21		T23	6		T24	63
all_pins[29]	transitions[0x1=>0x0]	1211577	1			T21	11		T23	3		T24	92
all_pins[30]	values[0x0]	3329235	1			T21	25		T22	1		T23	10
all_pins[30]	values[0x1]	2027612	1			T21	30		T23	9		T24	98
all_pins[30]	transitions[0x0=>0x1]	1214671	1			T21	9		T23	1		T24	54
all_pins[30]	transitions[0x1=>0x0]	1216731	1			T21	11		T23	6		T24	53
all_pins[31]	values[0x0]	3324646	1			T21	31		T22	1		T23	14
all_pins[31]	values[0x1]	2032201	1			T21	24		T23	5		T24	96
all_pins[31]	transitions[0x0=>0x1]	1214928	1			T21	8		T23	3		T24	67
all_pins[31]	transitions[0x1=>0x0]	1210339	1			T21	14		T23	7		T24	69