Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[1]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[2]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[3]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[4]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[5]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[6]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[7]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[8]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[9]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[10]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[11]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[12]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[13]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[14]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[15]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[16]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[17]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[18]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[19]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[20]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[21]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[22]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[23]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[24]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[25]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[26]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[27]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[28]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[29]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[30]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[31]	17138334	1			T21	806		T22	518		T23	6151

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

331099921

1

T21

12848

T22

13063

T23

95078

auto[1]

217326767

1

T21

12944

T22

3513

T23

101754

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

437894685

1

T21

25792

T22

12116

T23

196832

auto[1]

110532003

1

T22

4460

T25

4897

T26

81

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

405645198

1

T21

25792

T22

8425

T23

196832

auto[1]

142781490

1

T22

8151

T25

9093

T26

1616

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	6364172	1			T21	392		T22	63		T23	2919
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4574232	1			T21	414		T22	5		T23	3232
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1740212	1			T22	26		T25	60		T26	2
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2239917	1			T22	294		T25	122		T26	5
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	500375	1			T22	41		T25	21		T26	15
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1719426	1			T22	89		T25	82		T27	56
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	6372105	1			T21	437		T22	224		T23	3185
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4567272	1			T21	369		T22	26		T23	2966
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1739236	1			T22	73		T25	74		T27	44
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2237820	1			T22	137		T25	207		T26	15
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	501909	1			T22	15		T25	29		T26	46
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1719992	1			T22	43		T25	94		T26	2
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	6378459	1			T21	460		T22	147		T23	3087
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4563932	1			T21	346		T22	9		T23	3064
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1742452	1			T22	95		T25	99		T26	4
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2235474	1			T22	192		T25	179		T26	3
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	500059	1			T22	29		T25	30		T26	54
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1717958	1			T22	46		T25	69		T26	2
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	6370333	1			T21	501		T22	174		T23	2609
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4566992	1			T21	305		T22	16		T23	3542
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1738264	1			T22	60		T25	85		T27	46
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2242140	1			T22	186		T25	186		T26	14
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	501401	1			T22	28		T25	15		T26	59
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1719204	1			T22	54		T25	83		T27	46
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	6358995	1			T21	391		T22	166		T23	3143
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4573391	1			T21	415		T22	17		T23	3008
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1737418	1			T22	70		T25	61		T27	55
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2243658	1			T22	153		T25	279		T26	16
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	499299	1			T22	26		T25	39		T26	64
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1725573	1			T22	86		T25	66		T26	2
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	6373599	1			T21	402		T22	176		T23	2919
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4567815	1			T21	404		T22	16		T23	3232
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1737838	1			T22	68		T25	69		T27	51
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2231446	1			T22	159		T25	213		T26	15
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	502071	1			T22	22		T25	16		T26	65
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1725565	1			T22	77		T25	79		T27	58
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	6367570	1			T21	380		T22	160		T23	3288
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4575681	1			T21	426		T22	28		T23	2863
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1737887	1			T22	64		T25	117		T26	2
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2233504	1			T22	188		T25	126		T26	3
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	500625	1			T22	7		T25	26		T26	26
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1723067	1			T22	71		T25	62		T27	34
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	6355490	1			T21	449		T22	175		T23	2903
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4578637	1			T21	357		T22	28		T23	3248
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1738311	1			T22	97		T25	63		T27	45
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2239790	1			T22	119		T25	192		T26	18
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	498867	1			T22	18		T25	26		T26	63
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1727239	1			T22	81		T25	99		T27	52
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	6369247	1			T21	351		T22	212		T23	2705
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4574075	1			T21	455		T22	23		T23	3446
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1736187	1			T22	76		T25	99		T26	4
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2234951	1			T22	141		T25	165		T26	6
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	501748	1			T22	20		T25	27		T26	56
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1722126	1			T22	46		T25	61		T27	62
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	6356918	1			T21	382		T22	170		T23	3331
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4578169	1			T21	424		T22	15		T23	2820
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1735499	1			T22	50		T25	61		T26	2
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2243496	1			T22	190		T25	178		T26	3
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	499634	1			T22	26		T25	21		T26	23
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1724618	1			T22	67		T25	64		T27	64
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	6362062	1			T21	371		T22	131		T23	3007
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4571581	1			T21	435		T22	13		T23	3144
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1734429	1			T22	54		T25	100		T26	2
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2246293	1			T22	221		T25	215		T26	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	499682	1			T22	33		T25	34		T26	18
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1724287	1			T22	66		T25	85		T27	56
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	6363129	1			T21	387		T22	178		T23	3504
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4577147	1			T21	419		T22	21		T23	2647
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1742605	1			T22	89		T25	73		T26	2
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2233553	1			T22	169		T25	147		T26	7
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	498632	1			T22	19		T25	36		T26	41
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1723268	1			T22	42		T25	111		T27	60
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	6362629	1			T21	408		T22	167		T23	3543
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4579157	1			T21	398		T22	16		T23	2608
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1737856	1			T22	54		T25	55		T27	39
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2236583	1			T22	173		T25	246		T26	12
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	501498	1			T22	34		T25	36		T26	39
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1720611	1			T22	74		T25	94		T26	2
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	6373028	1			T21	404		T22	178		T23	2612
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4564450	1			T21	402		T22	15		T23	3539
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1739833	1			T22	96		T25	98		T27	58
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2235791	1			T22	144		T25	197		T26	20
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	501171	1			T22	29		T25	26		T26	68
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1724061	1			T22	56		T25	66		T26	2
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	6365253	1			T21	333		T22	80		T23	2573
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4566891	1			T21	473		T22	7		T23	3578
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1738016	1			T22	34		T25	137		T26	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2242571	1			T22	269		T25	192		T26	4
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	502581	1			T22	34		T25	38		T26	26
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1723022	1			T22	94		T25	47		T26	2
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	6365282	1			T21	406		T22	177		T23	2903
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4566906	1			T21	400		T22	20		T23	3248
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1731998	1			T22	50		T25	82		T27	60
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2253701	1			T22	192		T25	208		T26	15
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	502420	1			T22	17		T25	37		T26	40
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1718027	1			T22	62		T25	76		T26	2
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	6369032	1			T21	393		T22	209		T23	3115
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4573265	1			T21	413		T22	23		T23	3036
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1728952	1			T22	59		T25	67		T26	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2251925	1			T22	133		T25	187		T26	10
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	498194	1			T22	19		T25	30		T26	40
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1716966	1			T22	75		T25	66		T27	64
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	6374132	1			T21	331		T22	245		T23	2834
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4570196	1			T21	475		T22	36		T23	3317
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1734856	1			T22	80		T25	81		T26	3
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2245486	1			T22	83		T25	121		T26	3
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	500004	1			T22	14		T25	35		T26	12
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1713660	1			T22	60		T25	72		T26	5
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	6373904	1			T21	400		T22	200		T23	2737
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4575365	1			T21	406		T22	29		T23	3414
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1726402	1			T22	76		T25	63		T27	64
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2250060	1			T22	138		T25	161		T26	16
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	499277	1			T22	8		T25	24		T26	36
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1713326	1			T22	67		T25	67		T26	2
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	6374845	1			T21	422		T22	242		T23	3601
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4575534	1			T21	384		T22	31		T23	2550
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1737657	1			T22	93		T25	102		T26	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2241375	1			T22	89		T25	95		T26	18
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	498124	1			T22	7		T25	6		T26	34
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1710799	1			T22	56		T25	65		T26	2
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	6369423	1			T21	375		T22	159		T23	2651
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4573067	1			T21	431		T22	33		T23	3500
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1729197	1			T22	113		T25	91		T26	5
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2244168	1			T22	94		T25	194		T26	11
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	501833	1			T22	13		T25	34		T26	59
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1720646	1			T22	106		T25	79		T27	62
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	6363486	1			T21	410		T22	168		T23	2761
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4579930	1			T21	396		T22	29		T23	3390
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1739359	1			T22	64		T25	68		T27	39
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2240103	1			T22	175		T25	186		T26	9
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	502570	1			T22	11		T25	34		T26	35
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1712886	1			T22	71		T25	75		T26	2
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	6375341	1			T21	420		T22	138		T23	2610
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4561710	1			T21	386		T22	13		T23	3541
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1725161	1			T22	57		T25	59		T27	41
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2251887	1			T22	207		T25	216		T26	11
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	501280	1			T22	35		T25	41		T26	48
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1722955	1			T22	68		T25	60		T26	2
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	6378619	1			T21	422		T22	171		T23	3144
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4566980	1			T21	384		T22	12		T23	3007
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1731715	1			T22	64		T25	62		T26	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2244169	1			T22	202		T25	138		T27	48
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	500786	1			T22	20		T25	14		T26	6
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1716065	1			T22	49		T25	49		T27	44
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	6379390	1			T21	363		T22	182		T23	2759
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4570022	1			T21	443		T22	20		T23	3392
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1730057	1			T22	91		T25	102		T26	3
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2243692	1			T22	146		T25	107		T26	18
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	500516	1			T22	15		T25	16		T26	51
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1714657	1			T22	64		T25	37		T26	2
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	6384006	1			T21	390		T22	185		T23	3443
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4567484	1			T21	416		T22	19		T23	2708
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1732192	1			T22	75		T25	40		T27	48
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2238597	1			T22	121		T25	246		T26	10
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	500731	1			T22	31		T25	33		T26	53
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1715324	1			T22	87		T25	114		T26	2
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	6377063	1			T21	504		T22	190		T23	3017
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4569731	1			T21	302		T22	18		T23	3134
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1730020	1			T22	84		T25	102		T26	2
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2244225	1			T22	177		T25	145		T26	3
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	502013	1			T22	22		T25	15		T26	18
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1715282	1			T22	27		T25	78		T26	5
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	6380005	1			T21	359		T22	174		T23	2622
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4571087	1			T21	447		T22	21		T23	3529
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1732191	1			T22	112		T25	79		T26	2
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2241909	1			T22	120		T25	215		T26	11
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	501476	1			T22	12		T25	40		T26	52
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1711666	1			T22	79		T25	67		T26	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	6378590	1			T21	412		T22	190		T23	2824
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4565522	1			T21	394		T22	21		T23	3327
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1732122	1			T22	112		T25	59		T27	52
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2243584	1			T22	130		T25	222		T26	3
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	501223	1			T22	17		T25	42		T26	19
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1717293	1			T22	48		T25	72		T27	28
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	6370555	1			T21	441		T22	171		T23	2715
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4567592	1			T21	365		T22	23		T23	3436
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1731201	1			T22	61		T25	100		T27	72
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2247110	1			T22	169		T25	202		T26	2
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	502070	1			T22	22		T25	21		T26	19
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1719806	1			T22	72		T25	72		T27	28
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	6374254	1			T21	368		T22	145		T23	3533
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4571677	1			T21	438		T22	16		T23	2618
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1736316	1			T22	38		T25	73		T27	61
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2236927	1			T22	181		T25	177		T26	15
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	500307	1			T22	33		T25	23		T26	58
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1718853	1			T22	105		T25	64		T26	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	6366113	1			T21	384		T22	151		T23	2481
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4579556	1			T21	422		T22	21		T23	3670
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1727684	1			T22	52		T25	69		T27	37
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2243864	1			T22	186		T25	189		T26	5
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	500465	1			T22	23		T25	28		T26	29
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1720652	1			T22	85		T25	72		T27	52

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal