Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[1]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[2]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[3]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[4]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[5]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[6]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[7]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[8]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[9]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[10]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[11]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[12]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[13]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[14]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[15]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[16]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[17]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[18]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[19]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[20]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[21]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[22]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[23]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[24]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[25]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[26]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[27]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[28]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[29]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[30]	17138334	1			T21	806		T22	518		T23	6151
bins_for_gpio_bits[31]	17138334	1			T21	806		T22	518		T23	6151

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

331099921

1

T21

12848

T22

13063

T23

95078

auto[1]

217326767

1

T21

12944

T22

3513

T23

101754

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

331091632

1

T21

12848

T22

13054

T23

95078

auto[1]

217335056

1

T21

12944

T22

3522

T23

101754

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	10037603	1			T21	392		T22	368		T23	2919
bins_for_gpio_bits[0]	auto[0]	auto[1]	306412	1			T22	15		T25	11		T26	1
bins_for_gpio_bits[0]	auto[1]	auto[0]	306698	1			T22	15		T25	11		T26	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	6487621	1			T21	414		T22	120		T23	3232
bins_for_gpio_bits[1]	auto[0]	auto[0]	10042767	1			T21	437		T22	422		T23	3185
bins_for_gpio_bits[1]	auto[0]	auto[1]	306136	1			T22	11		T25	15		T27	12
bins_for_gpio_bits[1]	auto[1]	auto[0]	306394	1			T22	12		T25	15		T27	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	6483037	1			T21	369		T22	73		T23	2966
bins_for_gpio_bits[2]	auto[0]	auto[0]	10050529	1			T21	460		T22	425		T23	3087
bins_for_gpio_bits[2]	auto[0]	auto[1]	305612	1			T22	8		T25	12		T26	1
bins_for_gpio_bits[2]	auto[1]	auto[0]	305856	1			T22	9		T25	12		T26	1
bins_for_gpio_bits[2]	auto[1]	auto[1]	6476337	1			T21	346		T22	76		T23	3064
bins_for_gpio_bits[3]	auto[0]	auto[0]	10044442	1			T21	501		T22	411		T23	2609
bins_for_gpio_bits[3]	auto[0]	auto[1]	306002	1			T22	9		T25	15		T27	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	306295	1			T22	9		T25	15		T27	10
bins_for_gpio_bits[3]	auto[1]	auto[1]	6481595	1			T21	305		T22	89		T23	3542
bins_for_gpio_bits[4]	auto[0]	auto[0]	10032829	1			T21	391		T22	376		T23	3143
bins_for_gpio_bits[4]	auto[0]	auto[1]	306972	1			T22	13		T25	13		T27	8
bins_for_gpio_bits[4]	auto[1]	auto[0]	307242	1			T22	13		T25	13		T27	8
bins_for_gpio_bits[4]	auto[1]	auto[1]	6491291	1			T21	415		T22	116		T23	3008
bins_for_gpio_bits[5]	auto[0]	auto[0]	10036738	1			T21	402		T22	390		T23	2919
bins_for_gpio_bits[5]	auto[0]	auto[1]	305905	1			T22	13		T25	15		T27	12
bins_for_gpio_bits[5]	auto[1]	auto[0]	306145	1			T22	13		T25	15		T27	12
bins_for_gpio_bits[5]	auto[1]	auto[1]	6489546	1			T21	404		T22	102		T23	3232
bins_for_gpio_bits[6]	auto[0]	auto[0]	10032334	1			T21	380		T22	401		T23	3288
bins_for_gpio_bits[6]	auto[0]	auto[1]	306361	1			T22	11		T25	15		T26	1
bins_for_gpio_bits[6]	auto[1]	auto[0]	306627	1			T22	11		T25	15		T26	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	6493012	1			T21	426		T22	95		T23	2863
bins_for_gpio_bits[7]	auto[0]	auto[0]	10026552	1			T21	449		T22	379		T23	2903
bins_for_gpio_bits[7]	auto[0]	auto[1]	306800	1			T22	12		T25	17		T27	13
bins_for_gpio_bits[7]	auto[1]	auto[0]	307039	1			T22	12		T25	17		T27	13
bins_for_gpio_bits[7]	auto[1]	auto[1]	6497943	1			T21	357		T22	115		T23	3248
bins_for_gpio_bits[8]	auto[0]	auto[0]	10033727	1			T21	351		T22	420		T23	2705
bins_for_gpio_bits[8]	auto[0]	auto[1]	306357	1			T22	9		T25	13		T26	1
bins_for_gpio_bits[8]	auto[1]	auto[0]	306658	1			T22	9		T25	13		T26	1
bins_for_gpio_bits[8]	auto[1]	auto[1]	6491592	1			T21	455		T22	80		T23	3446
bins_for_gpio_bits[9]	auto[0]	auto[0]	10029099	1			T21	382		T22	400		T23	3331
bins_for_gpio_bits[9]	auto[0]	auto[1]	306551	1			T22	10		T25	9		T26	1
bins_for_gpio_bits[9]	auto[1]	auto[0]	306814	1			T22	10		T25	9		T26	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	6495870	1			T21	424		T22	98		T23	2820
bins_for_gpio_bits[10]	auto[0]	auto[0]	10036445	1			T21	371		T22	397		T23	3007
bins_for_gpio_bits[10]	auto[0]	auto[1]	306061	1			T22	9		T25	12		T26	1
bins_for_gpio_bits[10]	auto[1]	auto[0]	306339	1			T22	9		T25	12		T26	1
bins_for_gpio_bits[10]	auto[1]	auto[1]	6489489	1			T21	435		T22	103		T23	3144
bins_for_gpio_bits[11]	auto[0]	auto[0]	10032200	1			T21	387		T22	427		T23	3504
bins_for_gpio_bits[11]	auto[0]	auto[1]	306814	1			T22	9		T25	18		T26	1
bins_for_gpio_bits[11]	auto[1]	auto[0]	307087	1			T22	9		T25	18		T26	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	6492233	1			T21	419		T22	73		T23	2647
bins_for_gpio_bits[12]	auto[0]	auto[0]	10030953	1			T21	408		T22	381		T23	3543
bins_for_gpio_bits[12]	auto[0]	auto[1]	305885	1			T22	13		T25	16		T27	14
bins_for_gpio_bits[12]	auto[1]	auto[0]	306115	1			T22	13		T25	16		T27	14
bins_for_gpio_bits[12]	auto[1]	auto[1]	6495381	1			T21	398		T22	111		T23	2608
bins_for_gpio_bits[13]	auto[0]	auto[0]	10042589	1			T21	404		T22	408		T23	2612
bins_for_gpio_bits[13]	auto[0]	auto[1]	305758	1			T22	10		T25	11		T27	13
bins_for_gpio_bits[13]	auto[1]	auto[0]	306063	1			T22	10		T25	11		T27	14
bins_for_gpio_bits[13]	auto[1]	auto[1]	6483924	1			T21	402		T22	90		T23	3539
bins_for_gpio_bits[14]	auto[0]	auto[0]	10039028	1			T21	333		T22	370		T23	2573
bins_for_gpio_bits[14]	auto[0]	auto[1]	306529	1			T22	13		T25	11		T26	2
bins_for_gpio_bits[14]	auto[1]	auto[0]	306812	1			T22	13		T25	11		T26	2
bins_for_gpio_bits[14]	auto[1]	auto[1]	6485965	1			T21	473		T22	122		T23	3578
bins_for_gpio_bits[15]	auto[0]	auto[0]	10044388	1			T21	406		T22	407		T23	2903
bins_for_gpio_bits[15]	auto[0]	auto[1]	306373	1			T22	12		T25	15		T27	10
bins_for_gpio_bits[15]	auto[1]	auto[0]	306593	1			T22	12		T25	15		T27	11
bins_for_gpio_bits[15]	auto[1]	auto[1]	6480980	1			T21	400		T22	87		T23	3248
bins_for_gpio_bits[16]	auto[0]	auto[0]	10043067	1			T21	393		T22	389		T23	3115
bins_for_gpio_bits[16]	auto[0]	auto[1]	306586	1			T22	11		T25	14		T26	1
bins_for_gpio_bits[16]	auto[1]	auto[0]	306842	1			T22	12		T25	14		T27	11
bins_for_gpio_bits[16]	auto[1]	auto[1]	6481839	1			T21	413		T22	106		T23	3036
bins_for_gpio_bits[17]	auto[0]	auto[0]	10047574	1			T21	331		T22	399		T23	2834
bins_for_gpio_bits[17]	auto[0]	auto[1]	306663	1			T22	9		T25	12		T26	2
bins_for_gpio_bits[17]	auto[1]	auto[0]	306900	1			T22	9		T25	12		T26	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	6477197	1			T21	475		T22	101		T23	3317
bins_for_gpio_bits[18]	auto[0]	auto[0]	10043505	1			T21	400		T22	404		T23	2737
bins_for_gpio_bits[18]	auto[0]	auto[1]	306621	1			T22	10		T25	10		T27	17
bins_for_gpio_bits[18]	auto[1]	auto[0]	306861	1			T22	10		T25	10		T27	17
bins_for_gpio_bits[18]	auto[1]	auto[1]	6481347	1			T21	406		T22	94		T23	3414
bins_for_gpio_bits[19]	auto[0]	auto[0]	10047526	1			T21	422		T22	416		T23	3601
bins_for_gpio_bits[19]	auto[0]	auto[1]	306093	1			T22	8		T25	8		T26	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	306351	1			T22	8		T25	8		T26	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	6478364	1			T21	384		T22	86		T23	2550
bins_for_gpio_bits[20]	auto[0]	auto[0]	10035587	1			T21	375		T22	349		T23	2651
bins_for_gpio_bits[20]	auto[0]	auto[1]	306969	1			T22	16		T25	11		T26	1
bins_for_gpio_bits[20]	auto[1]	auto[0]	307201	1			T22	17		T25	11		T26	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	6488577	1			T21	431		T22	136		T23	3500
bins_for_gpio_bits[21]	auto[0]	auto[0]	10036207	1			T21	410		T22	398		T23	2761
bins_for_gpio_bits[21]	auto[0]	auto[1]	306467	1			T22	8		T25	12		T27	10
bins_for_gpio_bits[21]	auto[1]	auto[0]	306741	1			T22	9		T25	12		T27	10
bins_for_gpio_bits[21]	auto[1]	auto[1]	6488919	1			T21	396		T22	103		T23	3390
bins_for_gpio_bits[22]	auto[0]	auto[0]	10045604	1			T21	420		T22	386		T23	2610
bins_for_gpio_bits[22]	auto[0]	auto[1]	306518	1			T22	15		T25	13		T27	13
bins_for_gpio_bits[22]	auto[1]	auto[0]	306785	1			T22	16		T25	13		T27	13
bins_for_gpio_bits[22]	auto[1]	auto[1]	6479427	1			T21	386		T22	101		T23	3541
bins_for_gpio_bits[23]	auto[0]	auto[0]	10047345	1			T21	422		T22	426		T23	3144
bins_for_gpio_bits[23]	auto[0]	auto[1]	306930	1			T22	11		T25	7		T26	1
bins_for_gpio_bits[23]	auto[1]	auto[0]	307158	1			T22	11		T25	7		T26	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	6476901	1			T21	384		T22	70		T23	3007
bins_for_gpio_bits[24]	auto[0]	auto[0]	10046518	1			T21	363		T22	410		T23	2759
bins_for_gpio_bits[24]	auto[0]	auto[1]	306377	1			T22	8		T25	6		T26	1
bins_for_gpio_bits[24]	auto[1]	auto[0]	306621	1			T22	9		T25	6		T26	1
bins_for_gpio_bits[24]	auto[1]	auto[1]	6478818	1			T21	443		T22	91		T23	3392
bins_for_gpio_bits[25]	auto[0]	auto[0]	10047978	1			T21	390		T22	366		T23	3443
bins_for_gpio_bits[25]	auto[0]	auto[1]	306617	1			T22	15		T25	16		T27	13
bins_for_gpio_bits[25]	auto[1]	auto[0]	306817	1			T22	15		T25	16		T27	13
bins_for_gpio_bits[25]	auto[1]	auto[1]	6476922	1			T21	416		T22	122		T23	2708
bins_for_gpio_bits[26]	auto[0]	auto[0]	10044949	1			T21	504		T22	443		T23	3017
bins_for_gpio_bits[26]	auto[0]	auto[1]	306049	1			T22	8		T25	12		T26	1
bins_for_gpio_bits[26]	auto[1]	auto[0]	306359	1			T22	8		T25	12		T26	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	6480977	1			T21	302		T22	59		T23	3134
bins_for_gpio_bits[27]	auto[0]	auto[0]	10048091	1			T21	359		T22	392		T23	2622
bins_for_gpio_bits[27]	auto[0]	auto[1]	305759	1			T22	13		T25	11		T26	1
bins_for_gpio_bits[27]	auto[1]	auto[0]	306014	1			T22	14		T25	11		T26	1
bins_for_gpio_bits[27]	auto[1]	auto[1]	6478470	1			T21	447		T22	99		T23	3529
bins_for_gpio_bits[28]	auto[0]	auto[0]	10047610	1			T21	412		T22	423		T23	2824
bins_for_gpio_bits[28]	auto[0]	auto[1]	306437	1			T22	9		T25	16		T27	10
bins_for_gpio_bits[28]	auto[1]	auto[0]	306686	1			T22	9		T25	16		T27	10
bins_for_gpio_bits[28]	auto[1]	auto[1]	6477601	1			T21	394		T22	77		T23	3327
bins_for_gpio_bits[29]	auto[0]	auto[0]	10042092	1			T21	441		T22	388		T23	2715
bins_for_gpio_bits[29]	auto[0]	auto[1]	306510	1			T22	13		T25	17		T27	10
bins_for_gpio_bits[29]	auto[1]	auto[0]	306774	1			T22	13		T25	17		T27	10
bins_for_gpio_bits[29]	auto[1]	auto[1]	6482958	1			T21	365		T22	104		T23	3436
bins_for_gpio_bits[30]	auto[0]	auto[0]	10040902	1			T21	368		T22	348		T23	3533
bins_for_gpio_bits[30]	auto[0]	auto[1]	306345	1			T22	15		T25	11		T27	9
bins_for_gpio_bits[30]	auto[1]	auto[0]	306595	1			T22	16		T25	11		T27	9
bins_for_gpio_bits[30]	auto[1]	auto[1]	6484492	1			T21	438		T22	139		T23	2618
bins_for_gpio_bits[31]	auto[0]	auto[0]	10030639	1			T21	384		T22	374		T23	2481
bins_for_gpio_bits[31]	auto[0]	auto[1]	306746	1			T22	15		T25	11		T27	13
bins_for_gpio_bits[31]	auto[1]	auto[0]	307022	1			T22	15		T25	11		T27	13
bins_for_gpio_bits[31]	auto[1]	auto[1]	6493927	1			T21	422		T22	114		T23	3670