Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9984536 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
| auto[1] |
7480465 |
1 |
|
|
T24 |
377 |
|
T29 |
1286 |
|
T31 |
141268 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16517981 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
| auto[1] |
947020 |
1 |
|
|
T24 |
81 |
|
T29 |
60 |
|
T31 |
18586 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9971399 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
| auto[1] |
7493602 |
1 |
|
|
T24 |
411 |
|
T29 |
1500 |
|
T31 |
152085 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3302360 |
1 |
|
|
T24 |
224 |
|
T29 |
694 |
|
T31 |
67393 |
| auto[1] |
auto[0] |
auto[1] |
478765 |
1 |
|
|
T24 |
60 |
|
T29 |
36 |
|
T31 |
9368 |
| auto[1] |
auto[1] |
auto[0] |
3244222 |
1 |
|
|
T24 |
106 |
|
T29 |
746 |
|
T31 |
66106 |
| auto[1] |
auto[1] |
auto[1] |
468255 |
1 |
|
|
T24 |
21 |
|
T29 |
24 |
|
T31 |
9218 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |