Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9907699 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
auto[1] |
7557302 |
1 |
|
|
T24 |
422 |
|
T29 |
1134 |
|
T31 |
148778 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14410673 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
auto[1] |
3054328 |
1 |
|
|
T24 |
271 |
|
T29 |
841 |
|
T31 |
52383 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9964456 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
auto[1] |
7500545 |
1 |
|
|
T24 |
499 |
|
T29 |
1173 |
|
T31 |
142145 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2216003 |
1 |
|
|
T24 |
92 |
|
T29 |
181 |
|
T31 |
44937 |
auto[1] |
auto[0] |
auto[1] |
1521404 |
1 |
|
|
T24 |
115 |
|
T29 |
453 |
|
T31 |
25923 |
auto[1] |
auto[1] |
auto[0] |
2230214 |
1 |
|
|
T24 |
136 |
|
T29 |
151 |
|
T31 |
44825 |
auto[1] |
auto[1] |
auto[1] |
1532924 |
1 |
|
|
T24 |
156 |
|
T29 |
388 |
|
T31 |
26460 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |