Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9953023 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
auto[1] |
7511978 |
1 |
|
|
T24 |
419 |
|
T29 |
1558 |
|
T31 |
148208 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14416489 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
auto[1] |
3048512 |
1 |
|
|
T24 |
210 |
|
T29 |
896 |
|
T31 |
54037 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9965928 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
auto[1] |
7499073 |
1 |
|
|
T24 |
397 |
|
T29 |
1227 |
|
T31 |
147463 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2216534 |
1 |
|
|
T24 |
96 |
|
T29 |
123 |
|
T31 |
47130 |
auto[1] |
auto[0] |
auto[1] |
1518811 |
1 |
|
|
T24 |
94 |
|
T29 |
342 |
|
T31 |
27038 |
auto[1] |
auto[1] |
auto[0] |
2234027 |
1 |
|
|
T24 |
91 |
|
T29 |
208 |
|
T31 |
46296 |
auto[1] |
auto[1] |
auto[1] |
1529701 |
1 |
|
|
T24 |
116 |
|
T29 |
554 |
|
T31 |
26999 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |