Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9977420 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
auto[1] |
7487581 |
1 |
|
|
T24 |
350 |
|
T29 |
1303 |
|
T31 |
144146 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
14403690 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
auto[1] |
3061311 |
1 |
|
|
T24 |
216 |
|
T29 |
1124 |
|
T31 |
52305 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
9960936 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
auto[1] |
7504065 |
1 |
|
|
T24 |
396 |
|
T29 |
1350 |
|
T31 |
140517 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
2230933 |
1 |
|
|
T24 |
130 |
|
T29 |
140 |
|
T31 |
43457 |
auto[1] |
auto[0] |
auto[1] |
1539132 |
1 |
|
|
T24 |
151 |
|
T29 |
627 |
|
T31 |
25684 |
auto[1] |
auto[1] |
auto[0] |
2211821 |
1 |
|
|
T24 |
50 |
|
T29 |
86 |
|
T31 |
44755 |
auto[1] |
auto[1] |
auto[1] |
1522179 |
1 |
|
|
T24 |
65 |
|
T29 |
497 |
|
T31 |
26621 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |