Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9950659 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
| auto[1] |
7514342 |
1 |
|
|
T24 |
521 |
|
T29 |
1427 |
|
T31 |
143207 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16512717 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
| auto[1] |
952284 |
1 |
|
|
T24 |
41 |
|
T29 |
44 |
|
T31 |
17334 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9955745 |
1 |
|
|
T21 |
806 |
|
T22 |
265 |
|
T23 |
6151 |
| auto[1] |
7509256 |
1 |
|
|
T24 |
219 |
|
T29 |
1417 |
|
T31 |
143516 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3293839 |
1 |
|
|
T24 |
117 |
|
T29 |
606 |
|
T31 |
64754 |
| auto[1] |
auto[0] |
auto[1] |
478902 |
1 |
|
|
T24 |
26 |
|
T29 |
17 |
|
T31 |
8971 |
| auto[1] |
auto[1] |
auto[0] |
3263133 |
1 |
|
|
T24 |
61 |
|
T29 |
767 |
|
T31 |
61428 |
| auto[1] |
auto[1] |
auto[1] |
473382 |
1 |
|
|
T24 |
15 |
|
T29 |
27 |
|
T31 |
8363 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |