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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 946
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T92 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.532656344 Mar 07 12:57:13 PM PST 24 Mar 07 12:57:15 PM PST 24 11925906 ps
T762 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1959216810 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:45 PM PST 24 163730182 ps
T763 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1570426566 Mar 07 12:57:14 PM PST 24 Mar 07 12:57:16 PM PST 24 65490681 ps
T764 /workspace/coverage/cover_reg_top/12.gpio_intr_test.985096592 Mar 07 12:57:14 PM PST 24 Mar 07 12:57:15 PM PST 24 15022334 ps
T765 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1337104815 Mar 07 12:57:03 PM PST 24 Mar 07 12:57:04 PM PST 24 71778941 ps
T766 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.734729368 Mar 07 12:56:58 PM PST 24 Mar 07 12:57:01 PM PST 24 253460563 ps
T93 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1017598929 Mar 07 12:57:09 PM PST 24 Mar 07 12:57:11 PM PST 24 42633277 ps
T767 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3630971840 Mar 07 12:57:11 PM PST 24 Mar 07 12:57:14 PM PST 24 226758698 ps
T768 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.604294271 Mar 07 12:57:15 PM PST 24 Mar 07 12:57:17 PM PST 24 106666621 ps
T769 /workspace/coverage/cover_reg_top/24.gpio_intr_test.4005309523 Mar 07 12:57:13 PM PST 24 Mar 07 12:57:15 PM PST 24 55784037 ps
T770 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2930544775 Mar 07 12:56:50 PM PST 24 Mar 07 12:56:52 PM PST 24 130878272 ps
T771 /workspace/coverage/cover_reg_top/8.gpio_intr_test.4025803987 Mar 07 12:57:01 PM PST 24 Mar 07 12:57:02 PM PST 24 36531704 ps
T772 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.597465264 Mar 07 12:56:45 PM PST 24 Mar 07 12:56:46 PM PST 24 162423103 ps
T773 /workspace/coverage/cover_reg_top/40.gpio_intr_test.2819853436 Mar 07 12:57:23 PM PST 24 Mar 07 12:57:24 PM PST 24 42363500 ps
T774 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.321198416 Mar 07 12:57:11 PM PST 24 Mar 07 12:57:15 PM PST 24 447161063 ps
T775 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4222404177 Mar 07 12:57:20 PM PST 24 Mar 07 12:57:23 PM PST 24 151018147 ps
T776 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3876270750 Mar 07 12:57:16 PM PST 24 Mar 07 12:57:17 PM PST 24 321659191 ps
T777 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.785996992 Mar 07 12:57:32 PM PST 24 Mar 07 12:57:32 PM PST 24 29726891 ps
T778 /workspace/coverage/cover_reg_top/43.gpio_intr_test.607229573 Mar 07 12:57:19 PM PST 24 Mar 07 12:57:20 PM PST 24 14297483 ps
T779 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1076189954 Mar 07 12:57:05 PM PST 24 Mar 07 12:57:07 PM PST 24 37401336 ps
T780 /workspace/coverage/cover_reg_top/44.gpio_intr_test.339058403 Mar 07 12:57:22 PM PST 24 Mar 07 12:57:23 PM PST 24 33417262 ps
T106 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2680643235 Mar 07 12:57:06 PM PST 24 Mar 07 12:57:09 PM PST 24 19548813 ps
T781 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2452214505 Mar 07 12:57:24 PM PST 24 Mar 07 12:57:25 PM PST 24 17278929 ps
T782 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3179900802 Mar 07 12:57:30 PM PST 24 Mar 07 12:57:31 PM PST 24 11686216 ps
T783 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.416332052 Mar 07 12:57:20 PM PST 24 Mar 07 12:57:21 PM PST 24 151708033 ps
T784 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2182146562 Mar 07 12:57:28 PM PST 24 Mar 07 12:57:28 PM PST 24 40729347 ps
T785 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3844675347 Mar 07 12:57:10 PM PST 24 Mar 07 12:57:13 PM PST 24 92693649 ps
T786 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1202154313 Mar 07 12:56:41 PM PST 24 Mar 07 12:56:44 PM PST 24 59483652 ps
T787 /workspace/coverage/cover_reg_top/4.gpio_intr_test.4006749552 Mar 07 12:57:05 PM PST 24 Mar 07 12:57:07 PM PST 24 65244942 ps
T788 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2385011986 Mar 07 12:57:13 PM PST 24 Mar 07 12:57:16 PM PST 24 39719136 ps
T789 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.591459236 Mar 07 12:56:57 PM PST 24 Mar 07 12:56:59 PM PST 24 311134496 ps
T790 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1672466787 Mar 07 12:57:02 PM PST 24 Mar 07 12:57:04 PM PST 24 78148059 ps
T791 /workspace/coverage/cover_reg_top/6.gpio_intr_test.839587815 Mar 07 12:57:06 PM PST 24 Mar 07 12:57:08 PM PST 24 43896623 ps
T792 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1493635212 Mar 07 12:57:14 PM PST 24 Mar 07 12:57:16 PM PST 24 74924892 ps
T793 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3469236409 Mar 07 12:57:11 PM PST 24 Mar 07 12:57:13 PM PST 24 64486603 ps
T794 /workspace/coverage/cover_reg_top/9.gpio_intr_test.988100798 Mar 07 12:57:10 PM PST 24 Mar 07 12:57:12 PM PST 24 47002727 ps
T795 /workspace/coverage/cover_reg_top/19.gpio_intr_test.312288676 Mar 07 12:57:03 PM PST 24 Mar 07 12:57:03 PM PST 24 10557292 ps
T796 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1354815609 Mar 07 12:57:22 PM PST 24 Mar 07 12:57:24 PM PST 24 71092052 ps
T94 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.660088641 Mar 07 12:57:09 PM PST 24 Mar 07 12:57:11 PM PST 24 33240283 ps
T797 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.881674061 Mar 07 12:57:20 PM PST 24 Mar 07 12:57:22 PM PST 24 813542498 ps
T798 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1472546805 Mar 07 12:57:02 PM PST 24 Mar 07 12:57:02 PM PST 24 14163733 ps
T799 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2392983865 Mar 07 12:57:03 PM PST 24 Mar 07 12:57:04 PM PST 24 288338396 ps
T107 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.509290738 Mar 07 12:57:12 PM PST 24 Mar 07 12:57:14 PM PST 24 453864052 ps
T95 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3155493231 Mar 07 12:57:12 PM PST 24 Mar 07 12:57:18 PM PST 24 44906460 ps
T99 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3002201762 Mar 07 12:57:07 PM PST 24 Mar 07 12:57:11 PM PST 24 162843709 ps
T800 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3602747241 Mar 07 12:57:13 PM PST 24 Mar 07 12:57:17 PM PST 24 465650150 ps
T801 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2990611063 Mar 07 12:57:07 PM PST 24 Mar 07 12:57:09 PM PST 24 55086060 ps
T802 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.163536975 Mar 07 12:57:12 PM PST 24 Mar 07 12:57:14 PM PST 24 24089181 ps
T803 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1147250066 Mar 07 12:57:07 PM PST 24 Mar 07 12:57:09 PM PST 24 25286829 ps
T804 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4091139857 Mar 07 12:57:01 PM PST 24 Mar 07 12:57:02 PM PST 24 59090644 ps
T805 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2250229703 Mar 07 12:57:16 PM PST 24 Mar 07 12:57:17 PM PST 24 123431913 ps
T806 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1721442882 Mar 07 12:57:12 PM PST 24 Mar 07 12:57:14 PM PST 24 43350563 ps
T807 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2331391258 Mar 07 12:57:24 PM PST 24 Mar 07 12:57:25 PM PST 24 14111482 ps
T808 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.4264440698 Mar 07 12:57:08 PM PST 24 Mar 07 12:57:12 PM PST 24 49529557 ps
T809 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3828883816 Mar 07 12:57:10 PM PST 24 Mar 07 12:57:12 PM PST 24 40865691 ps
T810 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.795895551 Mar 07 12:57:07 PM PST 24 Mar 07 12:57:11 PM PST 24 368205995 ps
T811 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.82492857 Mar 07 12:57:18 PM PST 24 Mar 07 12:57:19 PM PST 24 19668379 ps
T812 /workspace/coverage/cover_reg_top/37.gpio_intr_test.2154204014 Mar 07 12:57:20 PM PST 24 Mar 07 12:57:21 PM PST 24 47581547 ps
T813 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2272866887 Mar 07 12:56:52 PM PST 24 Mar 07 12:56:53 PM PST 24 44778257 ps
T96 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1840647775 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:48 PM PST 24 89499833 ps
T814 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2458664102 Mar 07 12:57:09 PM PST 24 Mar 07 12:57:11 PM PST 24 27851589 ps
T815 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1160445289 Mar 07 12:57:22 PM PST 24 Mar 07 12:57:23 PM PST 24 11925287 ps
T816 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.690918239 Mar 07 12:57:16 PM PST 24 Mar 07 12:57:17 PM PST 24 561338263 ps
T817 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3198603859 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:01 PM PST 24 68880919 ps
T818 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2570458044 Mar 07 12:57:00 PM PST 24 Mar 07 12:57:01 PM PST 24 64762889 ps
T819 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2753121924 Mar 07 12:57:17 PM PST 24 Mar 07 12:57:17 PM PST 24 50836334 ps
T820 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3230892751 Mar 07 12:57:18 PM PST 24 Mar 07 12:57:19 PM PST 24 12207383 ps
T97 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2256276487 Mar 07 12:57:14 PM PST 24 Mar 07 12:57:16 PM PST 24 43791754 ps
T98 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1022178291 Mar 07 12:57:11 PM PST 24 Mar 07 12:57:12 PM PST 24 77441558 ps
T821 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1372086080 Mar 07 12:56:50 PM PST 24 Mar 07 12:56:51 PM PST 24 36788029 ps
T100 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.381529495 Mar 07 12:57:04 PM PST 24 Mar 07 12:57:05 PM PST 24 143943517 ps
T822 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3177333139 Mar 07 12:56:55 PM PST 24 Mar 07 12:56:56 PM PST 24 67496795 ps
T823 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3431929964 Mar 07 12:57:27 PM PST 24 Mar 07 12:57:28 PM PST 24 14804119 ps
T824 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.941764231 Mar 07 12:57:12 PM PST 24 Mar 07 12:57:14 PM PST 24 37581213 ps
T825 /workspace/coverage/cover_reg_top/32.gpio_intr_test.2583915220 Mar 07 12:57:16 PM PST 24 Mar 07 12:57:17 PM PST 24 15778157 ps
T826 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2395898770 Mar 07 12:57:11 PM PST 24 Mar 07 12:57:13 PM PST 24 369119219 ps
T827 /workspace/coverage/cover_reg_top/1.gpio_intr_test.1361838518 Mar 07 12:56:51 PM PST 24 Mar 07 12:56:52 PM PST 24 45273870 ps
T828 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3186040044 Mar 07 12:57:04 PM PST 24 Mar 07 12:57:07 PM PST 24 43803462 ps
T829 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.64422006 Mar 07 12:57:10 PM PST 24 Mar 07 12:57:12 PM PST 24 61893621 ps
T830 /workspace/coverage/cover_reg_top/21.gpio_intr_test.2634160392 Mar 07 12:57:26 PM PST 24 Mar 07 12:57:27 PM PST 24 10416158 ps
T831 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2458359334 Mar 07 12:57:12 PM PST 24 Mar 07 12:57:15 PM PST 24 16333143 ps
T832 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2197693187 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:01 PM PST 24 185153267 ps
T833 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3441986310 Mar 07 12:57:09 PM PST 24 Mar 07 12:57:11 PM PST 24 59292871 ps
T834 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1766431832 Mar 07 12:57:14 PM PST 24 Mar 07 12:57:15 PM PST 24 34129886 ps
T835 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1017945705 Mar 07 12:57:07 PM PST 24 Mar 07 12:57:08 PM PST 24 48877042 ps
T836 /workspace/coverage/cover_reg_top/10.gpio_intr_test.4219374279 Mar 07 12:57:13 PM PST 24 Mar 07 12:57:15 PM PST 24 38676238 ps
T837 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2782214465 Mar 07 12:57:07 PM PST 24 Mar 07 12:57:09 PM PST 24 513754910 ps
T838 /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2850996003 Mar 07 12:57:07 PM PST 24 Mar 07 12:57:09 PM PST 24 14881139 ps
T839 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3347961514 Mar 07 12:56:49 PM PST 24 Mar 07 12:56:50 PM PST 24 40739603 ps
T840 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.27359316 Mar 07 12:57:15 PM PST 24 Mar 07 12:57:17 PM PST 24 75263712 ps
T841 /workspace/coverage/cover_reg_top/38.gpio_intr_test.2705773805 Mar 07 12:57:20 PM PST 24 Mar 07 12:57:21 PM PST 24 31547857 ps
T842 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2885731352 Mar 07 12:57:09 PM PST 24 Mar 07 12:57:11 PM PST 24 62929664 ps
T843 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2253275785 Mar 07 12:57:10 PM PST 24 Mar 07 12:57:12 PM PST 24 25942149 ps
T844 /workspace/coverage/cover_reg_top/22.gpio_intr_test.773103101 Mar 07 12:57:16 PM PST 24 Mar 07 12:57:26 PM PST 24 35949438 ps
T845 /workspace/coverage/cover_reg_top/23.gpio_intr_test.3166558387 Mar 07 12:57:17 PM PST 24 Mar 07 12:57:18 PM PST 24 105891247 ps
T846 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1789377743 Mar 07 12:57:23 PM PST 24 Mar 07 12:57:24 PM PST 24 24887721 ps
T847 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.657682638 Mar 07 12:56:55 PM PST 24 Mar 07 12:56:56 PM PST 24 110227336 ps
T848 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2075656543 Mar 07 12:57:13 PM PST 24 Mar 07 12:57:15 PM PST 24 90862808 ps
T849 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3210427179 Mar 07 12:57:05 PM PST 24 Mar 07 12:57:08 PM PST 24 307820067 ps
T850 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3758040138 Mar 07 12:56:58 PM PST 24 Mar 07 12:56:59 PM PST 24 153528768 ps
T851 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.31773416 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:44 PM PST 24 42158468 ps
T852 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.412653875 Mar 07 12:56:52 PM PST 24 Mar 07 12:56:58 PM PST 24 78047368 ps
T853 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1099332185 Mar 07 12:56:39 PM PST 24 Mar 07 12:56:40 PM PST 24 31003367 ps
T854 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.789399079 Mar 07 12:57:05 PM PST 24 Mar 07 12:57:08 PM PST 24 128987021 ps
T855 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2750899 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:55 PM PST 24 54814616 ps
T856 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4226471030 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:00 PM PST 24 95428554 ps
T857 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2367905299 Mar 07 12:56:56 PM PST 24 Mar 07 12:56:57 PM PST 24 493407753 ps
T858 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2498188199 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:44 PM PST 24 47533102 ps
T859 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.510988734 Mar 07 12:57:12 PM PST 24 Mar 07 12:57:15 PM PST 24 56923584 ps
T860 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2083720287 Mar 07 12:57:01 PM PST 24 Mar 07 12:57:03 PM PST 24 153255283 ps
T861 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1648561111 Mar 07 12:57:00 PM PST 24 Mar 07 12:57:01 PM PST 24 28611281 ps
T862 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.31412138 Mar 07 12:57:00 PM PST 24 Mar 07 12:57:02 PM PST 24 348666777 ps
T863 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4057565196 Mar 07 12:57:14 PM PST 24 Mar 07 12:57:16 PM PST 24 223120274 ps
T864 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.147383005 Mar 07 12:56:51 PM PST 24 Mar 07 12:56:52 PM PST 24 43629727 ps
T865 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2701731107 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:01 PM PST 24 437254579 ps
T866 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.906691883 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:00 PM PST 24 381971932 ps
T867 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3713333639 Mar 07 12:57:07 PM PST 24 Mar 07 12:57:11 PM PST 24 36324335 ps
T868 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1616241757 Mar 07 12:56:47 PM PST 24 Mar 07 12:56:48 PM PST 24 166543178 ps
T869 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1489009681 Mar 07 12:56:52 PM PST 24 Mar 07 12:56:53 PM PST 24 33550790 ps
T870 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.196582941 Mar 07 12:57:09 PM PST 24 Mar 07 12:57:11 PM PST 24 233882762 ps
T871 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.997989399 Mar 07 12:57:02 PM PST 24 Mar 07 12:57:03 PM PST 24 175126336 ps
T872 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4240210426 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:45 PM PST 24 242047540 ps
T873 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3459576786 Mar 07 12:57:00 PM PST 24 Mar 07 12:57:02 PM PST 24 92014390 ps
T874 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3408100960 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:43 PM PST 24 88964548 ps
T875 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.751981323 Mar 07 12:56:39 PM PST 24 Mar 07 12:56:40 PM PST 24 131630929 ps
T876 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3997507081 Mar 07 12:57:07 PM PST 24 Mar 07 12:57:10 PM PST 24 55667489 ps
T877 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.616029906 Mar 07 12:57:03 PM PST 24 Mar 07 12:57:05 PM PST 24 176982689 ps
T878 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3918674986 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:00 PM PST 24 167402038 ps
T879 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2379698763 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:44 PM PST 24 921022633 ps
T880 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2040121181 Mar 07 12:56:53 PM PST 24 Mar 07 12:56:55 PM PST 24 154504564 ps
T881 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2035661273 Mar 07 12:57:03 PM PST 24 Mar 07 12:57:05 PM PST 24 71919374 ps
T882 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1682630256 Mar 07 12:56:41 PM PST 24 Mar 07 12:56:42 PM PST 24 59307154 ps
T883 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2876909313 Mar 07 12:56:47 PM PST 24 Mar 07 12:56:48 PM PST 24 224099695 ps
T884 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.492783631 Mar 07 12:57:06 PM PST 24 Mar 07 12:57:09 PM PST 24 170292230 ps
T885 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466901795 Mar 07 12:56:53 PM PST 24 Mar 07 12:56:55 PM PST 24 959093480 ps
T886 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1898421643 Mar 07 12:57:12 PM PST 24 Mar 07 12:57:14 PM PST 24 57126910 ps
T887 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3890195161 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:45 PM PST 24 279806835 ps
T888 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1661825288 Mar 07 12:56:41 PM PST 24 Mar 07 12:56:42 PM PST 24 83841898 ps
T889 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3832030103 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:43 PM PST 24 49272784 ps
T890 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3158250068 Mar 07 12:57:13 PM PST 24 Mar 07 12:57:15 PM PST 24 107778326 ps
T891 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1968726806 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:45 PM PST 24 119777726 ps
T892 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.192360502 Mar 07 12:56:55 PM PST 24 Mar 07 12:56:56 PM PST 24 20158909 ps
T893 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3080267250 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:44 PM PST 24 127238612 ps
T894 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1932030345 Mar 07 12:57:15 PM PST 24 Mar 07 12:57:17 PM PST 24 69373293 ps
T895 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3561624825 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:00 PM PST 24 201730576 ps
T896 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1525562005 Mar 07 12:56:40 PM PST 24 Mar 07 12:56:42 PM PST 24 49614336 ps
T897 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2913513146 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:45 PM PST 24 383231261 ps
T898 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.477631782 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:01 PM PST 24 125105843 ps
T899 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.916188127 Mar 07 12:56:45 PM PST 24 Mar 07 12:56:47 PM PST 24 53212106 ps
T900 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1684862925 Mar 07 12:56:49 PM PST 24 Mar 07 12:56:50 PM PST 24 125364838 ps
T901 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2639452953 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:00 PM PST 24 75682635 ps
T902 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.777134853 Mar 07 12:57:00 PM PST 24 Mar 07 12:57:01 PM PST 24 32119121 ps
T903 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3527338557 Mar 07 12:56:53 PM PST 24 Mar 07 12:56:55 PM PST 24 295917343 ps
T904 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3891714638 Mar 07 12:57:05 PM PST 24 Mar 07 12:57:07 PM PST 24 289560298 ps
T905 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.293663412 Mar 07 12:56:40 PM PST 24 Mar 07 12:56:41 PM PST 24 56772395 ps
T906 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4289825791 Mar 07 12:56:55 PM PST 24 Mar 07 12:56:57 PM PST 24 73154093 ps
T907 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2594156465 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:43 PM PST 24 92507617 ps
T908 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.93855331 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:44 PM PST 24 179928379 ps
T909 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.233175201 Mar 07 12:56:54 PM PST 24 Mar 07 12:56:55 PM PST 24 230890844 ps
T910 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3512855371 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:43 PM PST 24 111197822 ps
T911 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2532957638 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:44 PM PST 24 78865158 ps
T912 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.234887249 Mar 07 12:56:55 PM PST 24 Mar 07 12:56:56 PM PST 24 219291300 ps
T913 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3895864457 Mar 07 12:56:49 PM PST 24 Mar 07 12:56:51 PM PST 24 57856142 ps
T914 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1320314566 Mar 07 12:56:56 PM PST 24 Mar 07 12:56:57 PM PST 24 21826646 ps
T915 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2983244753 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:00 PM PST 24 39088159 ps
T916 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.905201829 Mar 07 12:56:47 PM PST 24 Mar 07 12:56:48 PM PST 24 115888110 ps
T917 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3856978679 Mar 07 12:56:40 PM PST 24 Mar 07 12:56:41 PM PST 24 60786938 ps
T918 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3049205283 Mar 07 12:56:56 PM PST 24 Mar 07 12:56:57 PM PST 24 39882884 ps
T919 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2164579054 Mar 07 12:56:56 PM PST 24 Mar 07 12:56:57 PM PST 24 129080311 ps
T920 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3067163647 Mar 07 12:57:01 PM PST 24 Mar 07 12:57:03 PM PST 24 304488202 ps
T921 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.308652065 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:45 PM PST 24 171738552 ps
T922 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.61226092 Mar 07 12:56:53 PM PST 24 Mar 07 12:56:54 PM PST 24 69108250 ps
T923 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3163549615 Mar 07 12:56:47 PM PST 24 Mar 07 12:56:49 PM PST 24 160733794 ps
T924 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3819925204 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:45 PM PST 24 254870147 ps
T925 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1118512964 Mar 07 12:56:44 PM PST 24 Mar 07 12:56:46 PM PST 24 395035943 ps
T926 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2792206342 Mar 07 12:56:44 PM PST 24 Mar 07 12:56:45 PM PST 24 306062180 ps
T927 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3212331545 Mar 07 12:57:01 PM PST 24 Mar 07 12:57:02 PM PST 24 51228329 ps
T928 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1063077898 Mar 07 12:56:53 PM PST 24 Mar 07 12:56:54 PM PST 24 255062121 ps
T929 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.386940045 Mar 07 12:56:39 PM PST 24 Mar 07 12:56:41 PM PST 24 76408173 ps
T930 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3399638430 Mar 07 12:56:56 PM PST 24 Mar 07 12:56:57 PM PST 24 243386725 ps
T931 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3062281932 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:01 PM PST 24 52897579 ps
T932 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2037156121 Mar 07 12:56:44 PM PST 24 Mar 07 12:56:45 PM PST 24 93328596 ps
T933 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1068014091 Mar 07 12:56:39 PM PST 24 Mar 07 12:56:41 PM PST 24 116693025 ps
T934 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.319111395 Mar 07 12:56:58 PM PST 24 Mar 07 12:56:59 PM PST 24 140307683 ps
T935 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.818198190 Mar 07 12:57:07 PM PST 24 Mar 07 12:57:09 PM PST 24 103441842 ps
T936 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.374528054 Mar 07 12:56:40 PM PST 24 Mar 07 12:56:42 PM PST 24 120250688 ps
T937 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2845836806 Mar 07 12:57:05 PM PST 24 Mar 07 12:57:08 PM PST 24 327988729 ps
T938 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2744766177 Mar 07 12:56:44 PM PST 24 Mar 07 12:56:45 PM PST 24 110217166 ps
T939 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2988276830 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:00 PM PST 24 29509178 ps
T940 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1720109385 Mar 07 12:56:59 PM PST 24 Mar 07 12:57:00 PM PST 24 33811532 ps
T941 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.490865953 Mar 07 12:56:44 PM PST 24 Mar 07 12:56:46 PM PST 24 390562583 ps
T942 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1875764982 Mar 07 12:56:42 PM PST 24 Mar 07 12:56:43 PM PST 24 40002095 ps
T943 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.388951204 Mar 07 12:57:00 PM PST 24 Mar 07 12:57:02 PM PST 24 345722475 ps
T944 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4215374082 Mar 07 12:57:13 PM PST 24 Mar 07 12:57:16 PM PST 24 178912123 ps
T945 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.151526536 Mar 07 12:56:38 PM PST 24 Mar 07 12:56:40 PM PST 24 102192656 ps
T946 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.875350509 Mar 07 12:56:43 PM PST 24 Mar 07 12:56:50 PM PST 24 110380116 ps

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3556591837
Short name T29
Test name
Test status
Simulation time 419424471 ps
CPU time 7.08 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:43 PM PST 24
Peak memory 198004 kb
Host smart-1bbe7dcd-fddf-456e-9ad4-90f893b79e8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556591837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3556591837
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3341916808
Short name T34
Test name
Test status
Simulation time 54698638 ps
CPU time 2.23 seconds
Started Mar 07 01:21:22 PM PST 24
Finished Mar 07 01:21:25 PM PST 24
Peak memory 198044 kb
Host smart-ad9c2de4-5849-49a2-ae1c-d62bc972129f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341916808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3341916808
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3563250665
Short name T31
Test name
Test status
Simulation time 131001675490 ps
CPU time 1284.19 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:42:12 PM PST 24
Peak memory 198468 kb
Host smart-ade2c7a5-3946-4ba1-8f9e-fd0c5218d9ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3563250665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3563250665
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1788322341
Short name T40
Test name
Test status
Simulation time 73671076 ps
CPU time 0.9 seconds
Started Mar 07 01:20:02 PM PST 24
Finished Mar 07 01:20:03 PM PST 24
Peak memory 213880 kb
Host smart-a7d50021-9fb6-424f-a9f1-c437adcd334d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788322341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1788322341
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.4219530335
Short name T86
Test name
Test status
Simulation time 79083448 ps
CPU time 0.67 seconds
Started Mar 07 12:56:58 PM PST 24
Finished Mar 07 12:56:58 PM PST 24
Peak memory 196180 kb
Host smart-f254a4ec-ee55-4208-a0cc-8d8a04e6e5a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219530335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.4219530335
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.4272411674
Short name T1
Test name
Test status
Simulation time 1919700612 ps
CPU time 5.8 seconds
Started Mar 07 01:20:23 PM PST 24
Finished Mar 07 01:20:30 PM PST 24
Peak memory 198140 kb
Host smart-95eb5fb7-5d39-4a32-81a2-b75f697af5c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272411674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.4272411674
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2233785608
Short name T49
Test name
Test status
Simulation time 118788791 ps
CPU time 1.48 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 198596 kb
Host smart-f3ac04b1-0f5a-440c-b168-59baba1f89b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233785608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2233785608
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/17.gpio_alert_test.441546950
Short name T19
Test name
Test status
Simulation time 17754547 ps
CPU time 0.56 seconds
Started Mar 07 01:20:50 PM PST 24
Finished Mar 07 01:20:50 PM PST 24
Peak memory 194040 kb
Host smart-32ae04e1-e584-4e83-b3b6-3b67d09c2dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441546950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.441546950
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.2071647527
Short name T83
Test name
Test status
Simulation time 88257291 ps
CPU time 0.72 seconds
Started Mar 07 12:57:14 PM PST 24
Finished Mar 07 12:57:16 PM PST 24
Peak memory 196608 kb
Host smart-4337b9c6-2e5e-4d58-9aa0-65cc8169124e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071647527 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.2071647527
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.27359316
Short name T840
Test name
Test status
Simulation time 75263712 ps
CPU time 1.23 seconds
Started Mar 07 12:57:15 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 198500 kb
Host smart-19f8df11-3441-48b2-b63b-0bf0fa7e6b4e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27359316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.gpio_tl_intg_err.27359316
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.1441129189
Short name T118
Test name
Test status
Simulation time 49783295 ps
CPU time 0.85 seconds
Started Mar 07 12:56:40 PM PST 24
Finished Mar 07 12:56:41 PM PST 24
Peak memory 196660 kb
Host smart-ca3b37b5-a1c7-4a07-b8ca-73b40f6778fa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441129189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.1441129189
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1202154313
Short name T786
Test name
Test status
Simulation time 59483652 ps
CPU time 2.14 seconds
Started Mar 07 12:56:41 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 197464 kb
Host smart-32002db4-4995-47cc-83c7-a8f6a37b6ff6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202154313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1202154313
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4221551330
Short name T760
Test name
Test status
Simulation time 336987850 ps
CPU time 0.66 seconds
Started Mar 07 12:57:02 PM PST 24
Finished Mar 07 12:57:03 PM PST 24
Peak memory 195376 kb
Host smart-84850e5f-c0c0-4d68-8120-ae6c2f6e6e5d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221551330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.4221551330
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2392983865
Short name T799
Test name
Test status
Simulation time 288338396 ps
CPU time 0.74 seconds
Started Mar 07 12:57:03 PM PST 24
Finished Mar 07 12:57:04 PM PST 24
Peak memory 198480 kb
Host smart-8f25a969-6f06-463d-8e82-0343d160637f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392983865 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2392983865
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.1017945705
Short name T835
Test name
Test status
Simulation time 48877042 ps
CPU time 0.6 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:08 PM PST 24
Peak memory 195428 kb
Host smart-0f2dd157-6837-4c66-84de-7185cc61b6c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017945705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.1017945705
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1076189954
Short name T779
Test name
Test status
Simulation time 37401336 ps
CPU time 0.66 seconds
Started Mar 07 12:57:05 PM PST 24
Finished Mar 07 12:57:07 PM PST 24
Peak memory 194220 kb
Host smart-6bbcaaa7-78af-48e3-bbcb-c15a948a56ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076189954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1076189954
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.4091139857
Short name T804
Test name
Test status
Simulation time 59090644 ps
CPU time 0.74 seconds
Started Mar 07 12:57:01 PM PST 24
Finished Mar 07 12:57:02 PM PST 24
Peak memory 196764 kb
Host smart-d4e8196d-d05d-45ac-abdb-4d4e855e5a85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091139857 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.4091139857
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1959216810
Short name T762
Test name
Test status
Simulation time 163730182 ps
CPU time 2.22 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 198588 kb
Host smart-ac820d75-1aac-4523-b724-e451725aa130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959216810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1959216810
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.511649990
Short name T47
Test name
Test status
Simulation time 45046902 ps
CPU time 0.88 seconds
Started Mar 07 12:56:46 PM PST 24
Finished Mar 07 12:56:47 PM PST 24
Peak memory 197416 kb
Host smart-7a4b8eb5-4955-4e0b-91af-a12970200bea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511649990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 0.gpio_tl_intg_err.511649990
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2167755309
Short name T749
Test name
Test status
Simulation time 135023750 ps
CPU time 0.87 seconds
Started Mar 07 12:56:49 PM PST 24
Finished Mar 07 12:56:50 PM PST 24
Peak memory 196496 kb
Host smart-a7f77aaa-e174-456f-93f3-d5e76f8233c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167755309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2167755309
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.734729368
Short name T766
Test name
Test status
Simulation time 253460563 ps
CPU time 2.41 seconds
Started Mar 07 12:56:58 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 197588 kb
Host smart-519cba1c-a4d3-4fd3-a5a7-7c9af2648af5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734729368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.734729368
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2182032523
Short name T722
Test name
Test status
Simulation time 60981437 ps
CPU time 0.7 seconds
Started Mar 07 12:56:45 PM PST 24
Finished Mar 07 12:56:47 PM PST 24
Peak memory 198400 kb
Host smart-5873bf38-a538-4b99-b6df-053a76fb76fb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182032523 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2182032523
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1840647775
Short name T96
Test name
Test status
Simulation time 89499833 ps
CPU time 0.59 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:48 PM PST 24
Peak memory 195276 kb
Host smart-122390bf-a1f6-4d36-8454-10f7b3e72bad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840647775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1840647775
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1361838518
Short name T827
Test name
Test status
Simulation time 45273870 ps
CPU time 0.57 seconds
Started Mar 07 12:56:51 PM PST 24
Finished Mar 07 12:56:52 PM PST 24
Peak memory 194168 kb
Host smart-ff8b8178-272b-4dad-a7de-0b5cc927577c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361838518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1361838518
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3828883816
Short name T809
Test name
Test status
Simulation time 40865691 ps
CPU time 0.64 seconds
Started Mar 07 12:57:10 PM PST 24
Finished Mar 07 12:57:12 PM PST 24
Peak memory 195012 kb
Host smart-09d1f191-d54f-437a-856d-e0b66f57e8e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828883816 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3828883816
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2272866887
Short name T813
Test name
Test status
Simulation time 44778257 ps
CPU time 0.96 seconds
Started Mar 07 12:56:52 PM PST 24
Finished Mar 07 12:56:53 PM PST 24
Peak memory 198436 kb
Host smart-127a4d2c-b7fb-4044-88b1-11970144a745
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272866887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2272866887
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3438104201
Short name T732
Test name
Test status
Simulation time 22780287 ps
CPU time 1.03 seconds
Started Mar 07 12:57:23 PM PST 24
Finished Mar 07 12:57:24 PM PST 24
Peak memory 198496 kb
Host smart-50d18f0a-a003-4cf3-bd5a-1faea85b4edd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438104201 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3438104201
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2850996003
Short name T838
Test name
Test status
Simulation time 14881139 ps
CPU time 0.62 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:09 PM PST 24
Peak memory 195916 kb
Host smart-fcdb91c2-1c75-4c61-bc68-9d63fa1b351a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850996003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2850996003
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.4219374279
Short name T836
Test name
Test status
Simulation time 38676238 ps
CPU time 0.6 seconds
Started Mar 07 12:57:13 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 194160 kb
Host smart-3ad7617f-8b65-43a5-a2e0-19283ab2c359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219374279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.4219374279
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.3630971840
Short name T767
Test name
Test status
Simulation time 226758698 ps
CPU time 1.13 seconds
Started Mar 07 12:57:11 PM PST 24
Finished Mar 07 12:57:14 PM PST 24
Peak memory 198620 kb
Host smart-d5e12853-7a61-49e5-a73c-1a057e722c3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630971840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.3630971840
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.1337104815
Short name T765
Test name
Test status
Simulation time 71778941 ps
CPU time 1.11 seconds
Started Mar 07 12:57:03 PM PST 24
Finished Mar 07 12:57:04 PM PST 24
Peak memory 198564 kb
Host smart-3db6d1c0-3f71-49b2-864e-48758b44293a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337104815 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.1337104815
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.2256276487
Short name T97
Test name
Test status
Simulation time 43791754 ps
CPU time 0.65 seconds
Started Mar 07 12:57:14 PM PST 24
Finished Mar 07 12:57:16 PM PST 24
Peak memory 196208 kb
Host smart-9a39c4e7-9dec-4a1f-bbe2-1735282a2feb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256276487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.2256276487
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2458664102
Short name T814
Test name
Test status
Simulation time 27851589 ps
CPU time 0.63 seconds
Started Mar 07 12:57:09 PM PST 24
Finished Mar 07 12:57:11 PM PST 24
Peak memory 194972 kb
Host smart-7a080562-0772-4d2c-904d-83fecdf5c8df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458664102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2458664102
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2680643235
Short name T106
Test name
Test status
Simulation time 19548813 ps
CPU time 0.66 seconds
Started Mar 07 12:57:06 PM PST 24
Finished Mar 07 12:57:09 PM PST 24
Peak memory 195512 kb
Host smart-24566729-7804-494c-bcbf-924cbddb920d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680643235 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2680643235
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.591459236
Short name T789
Test name
Test status
Simulation time 311134496 ps
CPU time 1.86 seconds
Started Mar 07 12:56:57 PM PST 24
Finished Mar 07 12:56:59 PM PST 24
Peak memory 198612 kb
Host smart-d56f5ee7-0a4e-49cb-93e3-f6024b8903e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591459236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.591459236
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.604294271
Short name T768
Test name
Test status
Simulation time 106666621 ps
CPU time 1.45 seconds
Started Mar 07 12:57:15 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 198576 kb
Host smart-986caf1d-f739-4ce7-b5b8-cfb5c9c8897f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604294271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.604294271
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.3363170602
Short name T727
Test name
Test status
Simulation time 66237745 ps
CPU time 0.9 seconds
Started Mar 07 12:57:03 PM PST 24
Finished Mar 07 12:57:04 PM PST 24
Peak memory 198416 kb
Host smart-29fb4f4e-ea5e-4953-b71b-17ef63adb4cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363170602 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.3363170602
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.1721442882
Short name T806
Test name
Test status
Simulation time 43350563 ps
CPU time 0.6 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:14 PM PST 24
Peak memory 195056 kb
Host smart-81286948-c327-4742-894e-4d9c77c55efb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721442882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.1721442882
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.985096592
Short name T764
Test name
Test status
Simulation time 15022334 ps
CPU time 0.59 seconds
Started Mar 07 12:57:14 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 194136 kb
Host smart-d78a2cd2-f07f-447d-b90e-0c45fb78f818
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985096592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.985096592
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.509290738
Short name T107
Test name
Test status
Simulation time 453864052 ps
CPU time 0.85 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:14 PM PST 24
Peak memory 197092 kb
Host smart-4a82dd7e-324a-4e24-8244-724c9b8f39ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509290738 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.509290738
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.714536223
Short name T743
Test name
Test status
Simulation time 46440133 ps
CPU time 1.29 seconds
Started Mar 07 12:57:06 PM PST 24
Finished Mar 07 12:57:09 PM PST 24
Peak memory 198600 kb
Host smart-87fc8bdf-fe33-41ca-9327-4eb9b8453b51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714536223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.714536223
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.636774609
Short name T39
Test name
Test status
Simulation time 78760400 ps
CPU time 1.17 seconds
Started Mar 07 12:57:10 PM PST 24
Finished Mar 07 12:57:12 PM PST 24
Peak memory 198568 kb
Host smart-02122ac8-2402-4412-97d1-1cc54062ba19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636774609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.636774609
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.4033044117
Short name T736
Test name
Test status
Simulation time 18023252 ps
CPU time 0.67 seconds
Started Mar 07 12:57:15 PM PST 24
Finished Mar 07 12:57:16 PM PST 24
Peak memory 197692 kb
Host smart-adaabaee-fd19-421f-ac1e-b132c3349b13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033044117 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.4033044117
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.785996992
Short name T777
Test name
Test status
Simulation time 29726891 ps
CPU time 0.6 seconds
Started Mar 07 12:57:32 PM PST 24
Finished Mar 07 12:57:32 PM PST 24
Peak memory 195436 kb
Host smart-9140a91d-ecec-4b3e-bdf6-2576f1cf2e9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785996992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio
_csr_rw.785996992
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2471220789
Short name T746
Test name
Test status
Simulation time 19806904 ps
CPU time 0.58 seconds
Started Mar 07 12:57:09 PM PST 24
Finished Mar 07 12:57:11 PM PST 24
Peak memory 194184 kb
Host smart-578c2730-d4e0-4dce-a077-1906d6d9dcba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471220789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2471220789
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2458359334
Short name T831
Test name
Test status
Simulation time 16333143 ps
CPU time 0.74 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 197220 kb
Host smart-6fcb6cf0-ba20-475f-b4fb-bcfafc147e11
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458359334 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2458359334
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1493635212
Short name T792
Test name
Test status
Simulation time 74924892 ps
CPU time 1.09 seconds
Started Mar 07 12:57:14 PM PST 24
Finished Mar 07 12:57:16 PM PST 24
Peak memory 198308 kb
Host smart-1f65ef96-e0f9-415b-8bae-17c08fcc5030
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493635212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1493635212
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.690918239
Short name T816
Test name
Test status
Simulation time 561338263 ps
CPU time 0.9 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 197636 kb
Host smart-ccbfd258-cd4c-4fde-ab76-b424cdfde5f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690918239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 13.gpio_tl_intg_err.690918239
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.2253275785
Short name T843
Test name
Test status
Simulation time 25942149 ps
CPU time 0.76 seconds
Started Mar 07 12:57:10 PM PST 24
Finished Mar 07 12:57:12 PM PST 24
Peak memory 198332 kb
Host smart-5ab42839-3c1c-4f2d-92cc-e118eb341462
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253275785 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.2253275785
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4263225197
Short name T90
Test name
Test status
Simulation time 47253120 ps
CPU time 0.59 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:14 PM PST 24
Peak memory 195580 kb
Host smart-4e3fe9b6-0f4b-453d-9d86-a76c55dc73e8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263225197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.4263225197
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.3193295066
Short name T751
Test name
Test status
Simulation time 15968865 ps
CPU time 0.59 seconds
Started Mar 07 12:57:11 PM PST 24
Finished Mar 07 12:57:13 PM PST 24
Peak memory 194956 kb
Host smart-1719ce88-6eee-493e-9f3d-309ade304c6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193295066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.3193295066
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3514062015
Short name T105
Test name
Test status
Simulation time 32589494 ps
CPU time 0.73 seconds
Started Mar 07 12:57:08 PM PST 24
Finished Mar 07 12:57:10 PM PST 24
Peak memory 195640 kb
Host smart-6710ffc8-d83e-49a7-8130-a2f62021c271
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514062015 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3514062015
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.2430308239
Short name T733
Test name
Test status
Simulation time 62909802 ps
CPU time 1.71 seconds
Started Mar 07 12:57:14 PM PST 24
Finished Mar 07 12:57:16 PM PST 24
Peak memory 198620 kb
Host smart-a7a2c3b3-8351-4a50-ba76-3effb6eb1d41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430308239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.2430308239
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.881674061
Short name T797
Test name
Test status
Simulation time 813542498 ps
CPU time 1.39 seconds
Started Mar 07 12:57:20 PM PST 24
Finished Mar 07 12:57:22 PM PST 24
Peak memory 198568 kb
Host smart-dc74f6e1-1623-41fa-a730-c9c581fd4748
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881674061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.881674061
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.4030528053
Short name T750
Test name
Test status
Simulation time 93524448 ps
CPU time 0.72 seconds
Started Mar 07 12:57:20 PM PST 24
Finished Mar 07 12:57:22 PM PST 24
Peak memory 197904 kb
Host smart-2c114aeb-231d-4b4f-b302-c1c0fc71225f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030528053 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.4030528053
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2023299689
Short name T88
Test name
Test status
Simulation time 55889517 ps
CPU time 0.64 seconds
Started Mar 07 12:57:14 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 195492 kb
Host smart-699e0524-0725-4ec7-96d3-bcc44bcc5df8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023299689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2023299689
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3718943292
Short name T757
Test name
Test status
Simulation time 15832506 ps
CPU time 0.61 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 194288 kb
Host smart-98017bce-e744-4e5b-b9d8-443c4e9b9e3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718943292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3718943292
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2131890452
Short name T103
Test name
Test status
Simulation time 69172460 ps
CPU time 0.86 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:09 PM PST 24
Peak memory 197728 kb
Host smart-4b60864d-396b-4c96-9fd7-4cec1bfacb34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131890452 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2131890452
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3186040044
Short name T828
Test name
Test status
Simulation time 43803462 ps
CPU time 2.19 seconds
Started Mar 07 12:57:04 PM PST 24
Finished Mar 07 12:57:07 PM PST 24
Peak memory 198700 kb
Host smart-33ce7ee1-ccbe-4f65-a0ac-b21ce8f8fe8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186040044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3186040044
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1191746018
Short name T48
Test name
Test status
Simulation time 465281292 ps
CPU time 1.26 seconds
Started Mar 07 12:57:10 PM PST 24
Finished Mar 07 12:57:13 PM PST 24
Peak memory 198500 kb
Host smart-63a27d4b-d91d-432c-bfb7-356002f53a6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191746018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1191746018
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2950942737
Short name T731
Test name
Test status
Simulation time 60960686 ps
CPU time 0.94 seconds
Started Mar 07 12:57:09 PM PST 24
Finished Mar 07 12:57:11 PM PST 24
Peak memory 198468 kb
Host smart-fd86aa02-b320-4073-85b5-70aa44e0cd52
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950942737 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2950942737
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3155493231
Short name T95
Test name
Test status
Simulation time 44906460 ps
CPU time 0.6 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:18 PM PST 24
Peak memory 195268 kb
Host smart-db8d278e-15e3-4f79-9bb9-7515d09379a6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155493231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3155493231
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.303497799
Short name T756
Test name
Test status
Simulation time 21917350 ps
CPU time 0.57 seconds
Started Mar 07 12:57:15 PM PST 24
Finished Mar 07 12:57:16 PM PST 24
Peak memory 194140 kb
Host smart-355d7961-cac8-4a94-bad9-50d10bdbdfd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303497799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.303497799
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2795132052
Short name T87
Test name
Test status
Simulation time 21764777 ps
CPU time 0.81 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 197648 kb
Host smart-3c261a61-9ba4-4e08-b06a-9f2666f36d8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795132052 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2795132052
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.4264440698
Short name T808
Test name
Test status
Simulation time 49529557 ps
CPU time 2.48 seconds
Started Mar 07 12:57:08 PM PST 24
Finished Mar 07 12:57:12 PM PST 24
Peak memory 198564 kb
Host smart-5f19563d-f754-49c2-a896-6d9a1d9c2b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264440698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.4264440698
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.4191269369
Short name T37
Test name
Test status
Simulation time 159770241 ps
CPU time 0.83 seconds
Started Mar 07 12:57:20 PM PST 24
Finished Mar 07 12:57:21 PM PST 24
Peak memory 198264 kb
Host smart-e78ab2e1-9932-473c-ba4b-556874e414d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191269369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.4191269369
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3150828004
Short name T723
Test name
Test status
Simulation time 120102396 ps
CPU time 0.89 seconds
Started Mar 07 12:57:18 PM PST 24
Finished Mar 07 12:57:19 PM PST 24
Peak memory 198500 kb
Host smart-66b8c94d-e2d4-42e4-b594-a651f1eb0af6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150828004 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3150828004
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.862316143
Short name T82
Test name
Test status
Simulation time 74888309 ps
CPU time 0.59 seconds
Started Mar 07 12:57:00 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 195356 kb
Host smart-f2fd6b8a-1eb5-4f31-b9c7-dc6c1ddb2f26
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862316143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.862316143
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3225641710
Short name T761
Test name
Test status
Simulation time 13468132 ps
CPU time 0.61 seconds
Started Mar 07 12:57:04 PM PST 24
Finished Mar 07 12:57:05 PM PST 24
Peak memory 194196 kb
Host smart-8b4d8f5d-5992-4657-8842-c4d4aebb3016
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225641710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3225641710
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.1147250066
Short name T803
Test name
Test status
Simulation time 25286829 ps
CPU time 0.75 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:09 PM PST 24
Peak memory 196748 kb
Host smart-b97f2df2-6429-4e7c-b9fe-898b324c8d03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147250066 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.1147250066
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1354815609
Short name T796
Test name
Test status
Simulation time 71092052 ps
CPU time 1.63 seconds
Started Mar 07 12:57:22 PM PST 24
Finished Mar 07 12:57:24 PM PST 24
Peak memory 198612 kb
Host smart-ff358a3d-c6a7-4b3f-b2f8-2e89cd7e69e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354815609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1354815609
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3876270750
Short name T776
Test name
Test status
Simulation time 321659191 ps
CPU time 1.19 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 198620 kb
Host smart-e3d2f4a4-c8aa-47b7-b1d7-84183b993b0f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876270750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3876270750
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1472546805
Short name T798
Test name
Test status
Simulation time 14163733 ps
CPU time 0.67 seconds
Started Mar 07 12:57:02 PM PST 24
Finished Mar 07 12:57:02 PM PST 24
Peak memory 197688 kb
Host smart-f1040330-f072-4d9f-b6e9-22d12acc811e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472546805 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1472546805
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3431929964
Short name T823
Test name
Test status
Simulation time 14804119 ps
CPU time 0.59 seconds
Started Mar 07 12:57:27 PM PST 24
Finished Mar 07 12:57:28 PM PST 24
Peak memory 195856 kb
Host smart-fb1658f7-71f7-4556-9200-240d6c078f06
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431929964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3431929964
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2990611063
Short name T801
Test name
Test status
Simulation time 55086060 ps
CPU time 0.59 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:09 PM PST 24
Peak memory 194312 kb
Host smart-ff45cf55-1ab4-41fe-8aac-cce21f2aa567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990611063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2990611063
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2885731352
Short name T842
Test name
Test status
Simulation time 62929664 ps
CPU time 0.84 seconds
Started Mar 07 12:57:09 PM PST 24
Finished Mar 07 12:57:11 PM PST 24
Peak memory 197624 kb
Host smart-8250f1dd-7b5c-4be8-8c02-2e58cd05949f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885731352 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2885731352
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.82492857
Short name T811
Test name
Test status
Simulation time 19668379 ps
CPU time 0.92 seconds
Started Mar 07 12:57:18 PM PST 24
Finished Mar 07 12:57:19 PM PST 24
Peak memory 198464 kb
Host smart-33db3071-d069-4b65-aa1f-33f65ac95e38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82492857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.82492857
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1123536023
Short name T38
Test name
Test status
Simulation time 153150377 ps
CPU time 1.1 seconds
Started Mar 07 12:57:26 PM PST 24
Finished Mar 07 12:57:27 PM PST 24
Peak memory 198616 kb
Host smart-4ae50804-edda-423b-99db-5c6f8e208e18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123536023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1123536023
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.4287573233
Short name T726
Test name
Test status
Simulation time 32684608 ps
CPU time 0.66 seconds
Started Mar 07 12:57:19 PM PST 24
Finished Mar 07 12:57:20 PM PST 24
Peak memory 197932 kb
Host smart-910ed835-0a70-4d9f-801d-cfd3636fc18a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287573233 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.4287573233
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2035967874
Short name T84
Test name
Test status
Simulation time 43389663 ps
CPU time 0.6 seconds
Started Mar 07 12:57:20 PM PST 24
Finished Mar 07 12:57:20 PM PST 24
Peak memory 196180 kb
Host smart-8dbd2e30-9af0-420c-84ba-6c96739e587d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035967874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2035967874
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.312288676
Short name T795
Test name
Test status
Simulation time 10557292 ps
CPU time 0.61 seconds
Started Mar 07 12:57:03 PM PST 24
Finished Mar 07 12:57:03 PM PST 24
Peak memory 194204 kb
Host smart-5c565eea-5061-40ef-bb78-989df555cd89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312288676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.312288676
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2250229703
Short name T805
Test name
Test status
Simulation time 123431913 ps
CPU time 0.75 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 197216 kb
Host smart-3da8ee9f-703d-4106-9893-34d5386b5645
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250229703 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2250229703
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.603245535
Short name T742
Test name
Test status
Simulation time 207086283 ps
CPU time 1.47 seconds
Started Mar 07 12:57:15 PM PST 24
Finished Mar 07 12:57:16 PM PST 24
Peak memory 198556 kb
Host smart-a6b76abe-e29d-4d22-9eb6-ce45f5a2e395
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603245535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.603245535
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2386731426
Short name T50
Test name
Test status
Simulation time 287864169 ps
CPU time 1.04 seconds
Started Mar 07 12:57:11 PM PST 24
Finished Mar 07 12:57:13 PM PST 24
Peak memory 198636 kb
Host smart-e4bd4976-5284-4552-a50d-4f4262de8e82
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386731426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2386731426
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1022178291
Short name T98
Test name
Test status
Simulation time 77441558 ps
CPU time 0.92 seconds
Started Mar 07 12:57:11 PM PST 24
Finished Mar 07 12:57:12 PM PST 24
Peak memory 196524 kb
Host smart-5d65ec9f-0059-485e-946a-5fdc3810f884
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022178291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1022178291
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2395898770
Short name T826
Test name
Test status
Simulation time 369119219 ps
CPU time 1.46 seconds
Started Mar 07 12:57:11 PM PST 24
Finished Mar 07 12:57:13 PM PST 24
Peak memory 197268 kb
Host smart-8124e510-c64c-4685-93b8-42053b4cc605
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395898770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2395898770
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3285194053
Short name T119
Test name
Test status
Simulation time 19117895 ps
CPU time 0.65 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:14 PM PST 24
Peak memory 195220 kb
Host smart-ceba86f4-73b4-42bf-9463-b69357eda00e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285194053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3285194053
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.4165338973
Short name T724
Test name
Test status
Simulation time 74135226 ps
CPU time 1.13 seconds
Started Mar 07 12:56:47 PM PST 24
Finished Mar 07 12:56:49 PM PST 24
Peak memory 198540 kb
Host smart-9128db1d-9ab4-4722-8163-89e775abec23
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165338973 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.4165338973
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2421586701
Short name T120
Test name
Test status
Simulation time 36911185 ps
CPU time 0.59 seconds
Started Mar 07 12:56:40 PM PST 24
Finished Mar 07 12:56:41 PM PST 24
Peak memory 195752 kb
Host smart-558bfed1-f16d-426c-b8f3-155e30cf4e91
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421586701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2421586701
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1482750763
Short name T754
Test name
Test status
Simulation time 19340282 ps
CPU time 0.57 seconds
Started Mar 07 12:56:51 PM PST 24
Finished Mar 07 12:56:52 PM PST 24
Peak memory 194216 kb
Host smart-357b82c5-91c4-439e-b6d8-564aa0bb44dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482750763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1482750763
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.505427107
Short name T101
Test name
Test status
Simulation time 18283565 ps
CPU time 0.9 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 198360 kb
Host smart-187180a6-8e14-487e-b9fe-edf3b7639992
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505427107 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 2.gpio_same_csr_outstanding.505427107
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3844675347
Short name T785
Test name
Test status
Simulation time 92693649 ps
CPU time 2.04 seconds
Started Mar 07 12:57:10 PM PST 24
Finished Mar 07 12:57:13 PM PST 24
Peak memory 198536 kb
Host smart-bc121afb-b148-4f8e-8760-0b3b8e00d6c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844675347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3844675347
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3347961514
Short name T839
Test name
Test status
Simulation time 40739603 ps
CPU time 0.88 seconds
Started Mar 07 12:56:49 PM PST 24
Finished Mar 07 12:56:50 PM PST 24
Peak memory 197764 kb
Host smart-33ae75a0-844a-4d98-a14a-d2e201cceff5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347961514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3347961514
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2319999337
Short name T725
Test name
Test status
Simulation time 14508503 ps
CPU time 0.6 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:09 PM PST 24
Peak memory 194204 kb
Host smart-9bb23400-1aea-4047-a5ec-4123f1499386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319999337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2319999337
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2634160392
Short name T830
Test name
Test status
Simulation time 10416158 ps
CPU time 0.59 seconds
Started Mar 07 12:57:26 PM PST 24
Finished Mar 07 12:57:27 PM PST 24
Peak memory 194852 kb
Host smart-b303c6aa-e52a-4aef-9d69-a0236142328b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634160392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2634160392
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.773103101
Short name T844
Test name
Test status
Simulation time 35949438 ps
CPU time 0.57 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:26 PM PST 24
Peak memory 194108 kb
Host smart-44a5a70e-d9fb-4ed4-aa77-242a1fc15562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773103101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.773103101
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3166558387
Short name T845
Test name
Test status
Simulation time 105891247 ps
CPU time 0.6 seconds
Started Mar 07 12:57:17 PM PST 24
Finished Mar 07 12:57:18 PM PST 24
Peak memory 194252 kb
Host smart-05d17ee9-a0ba-4ed1-b889-7ba169f9249b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166558387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3166558387
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.4005309523
Short name T769
Test name
Test status
Simulation time 55784037 ps
CPU time 0.57 seconds
Started Mar 07 12:57:13 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 194820 kb
Host smart-e444d998-3775-45c3-8cc2-903c16763823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005309523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.4005309523
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2655757387
Short name T739
Test name
Test status
Simulation time 14202166 ps
CPU time 0.59 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 194296 kb
Host smart-79c30eb9-d435-4f05-b692-7249077e093b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655757387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2655757387
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1766431832
Short name T834
Test name
Test status
Simulation time 34129886 ps
CPU time 0.59 seconds
Started Mar 07 12:57:14 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 194228 kb
Host smart-f9e8b4c4-df8d-4d88-8aee-c1b77a5dd250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766431832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1766431832
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1105367864
Short name T747
Test name
Test status
Simulation time 14862492 ps
CPU time 0.59 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 194836 kb
Host smart-1bf61b57-6266-450b-9133-85372b28db3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105367864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1105367864
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2420408479
Short name T744
Test name
Test status
Simulation time 20490929 ps
CPU time 0.6 seconds
Started Mar 07 12:57:08 PM PST 24
Finished Mar 07 12:57:10 PM PST 24
Peak memory 194848 kb
Host smart-ccfa9b55-f903-48db-adab-0632a03c752e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420408479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2420408479
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2331391258
Short name T807
Test name
Test status
Simulation time 14111482 ps
CPU time 0.61 seconds
Started Mar 07 12:57:24 PM PST 24
Finished Mar 07 12:57:25 PM PST 24
Peak memory 194860 kb
Host smart-fda0fa5b-9005-491f-a286-0a7283cdd825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331391258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2331391258
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.1486529939
Short name T91
Test name
Test status
Simulation time 19596986 ps
CPU time 0.68 seconds
Started Mar 07 12:57:06 PM PST 24
Finished Mar 07 12:57:08 PM PST 24
Peak memory 195560 kb
Host smart-6eaea4f2-6b0a-424d-ad8e-726a95fc9200
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486529939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.1486529939
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2243873149
Short name T741
Test name
Test status
Simulation time 408991511 ps
CPU time 2.1 seconds
Started Mar 07 12:56:54 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 196976 kb
Host smart-e9e944bb-7d05-4fc4-9e35-cd9b1f0e7740
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243873149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2243873149
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.1001090301
Short name T81
Test name
Test status
Simulation time 69273027 ps
CPU time 0.65 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:43 PM PST 24
Peak memory 195504 kb
Host smart-212e31fe-19e7-4d35-b60e-871e33636c9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001090301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.1001090301
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3262038357
Short name T729
Test name
Test status
Simulation time 21417848 ps
CPU time 0.67 seconds
Started Mar 07 12:56:55 PM PST 24
Finished Mar 07 12:56:56 PM PST 24
Peak memory 198000 kb
Host smart-4401daf1-7bf8-4b2a-bc4b-bdec8f912896
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262038357 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3262038357
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3015269176
Short name T753
Test name
Test status
Simulation time 11161192 ps
CPU time 0.59 seconds
Started Mar 07 12:57:05 PM PST 24
Finished Mar 07 12:57:06 PM PST 24
Peak memory 195108 kb
Host smart-c0873ae3-2d1b-4005-8094-743c6e7f6b18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015269176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3015269176
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3441986310
Short name T833
Test name
Test status
Simulation time 59292871 ps
CPU time 0.64 seconds
Started Mar 07 12:57:09 PM PST 24
Finished Mar 07 12:57:11 PM PST 24
Peak memory 194884 kb
Host smart-10a8098e-ec12-418f-9052-ba42056105ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441986310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3441986310
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2570458044
Short name T818
Test name
Test status
Simulation time 64762889 ps
CPU time 0.59 seconds
Started Mar 07 12:57:00 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 194844 kb
Host smart-2a0c8d02-e78a-4b3e-bb08-5563bdd0fc65
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570458044 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2570458044
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.321198416
Short name T774
Test name
Test status
Simulation time 447161063 ps
CPU time 2.87 seconds
Started Mar 07 12:57:11 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 198592 kb
Host smart-3a8de10a-74c4-4f36-965f-676467c445d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321198416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.321198416
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2197693187
Short name T832
Test name
Test status
Simulation time 185153267 ps
CPU time 1.36 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 198652 kb
Host smart-4ee00938-4c8e-44fd-b51d-3b89888784d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197693187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2197693187
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2650367532
Short name T730
Test name
Test status
Simulation time 63714442 ps
CPU time 0.66 seconds
Started Mar 07 12:57:13 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 194232 kb
Host smart-41e089d1-070d-47aa-90c5-75993546435a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650367532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2650367532
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.3929506287
Short name T745
Test name
Test status
Simulation time 40228950 ps
CPU time 0.6 seconds
Started Mar 07 12:57:24 PM PST 24
Finished Mar 07 12:57:25 PM PST 24
Peak memory 194208 kb
Host smart-76c0fed7-d8e6-451d-80eb-1e243738bab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929506287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.3929506287
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.2583915220
Short name T825
Test name
Test status
Simulation time 15778157 ps
CPU time 0.56 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 194152 kb
Host smart-6b64b8db-d425-460f-bca8-0e0cbb0fd76f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583915220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.2583915220
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.4167993767
Short name T759
Test name
Test status
Simulation time 51380209 ps
CPU time 0.62 seconds
Started Mar 07 12:57:29 PM PST 24
Finished Mar 07 12:57:30 PM PST 24
Peak memory 194328 kb
Host smart-e5758e61-5348-49b7-b6da-7a05760a0878
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167993767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.4167993767
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2792711086
Short name T734
Test name
Test status
Simulation time 53594576 ps
CPU time 0.6 seconds
Started Mar 07 12:57:30 PM PST 24
Finished Mar 07 12:57:31 PM PST 24
Peak memory 194224 kb
Host smart-c969cbee-bb51-4925-8bbd-980bde5f6861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792711086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2792711086
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1789377743
Short name T846
Test name
Test status
Simulation time 24887721 ps
CPU time 0.61 seconds
Started Mar 07 12:57:23 PM PST 24
Finished Mar 07 12:57:24 PM PST 24
Peak memory 194936 kb
Host smart-0e545485-15b8-4457-85f8-27b0c132285a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789377743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1789377743
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3179900802
Short name T782
Test name
Test status
Simulation time 11686216 ps
CPU time 0.62 seconds
Started Mar 07 12:57:30 PM PST 24
Finished Mar 07 12:57:31 PM PST 24
Peak memory 194884 kb
Host smart-30512c08-16e2-4260-a493-f9f15014eef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179900802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3179900802
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.2154204014
Short name T812
Test name
Test status
Simulation time 47581547 ps
CPU time 0.61 seconds
Started Mar 07 12:57:20 PM PST 24
Finished Mar 07 12:57:21 PM PST 24
Peak memory 194228 kb
Host smart-71ce3732-0fda-4adb-903d-075ac52ddb51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154204014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.2154204014
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.2705773805
Short name T841
Test name
Test status
Simulation time 31547857 ps
CPU time 0.6 seconds
Started Mar 07 12:57:20 PM PST 24
Finished Mar 07 12:57:21 PM PST 24
Peak memory 194268 kb
Host smart-8ac72f6a-b1fd-4a2b-8598-e8171238fe8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705773805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.2705773805
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3230892751
Short name T820
Test name
Test status
Simulation time 12207383 ps
CPU time 0.61 seconds
Started Mar 07 12:57:18 PM PST 24
Finished Mar 07 12:57:19 PM PST 24
Peak memory 194912 kb
Host smart-2eb45456-d76a-43d3-ad74-de6598f3ff8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230892751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3230892751
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.381529495
Short name T100
Test name
Test status
Simulation time 143943517 ps
CPU time 0.86 seconds
Started Mar 07 12:57:04 PM PST 24
Finished Mar 07 12:57:05 PM PST 24
Peak memory 196632 kb
Host smart-2f32bce4-bd1d-4b07-bdc0-febb4b090da5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381529495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.gpio_csr_aliasing.381529495
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3002201762
Short name T99
Test name
Test status
Simulation time 162843709 ps
CPU time 2.85 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:11 PM PST 24
Peak memory 197328 kb
Host smart-dd922385-f749-4f1d-b5ee-dbcdf8fb3694
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002201762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3002201762
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3177333139
Short name T822
Test name
Test status
Simulation time 67496795 ps
CPU time 0.64 seconds
Started Mar 07 12:56:55 PM PST 24
Finished Mar 07 12:56:56 PM PST 24
Peak memory 196056 kb
Host smart-bfcadb43-e12c-429a-9250-744aa7f12e74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177333139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3177333139
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3198603859
Short name T817
Test name
Test status
Simulation time 68880919 ps
CPU time 1.69 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 198560 kb
Host smart-5a1fc3b7-a3b6-4fbf-9b07-513c9fe2288c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198603859 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3198603859
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1917764628
Short name T758
Test name
Test status
Simulation time 26492959 ps
CPU time 0.58 seconds
Started Mar 07 12:56:57 PM PST 24
Finished Mar 07 12:57:03 PM PST 24
Peak memory 194508 kb
Host smart-074c779f-4a67-466b-9097-cf854e0336d4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917764628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1917764628
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.4006749552
Short name T787
Test name
Test status
Simulation time 65244942 ps
CPU time 0.56 seconds
Started Mar 07 12:57:05 PM PST 24
Finished Mar 07 12:57:07 PM PST 24
Peak memory 194232 kb
Host smart-d64f0f00-6714-4920-add0-4a37ca401923
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006749552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.4006749552
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1372086080
Short name T821
Test name
Test status
Simulation time 36788029 ps
CPU time 0.9 seconds
Started Mar 07 12:56:50 PM PST 24
Finished Mar 07 12:56:51 PM PST 24
Peak memory 197672 kb
Host smart-c4387216-c93c-4b1f-b086-8a0cb58f7548
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372086080 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1372086080
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2930544775
Short name T770
Test name
Test status
Simulation time 130878272 ps
CPU time 2.48 seconds
Started Mar 07 12:56:50 PM PST 24
Finished Mar 07 12:56:52 PM PST 24
Peak memory 198604 kb
Host smart-c5ff9c22-065b-4f96-9d25-c4b1a8d80f23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930544775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2930544775
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.597465264
Short name T772
Test name
Test status
Simulation time 162423103 ps
CPU time 0.85 seconds
Started Mar 07 12:56:45 PM PST 24
Finished Mar 07 12:56:46 PM PST 24
Peak memory 198428 kb
Host smart-781febd1-ada8-4e4d-8362-e258b1d72bd6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597465264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.597465264
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.2819853436
Short name T773
Test name
Test status
Simulation time 42363500 ps
CPU time 0.55 seconds
Started Mar 07 12:57:23 PM PST 24
Finished Mar 07 12:57:24 PM PST 24
Peak memory 194236 kb
Host smart-e251455a-4a35-47f0-bb6c-a510d36f38b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819853436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.2819853436
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2182146562
Short name T784
Test name
Test status
Simulation time 40729347 ps
CPU time 0.55 seconds
Started Mar 07 12:57:28 PM PST 24
Finished Mar 07 12:57:28 PM PST 24
Peak memory 194228 kb
Host smart-64e381ab-6bc3-4809-a156-583bd4c102a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182146562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2182146562
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1160445289
Short name T815
Test name
Test status
Simulation time 11925287 ps
CPU time 0.59 seconds
Started Mar 07 12:57:22 PM PST 24
Finished Mar 07 12:57:23 PM PST 24
Peak memory 194900 kb
Host smart-d1596bd4-940e-4808-a37d-3c90f86d6202
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160445289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1160445289
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.607229573
Short name T778
Test name
Test status
Simulation time 14297483 ps
CPU time 0.55 seconds
Started Mar 07 12:57:19 PM PST 24
Finished Mar 07 12:57:20 PM PST 24
Peak memory 194232 kb
Host smart-2ccf2fde-e8b9-4a53-95fe-c126ad417dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607229573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.607229573
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.339058403
Short name T780
Test name
Test status
Simulation time 33417262 ps
CPU time 0.58 seconds
Started Mar 07 12:57:22 PM PST 24
Finished Mar 07 12:57:23 PM PST 24
Peak memory 194268 kb
Host smart-833f61fd-5f17-4e4a-91ac-b102d2439a2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339058403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.339058403
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2452214505
Short name T781
Test name
Test status
Simulation time 17278929 ps
CPU time 0.59 seconds
Started Mar 07 12:57:24 PM PST 24
Finished Mar 07 12:57:25 PM PST 24
Peak memory 194296 kb
Host smart-6a65fd09-156e-49c6-92ac-081c45a6072b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452214505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2452214505
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.3909042708
Short name T735
Test name
Test status
Simulation time 84565953 ps
CPU time 0.55 seconds
Started Mar 07 12:57:17 PM PST 24
Finished Mar 07 12:57:18 PM PST 24
Peak memory 194872 kb
Host smart-2c7afbe2-70ed-4003-9fca-4529ac6c3095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909042708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.3909042708
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2753121924
Short name T819
Test name
Test status
Simulation time 50836334 ps
CPU time 0.59 seconds
Started Mar 07 12:57:17 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 194152 kb
Host smart-98feb3f9-d16e-4eb9-a8c9-00648f718f52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753121924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2753121924
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2101349970
Short name T728
Test name
Test status
Simulation time 36741460 ps
CPU time 0.61 seconds
Started Mar 07 12:57:19 PM PST 24
Finished Mar 07 12:57:20 PM PST 24
Peak memory 194916 kb
Host smart-9e6f9746-5cdd-44b9-919d-07c4f1af3256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101349970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2101349970
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.567422054
Short name T752
Test name
Test status
Simulation time 17406546 ps
CPU time 0.63 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 194300 kb
Host smart-36534806-8667-4d75-856d-683cea0479e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567422054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.567422054
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2526807011
Short name T737
Test name
Test status
Simulation time 32898977 ps
CPU time 0.66 seconds
Started Mar 07 12:56:58 PM PST 24
Finished Mar 07 12:56:59 PM PST 24
Peak memory 198408 kb
Host smart-f8f3ae30-feaa-4671-9cce-18ac186ed646
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526807011 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2526807011
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.4017466619
Short name T755
Test name
Test status
Simulation time 36204090 ps
CPU time 0.57 seconds
Started Mar 07 12:57:09 PM PST 24
Finished Mar 07 12:57:10 PM PST 24
Peak memory 195072 kb
Host smart-33e2c526-5ab8-465c-b98d-d65041f88eca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017466619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.4017466619
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3469236409
Short name T793
Test name
Test status
Simulation time 64486603 ps
CPU time 0.61 seconds
Started Mar 07 12:57:11 PM PST 24
Finished Mar 07 12:57:13 PM PST 24
Peak memory 194224 kb
Host smart-f63e7cce-798c-4573-8019-2a9d91b95ba6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469236409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3469236409
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.941764231
Short name T824
Test name
Test status
Simulation time 37581213 ps
CPU time 0.86 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:14 PM PST 24
Peak memory 197576 kb
Host smart-fbeb0e8b-4a58-4a18-ac3a-76292925e27d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941764231 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 5.gpio_same_csr_outstanding.941764231
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3602747241
Short name T800
Test name
Test status
Simulation time 465650150 ps
CPU time 2.35 seconds
Started Mar 07 12:57:13 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 198560 kb
Host smart-091b0d06-f3e2-489e-884f-c4b723c1b7db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602747241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3602747241
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.1672466787
Short name T790
Test name
Test status
Simulation time 78148059 ps
CPU time 1.14 seconds
Started Mar 07 12:57:02 PM PST 24
Finished Mar 07 12:57:04 PM PST 24
Peak memory 198620 kb
Host smart-1749460c-e2b6-4ac7-9016-8fc3c3c76305
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672466787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.1672466787
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2441572393
Short name T748
Test name
Test status
Simulation time 49388102 ps
CPU time 0.65 seconds
Started Mar 07 12:57:17 PM PST 24
Finished Mar 07 12:57:18 PM PST 24
Peak memory 198260 kb
Host smart-045e1c33-8b81-4206-bd8f-5bae3737f48e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441572393 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2441572393
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1358179562
Short name T89
Test name
Test status
Simulation time 21519312 ps
CPU time 0.58 seconds
Started Mar 07 12:57:13 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 195240 kb
Host smart-c14fafa9-4844-466e-a8df-64fe6580638e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358179562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1358179562
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.839587815
Short name T791
Test name
Test status
Simulation time 43896623 ps
CPU time 0.61 seconds
Started Mar 07 12:57:06 PM PST 24
Finished Mar 07 12:57:08 PM PST 24
Peak memory 194228 kb
Host smart-f9f63552-10e6-4f18-a634-ada6a6891ca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839587815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.839587815
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1661040005
Short name T85
Test name
Test status
Simulation time 19267152 ps
CPU time 0.66 seconds
Started Mar 07 12:57:00 PM PST 24
Finished Mar 07 12:57:08 PM PST 24
Peak memory 195964 kb
Host smart-ef53d029-98b9-4f05-b2de-69374dbbab9d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661040005 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1661040005
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.795895551
Short name T810
Test name
Test status
Simulation time 368205995 ps
CPU time 2.64 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:11 PM PST 24
Peak memory 198640 kb
Host smart-d9dd68db-91f9-4418-9add-3923ac92f7e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795895551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.795895551
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1570426566
Short name T763
Test name
Test status
Simulation time 65490681 ps
CPU time 0.84 seconds
Started Mar 07 12:57:14 PM PST 24
Finished Mar 07 12:57:16 PM PST 24
Peak memory 197732 kb
Host smart-04b0a534-0d74-408b-a2f1-15423b0384fd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570426566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1570426566
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.163536975
Short name T802
Test name
Test status
Simulation time 24089181 ps
CPU time 1.01 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:14 PM PST 24
Peak memory 198448 kb
Host smart-764d4ab0-d370-4988-9336-dbaca58b6aa9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163536975 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.163536975
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.532656344
Short name T92
Test name
Test status
Simulation time 11925906 ps
CPU time 0.62 seconds
Started Mar 07 12:57:13 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 195508 kb
Host smart-0c1c9b75-1657-47a2-a6a2-b915117cee9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532656344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_
csr_rw.532656344
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3102978318
Short name T740
Test name
Test status
Simulation time 12274463 ps
CPU time 0.59 seconds
Started Mar 07 12:57:06 PM PST 24
Finished Mar 07 12:57:08 PM PST 24
Peak memory 194264 kb
Host smart-e90a7bf1-1fca-491c-8c07-5ef0e489f71a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102978318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3102978318
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.506612375
Short name T104
Test name
Test status
Simulation time 33520501 ps
CPU time 0.87 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:14 PM PST 24
Peak memory 196992 kb
Host smart-52b3c06c-2ab9-4c61-ae56-aa6a692a74d2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506612375 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.506612375
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.416332052
Short name T783
Test name
Test status
Simulation time 151708033 ps
CPU time 1.49 seconds
Started Mar 07 12:57:20 PM PST 24
Finished Mar 07 12:57:21 PM PST 24
Peak memory 198624 kb
Host smart-6fb46f03-c42a-4978-934e-8942187f021f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416332052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.416332052
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.380571639
Short name T51
Test name
Test status
Simulation time 193224971 ps
CPU time 0.87 seconds
Started Mar 07 12:57:27 PM PST 24
Finished Mar 07 12:57:28 PM PST 24
Peak memory 198300 kb
Host smart-d0d4edf6-5645-4d42-8aaf-d3bee76f2cac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380571639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.380571639
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.64422006
Short name T829
Test name
Test status
Simulation time 61893621 ps
CPU time 0.82 seconds
Started Mar 07 12:57:10 PM PST 24
Finished Mar 07 12:57:12 PM PST 24
Peak memory 198460 kb
Host smart-dc2c6a21-cebc-4fdb-a040-f155d8e53699
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64422006 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.64422006
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.660088641
Short name T94
Test name
Test status
Simulation time 33240283 ps
CPU time 0.61 seconds
Started Mar 07 12:57:09 PM PST 24
Finished Mar 07 12:57:11 PM PST 24
Peak memory 195356 kb
Host smart-efb924c6-567d-491a-931b-9580f2d43e57
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660088641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.660088641
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.4025803987
Short name T771
Test name
Test status
Simulation time 36531704 ps
CPU time 0.62 seconds
Started Mar 07 12:57:01 PM PST 24
Finished Mar 07 12:57:02 PM PST 24
Peak memory 194132 kb
Host smart-5f2f1dc9-646f-441c-a2f0-481feb302584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025803987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.4025803987
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.2782214465
Short name T837
Test name
Test status
Simulation time 513754910 ps
CPU time 0.84 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:09 PM PST 24
Peak memory 196856 kb
Host smart-1f968128-f137-4518-9bf6-2be71ce844ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782214465 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.2782214465
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.394880635
Short name T738
Test name
Test status
Simulation time 193115577 ps
CPU time 1.97 seconds
Started Mar 07 12:57:20 PM PST 24
Finished Mar 07 12:57:23 PM PST 24
Peak memory 198584 kb
Host smart-c9ab30a2-e39d-425f-a64f-54d4e5ac8590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394880635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.394880635
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1093248303
Short name T45
Test name
Test status
Simulation time 405939637 ps
CPU time 1.46 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 198592 kb
Host smart-06d94e92-307b-4520-8412-b6ed3cd98a10
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093248303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1093248303
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2385011986
Short name T788
Test name
Test status
Simulation time 39719136 ps
CPU time 1.82 seconds
Started Mar 07 12:57:13 PM PST 24
Finished Mar 07 12:57:16 PM PST 24
Peak memory 198660 kb
Host smart-2f15ac26-5840-4a81-9ff9-ed125c4af26a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385011986 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2385011986
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1017598929
Short name T93
Test name
Test status
Simulation time 42633277 ps
CPU time 0.58 seconds
Started Mar 07 12:57:09 PM PST 24
Finished Mar 07 12:57:11 PM PST 24
Peak memory 195172 kb
Host smart-5019bedf-1daa-47a9-b099-a07d332a4db7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017598929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1017598929
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.988100798
Short name T794
Test name
Test status
Simulation time 47002727 ps
CPU time 0.6 seconds
Started Mar 07 12:57:10 PM PST 24
Finished Mar 07 12:57:12 PM PST 24
Peak memory 194192 kb
Host smart-db33f199-7a18-45cd-8b0e-d9b077ea1daa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988100798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.988100798
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3878820238
Short name T102
Test name
Test status
Simulation time 65819918 ps
CPU time 0.65 seconds
Started Mar 07 12:57:16 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 195436 kb
Host smart-a5e25805-f856-4671-9752-c044d0457105
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878820238 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3878820238
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4222404177
Short name T775
Test name
Test status
Simulation time 151018147 ps
CPU time 2.92 seconds
Started Mar 07 12:57:20 PM PST 24
Finished Mar 07 12:57:23 PM PST 24
Peak memory 198548 kb
Host smart-e8bc26ec-ea48-414e-b0ff-f03e6b78bbac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222404177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.4222404177
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2922914352
Short name T46
Test name
Test status
Simulation time 374554711 ps
CPU time 1.14 seconds
Started Mar 07 12:57:13 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 198608 kb
Host smart-dbbdecff-659c-4aa7-bb78-5ad1a3e38f3d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922914352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2922914352
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.2716981477
Short name T256
Test name
Test status
Simulation time 38917478 ps
CPU time 0.58 seconds
Started Mar 07 01:20:06 PM PST 24
Finished Mar 07 01:20:07 PM PST 24
Peak memory 194112 kb
Host smart-da04a30e-70ad-4e1a-b50f-12c0979b95b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716981477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.2716981477
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.289185228
Short name T226
Test name
Test status
Simulation time 49395983 ps
CPU time 0.91 seconds
Started Mar 07 01:20:06 PM PST 24
Finished Mar 07 01:20:08 PM PST 24
Peak memory 196404 kb
Host smart-e21e8181-9265-4989-817b-a16be8bb5713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289185228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.289185228
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.1677278590
Short name T203
Test name
Test status
Simulation time 695385755 ps
CPU time 21.72 seconds
Started Mar 07 01:20:03 PM PST 24
Finished Mar 07 01:20:25 PM PST 24
Peak memory 196360 kb
Host smart-0e6bdc82-bd0c-41bb-9645-7cc18d2cb6ff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677278590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.1677278590
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2254010870
Short name T394
Test name
Test status
Simulation time 571150445 ps
CPU time 1.07 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:07 PM PST 24
Peak memory 198092 kb
Host smart-f736a3af-6b03-4a58-a7e8-8e945b88eaa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254010870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2254010870
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2327902888
Short name T249
Test name
Test status
Simulation time 36690155 ps
CPU time 1.13 seconds
Started Mar 07 01:20:04 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 196148 kb
Host smart-0bac50cf-8e46-45f6-9f3c-50cd411d1871
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327902888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2327902888
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2170373591
Short name T565
Test name
Test status
Simulation time 369253935 ps
CPU time 3.58 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:09 PM PST 24
Peak memory 198272 kb
Host smart-353d931c-43d5-47dd-9407-d4fa5ad47636
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170373591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2170373591
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4220640413
Short name T387
Test name
Test status
Simulation time 421797069 ps
CPU time 2.13 seconds
Started Mar 07 01:20:03 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 195884 kb
Host smart-49202f4d-14a1-4839-9254-6ea3321488cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220640413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4220640413
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3140225012
Short name T316
Test name
Test status
Simulation time 64995527 ps
CPU time 0.88 seconds
Started Mar 07 01:20:02 PM PST 24
Finished Mar 07 01:20:03 PM PST 24
Peak memory 197408 kb
Host smart-f13151be-f35e-4e52-ac46-5cf4b1484afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140225012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3140225012
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3937767869
Short name T55
Test name
Test status
Simulation time 21850214 ps
CPU time 0.72 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 195532 kb
Host smart-28ac5b63-4b40-4f5a-a896-da10d8708dd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937767869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3937767869
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3773963769
Short name T354
Test name
Test status
Simulation time 477692940 ps
CPU time 5.55 seconds
Started Mar 07 01:20:07 PM PST 24
Finished Mar 07 01:20:13 PM PST 24
Peak memory 198148 kb
Host smart-62fb3ef7-87f8-4c7f-b66a-bec25f79700f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773963769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3773963769
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.2395117498
Short name T689
Test name
Test status
Simulation time 75252678 ps
CPU time 0.91 seconds
Started Mar 07 01:20:02 PM PST 24
Finished Mar 07 01:20:04 PM PST 24
Peak memory 195460 kb
Host smart-4606b217-9e04-4b6a-a7ba-2ef2e56ed297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395117498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2395117498
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2140335118
Short name T327
Test name
Test status
Simulation time 621506103 ps
CPU time 1.32 seconds
Started Mar 07 01:20:03 PM PST 24
Finished Mar 07 01:20:05 PM PST 24
Peak memory 196596 kb
Host smart-8d5965af-dd42-48b7-80cc-0cd27cb53ed4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140335118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2140335118
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1983550632
Short name T7
Test name
Test status
Simulation time 15989743586 ps
CPU time 149.2 seconds
Started Mar 07 01:20:04 PM PST 24
Finished Mar 07 01:22:34 PM PST 24
Peak memory 198296 kb
Host smart-3571c2fa-bc23-4eb9-86ab-b1f573b02793
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983550632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1983550632
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.438212570
Short name T461
Test name
Test status
Simulation time 80090709999 ps
CPU time 1466.74 seconds
Started Mar 07 01:20:03 PM PST 24
Finished Mar 07 01:44:30 PM PST 24
Peak memory 198504 kb
Host smart-86c67538-912d-41fb-a6a7-00568865904b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=438212570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.438212570
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.2458283393
Short name T713
Test name
Test status
Simulation time 23815573 ps
CPU time 0.58 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 194068 kb
Host smart-fb2a3e84-cb02-458d-b4ce-09ca596369c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458283393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.2458283393
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.2808372002
Short name T314
Test name
Test status
Simulation time 275085371 ps
CPU time 0.76 seconds
Started Mar 07 01:20:06 PM PST 24
Finished Mar 07 01:20:08 PM PST 24
Peak memory 195352 kb
Host smart-e6ddb973-52a6-43d1-9ee5-d4141b3386c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808372002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.2808372002
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.857862052
Short name T597
Test name
Test status
Simulation time 1155844468 ps
CPU time 15.37 seconds
Started Mar 07 01:19:59 PM PST 24
Finished Mar 07 01:20:15 PM PST 24
Peak memory 195680 kb
Host smart-6afe8210-02ff-4660-a57f-2ccbd0a5f453
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857862052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stress
.857862052
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2300556371
Short name T164
Test name
Test status
Simulation time 318533027 ps
CPU time 1.11 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:07 PM PST 24
Peak memory 198236 kb
Host smart-0650b8a9-7f57-413e-b211-333d53634eb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300556371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2300556371
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1513116060
Short name T530
Test name
Test status
Simulation time 339790116 ps
CPU time 1.44 seconds
Started Mar 07 01:20:06 PM PST 24
Finished Mar 07 01:20:08 PM PST 24
Peak memory 197348 kb
Host smart-6eadcfba-765b-4b25-bacf-d03309bc7495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513116060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1513116060
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1308007020
Short name T491
Test name
Test status
Simulation time 68864881 ps
CPU time 1.47 seconds
Started Mar 07 01:20:06 PM PST 24
Finished Mar 07 01:20:08 PM PST 24
Peak memory 196400 kb
Host smart-3ed07e40-67b5-414b-b578-3497e1b0c2da
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308007020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1308007020
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.183557411
Short name T253
Test name
Test status
Simulation time 48659600 ps
CPU time 1.29 seconds
Started Mar 07 01:20:04 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 196824 kb
Host smart-d78ffd7b-81e1-4b7e-a346-b43e1ed17d2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183557411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.183557411
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2293734146
Short name T600
Test name
Test status
Simulation time 29720566 ps
CPU time 0.77 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 196344 kb
Host smart-7c2312c1-7f68-4e9b-b9ca-beecf3e15108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293734146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2293734146
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3276245386
Short name T163
Test name
Test status
Simulation time 47929763 ps
CPU time 1.12 seconds
Started Mar 07 01:20:07 PM PST 24
Finished Mar 07 01:20:08 PM PST 24
Peak memory 195972 kb
Host smart-19c4655c-e0ee-4f19-8c7d-fd0ce838f801
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276245386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3276245386
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2015463485
Short name T337
Test name
Test status
Simulation time 1617833565 ps
CPU time 4.63 seconds
Started Mar 07 01:20:02 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 198148 kb
Host smart-d200dbf1-e335-4531-956e-2aa13a0aa194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015463485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2015463485
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2231840576
Short name T53
Test name
Test status
Simulation time 131070308 ps
CPU time 0.81 seconds
Started Mar 07 01:20:03 PM PST 24
Finished Mar 07 01:20:05 PM PST 24
Peak memory 213632 kb
Host smart-8ef1280a-9375-420a-9bae-4bd3cf97dc6d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231840576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2231840576
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.2909097390
Short name T229
Test name
Test status
Simulation time 66634870 ps
CPU time 1.17 seconds
Started Mar 07 01:20:04 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 196828 kb
Host smart-ab54c83e-a0ea-42d6-950e-6584d39d661d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909097390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.2909097390
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.3789662692
Short name T298
Test name
Test status
Simulation time 228931641 ps
CPU time 1.16 seconds
Started Mar 07 01:20:02 PM PST 24
Finished Mar 07 01:20:04 PM PST 24
Peak memory 195812 kb
Host smart-f4a347df-4546-43e2-8241-e64484c4d234
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789662692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.3789662692
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.4127976069
Short name T628
Test name
Test status
Simulation time 58583317946 ps
CPU time 178.94 seconds
Started Mar 07 01:20:07 PM PST 24
Finished Mar 07 01:23:07 PM PST 24
Peak memory 198288 kb
Host smart-64672268-07b9-447c-98ab-d8c7b00ff9e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127976069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.4127976069
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3061369388
Short name T435
Test name
Test status
Simulation time 58340783 ps
CPU time 0.58 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:36 PM PST 24
Peak memory 194092 kb
Host smart-7230c41c-57d2-4ed4-9c83-4315c3a4f353
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061369388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3061369388
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2219545253
Short name T615
Test name
Test status
Simulation time 45393277 ps
CPU time 0.84 seconds
Started Mar 07 01:20:30 PM PST 24
Finished Mar 07 01:20:30 PM PST 24
Peak memory 196392 kb
Host smart-cc0e6847-7d18-4df4-8217-83531cb3c10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219545253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2219545253
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3905997836
Short name T430
Test name
Test status
Simulation time 636662501 ps
CPU time 21.94 seconds
Started Mar 07 01:20:30 PM PST 24
Finished Mar 07 01:20:52 PM PST 24
Peak memory 198176 kb
Host smart-24032192-0e2f-4d38-b416-62825d0dc26b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905997836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3905997836
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.1189628261
Short name T714
Test name
Test status
Simulation time 60117361 ps
CPU time 0.83 seconds
Started Mar 07 01:20:35 PM PST 24
Finished Mar 07 01:20:37 PM PST 24
Peak memory 196676 kb
Host smart-a8b0d225-49e0-4a6c-b1fb-b462fb30eda6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189628261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.1189628261
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.113517524
Short name T205
Test name
Test status
Simulation time 98895584 ps
CPU time 1.4 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:20:34 PM PST 24
Peak memory 197136 kb
Host smart-f93f922e-67e1-4af8-99d8-accb5f68b191
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113517524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.113517524
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.2611455640
Short name T535
Test name
Test status
Simulation time 79594759 ps
CPU time 1.06 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:36 PM PST 24
Peak memory 196512 kb
Host smart-29fa4fc0-d2ca-4787-ad5b-055b84e69af3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611455640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.2611455640
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3659931521
Short name T609
Test name
Test status
Simulation time 364713547 ps
CPU time 2.95 seconds
Started Mar 07 01:20:31 PM PST 24
Finished Mar 07 01:20:35 PM PST 24
Peak memory 195912 kb
Host smart-95945e50-7dbf-4823-af97-60ce5d48e360
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659931521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3659931521
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.4064308687
Short name T326
Test name
Test status
Simulation time 34078722 ps
CPU time 0.86 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:37 PM PST 24
Peak memory 196536 kb
Host smart-e5f02268-141e-481d-9142-f319d4ac894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064308687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.4064308687
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3373135389
Short name T515
Test name
Test status
Simulation time 58126834 ps
CPU time 0.83 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:36 PM PST 24
Peak memory 196144 kb
Host smart-629f41da-2842-496e-b5ac-408e167cffa4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373135389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3373135389
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.128575161
Short name T3
Test name
Test status
Simulation time 3380017430 ps
CPU time 5.68 seconds
Started Mar 07 01:20:35 PM PST 24
Finished Mar 07 01:20:41 PM PST 24
Peak memory 198164 kb
Host smart-19faeaa9-8688-48e7-a6c1-54eb9d19434c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128575161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.128575161
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.4244178587
Short name T563
Test name
Test status
Simulation time 82947084 ps
CPU time 1.28 seconds
Started Mar 07 01:20:26 PM PST 24
Finished Mar 07 01:20:27 PM PST 24
Peak memory 196020 kb
Host smart-70ccf58f-d54b-46f2-95a2-c10b8e04b9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244178587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.4244178587
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1491668187
Short name T398
Test name
Test status
Simulation time 620151793 ps
CPU time 1.47 seconds
Started Mar 07 01:20:24 PM PST 24
Finished Mar 07 01:20:26 PM PST 24
Peak memory 198120 kb
Host smart-a9716919-f51b-41c7-8de6-09cf03009eb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491668187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1491668187
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3243824179
Short name T674
Test name
Test status
Simulation time 3436273599 ps
CPU time 92.55 seconds
Started Mar 07 01:20:36 PM PST 24
Finished Mar 07 01:22:09 PM PST 24
Peak memory 198324 kb
Host smart-b0fecfcd-5b52-4698-8fc1-6c8048ed276a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243824179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3243824179
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.4030803852
Short name T554
Test name
Test status
Simulation time 13371857 ps
CPU time 0.59 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:36 PM PST 24
Peak memory 194108 kb
Host smart-ae40a96a-9787-47eb-9252-68171416b08a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030803852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.4030803852
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2208966103
Short name T371
Test name
Test status
Simulation time 18620209 ps
CPU time 0.7 seconds
Started Mar 07 01:20:30 PM PST 24
Finished Mar 07 01:20:30 PM PST 24
Peak memory 194752 kb
Host smart-55e7e1c6-1642-4f0e-b4d6-c9381ba1b715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208966103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2208966103
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.1021045624
Short name T16
Test name
Test status
Simulation time 243345563 ps
CPU time 8.72 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:20:41 PM PST 24
Peak memory 195696 kb
Host smart-fce13843-cc12-41e3-9de5-004ea9e0cac7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021045624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.1021045624
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3542716827
Short name T353
Test name
Test status
Simulation time 52351050 ps
CPU time 0.89 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:20:33 PM PST 24
Peak memory 196092 kb
Host smart-aae29ab3-c14f-41e1-8d89-05c08660f376
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542716827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3542716827
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.165037743
Short name T386
Test name
Test status
Simulation time 630105498 ps
CPU time 1.05 seconds
Started Mar 07 01:20:31 PM PST 24
Finished Mar 07 01:20:33 PM PST 24
Peak memory 196228 kb
Host smart-28e7c304-fe0a-4ab9-aed6-6ea938a5b634
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165037743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.165037743
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1630759631
Short name T626
Test name
Test status
Simulation time 60608260 ps
CPU time 2.33 seconds
Started Mar 07 01:20:37 PM PST 24
Finished Mar 07 01:20:40 PM PST 24
Peak memory 198164 kb
Host smart-75807d1d-31d5-46be-a753-f7a407e5ce7d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630759631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1630759631
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.4017241320
Short name T340
Test name
Test status
Simulation time 26378176 ps
CPU time 1.08 seconds
Started Mar 07 01:20:37 PM PST 24
Finished Mar 07 01:20:39 PM PST 24
Peak memory 195648 kb
Host smart-f41bbde0-c508-4201-833b-fde389bb1188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017241320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.4017241320
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2399638800
Short name T69
Test name
Test status
Simulation time 108742289 ps
CPU time 1.25 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:20:34 PM PST 24
Peak memory 197208 kb
Host smart-b4366d46-10d6-4ee7-bf13-ff8f687ee15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399638800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2399638800
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.628482854
Short name T393
Test name
Test status
Simulation time 64321809 ps
CPU time 0.73 seconds
Started Mar 07 01:20:31 PM PST 24
Finished Mar 07 01:20:33 PM PST 24
Peak memory 195540 kb
Host smart-e7ac06bb-31b7-408b-9f0f-c8cb57080d62
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628482854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.628482854
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_smoke.980752529
Short name T415
Test name
Test status
Simulation time 183506125 ps
CPU time 1.33 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:20:34 PM PST 24
Peak memory 195664 kb
Host smart-3469b2a9-757e-42bd-9201-5d138b3de584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980752529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.980752529
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2101431551
Short name T175
Test name
Test status
Simulation time 67859896 ps
CPU time 1.32 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:20:33 PM PST 24
Peak memory 198176 kb
Host smart-cc4cc1af-ecd9-49ae-975a-39c38aa6a499
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101431551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2101431551
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3608996133
Short name T330
Test name
Test status
Simulation time 2960919519 ps
CPU time 46.05 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 198396 kb
Host smart-564af75e-57bf-476b-a004-32f0afba1ea6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608996133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3608996133
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.4159152131
Short name T291
Test name
Test status
Simulation time 40151021520 ps
CPU time 1189.88 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:40:22 PM PST 24
Peak memory 198444 kb
Host smart-52cdef9e-1576-41f2-919b-430f5fe0b237
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4159152131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.4159152131
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.4263357142
Short name T263
Test name
Test status
Simulation time 22496438 ps
CPU time 0.59 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:20:33 PM PST 24
Peak memory 195060 kb
Host smart-611375d5-3eb5-4251-b774-c51eaaebc0db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263357142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.4263357142
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.80457455
Short name T178
Test name
Test status
Simulation time 163810334 ps
CPU time 1.02 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:20:33 PM PST 24
Peak memory 196536 kb
Host smart-531a20a1-9cb0-43d5-adaa-02ed644c9dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80457455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.80457455
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.354610319
Short name T482
Test name
Test status
Simulation time 401112807 ps
CPU time 13.51 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 195640 kb
Host smart-c24ff0a4-93ec-4c35-be75-67278a98923b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354610319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.354610319
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2374406604
Short name T404
Test name
Test status
Simulation time 87104632 ps
CPU time 0.81 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:37 PM PST 24
Peak memory 196012 kb
Host smart-eb4add49-04fa-4859-aff8-aaa3303b84e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374406604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2374406604
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3271404009
Short name T652
Test name
Test status
Simulation time 85429048 ps
CPU time 0.81 seconds
Started Mar 07 01:20:33 PM PST 24
Finished Mar 07 01:20:36 PM PST 24
Peak memory 195648 kb
Host smart-dce4ad38-af7e-452e-87fb-18ceaa4ce4d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271404009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3271404009
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.2691471861
Short name T424
Test name
Test status
Simulation time 208519091 ps
CPU time 2.16 seconds
Started Mar 07 01:20:33 PM PST 24
Finished Mar 07 01:20:37 PM PST 24
Peak memory 196444 kb
Host smart-cfe914b3-1e73-4c2c-87ab-382f80dbcc65
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691471861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.2691471861
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2109780024
Short name T698
Test name
Test status
Simulation time 577541494 ps
CPU time 2.66 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:37 PM PST 24
Peak memory 197268 kb
Host smart-9ab52900-6c18-4730-be2e-c819674a109b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109780024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2109780024
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1229382361
Short name T141
Test name
Test status
Simulation time 49625105 ps
CPU time 1.12 seconds
Started Mar 07 01:20:30 PM PST 24
Finished Mar 07 01:20:31 PM PST 24
Peak memory 196200 kb
Host smart-3ff8d598-a6ec-4918-adde-d257395be032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229382361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1229382361
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2582774711
Short name T137
Test name
Test status
Simulation time 34275555 ps
CPU time 0.99 seconds
Started Mar 07 01:20:31 PM PST 24
Finished Mar 07 01:20:32 PM PST 24
Peak memory 196200 kb
Host smart-e59ce474-d347-4ee2-86c1-42a3ec8e6bc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582774711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2582774711
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3804592444
Short name T623
Test name
Test status
Simulation time 702918257 ps
CPU time 4.47 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:39 PM PST 24
Peak memory 198044 kb
Host smart-56f09485-bf7d-42a9-b7f9-bfc2896c2844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804592444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3804592444
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1527484284
Short name T454
Test name
Test status
Simulation time 52434226 ps
CPU time 1.06 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:37 PM PST 24
Peak memory 195856 kb
Host smart-fe2e9596-82cb-47ec-8fab-55cb85cccfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527484284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1527484284
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.4101098123
Short name T57
Test name
Test status
Simulation time 39233189 ps
CPU time 0.88 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:20:34 PM PST 24
Peak memory 195228 kb
Host smart-485213f3-be8e-4e6b-9378-0fc41f5ecdeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101098123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.4101098123
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3878972127
Short name T200
Test name
Test status
Simulation time 6250275369 ps
CPU time 169.55 seconds
Started Mar 07 01:20:35 PM PST 24
Finished Mar 07 01:23:25 PM PST 24
Peak memory 198248 kb
Host smart-29ba7f13-c862-48d1-a5b9-c4da406b5a21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878972127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3878972127
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.737804185
Short name T556
Test name
Test status
Simulation time 96556395 ps
CPU time 0.6 seconds
Started Mar 07 01:20:44 PM PST 24
Finished Mar 07 01:20:45 PM PST 24
Peak memory 195000 kb
Host smart-228d6ca9-ce13-4ea3-9370-b5d392a01ba4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737804185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.737804185
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.2523219801
Short name T608
Test name
Test status
Simulation time 22354468 ps
CPU time 0.83 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 196176 kb
Host smart-6064378d-0369-4b8e-bb25-311750b5f54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523219801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.2523219801
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1880189389
Short name T297
Test name
Test status
Simulation time 294478422 ps
CPU time 14.75 seconds
Started Mar 07 01:20:50 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 197200 kb
Host smart-68029864-5acf-4152-8ad9-ea1048b01b83
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880189389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1880189389
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.2763489073
Short name T212
Test name
Test status
Simulation time 149291665 ps
CPU time 0.75 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 194940 kb
Host smart-f6ec99fc-81b3-4e93-b5b2-86d0506b0cda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763489073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.2763489073
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3092354322
Short name T586
Test name
Test status
Simulation time 450161298 ps
CPU time 0.82 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:49 PM PST 24
Peak memory 195532 kb
Host smart-cd9deffe-6c9c-4964-95dd-07d6b93ed58e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092354322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3092354322
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2271541183
Short name T375
Test name
Test status
Simulation time 61990683 ps
CPU time 1.44 seconds
Started Mar 07 01:20:44 PM PST 24
Finished Mar 07 01:20:46 PM PST 24
Peak memory 196556 kb
Host smart-eee26d46-0f4a-40a6-93e4-6aa5b1f39603
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271541183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2271541183
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.489782752
Short name T451
Test name
Test status
Simulation time 157695463 ps
CPU time 1.12 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 195820 kb
Host smart-3c9048a3-7ec7-4ad6-bb12-304061d14dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489782752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
489782752
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2282394338
Short name T262
Test name
Test status
Simulation time 19463714 ps
CPU time 0.62 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:35 PM PST 24
Peak memory 194168 kb
Host smart-1628f581-548f-47d9-b923-c0f32a475a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282394338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2282394338
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.1699133519
Short name T474
Test name
Test status
Simulation time 83599772 ps
CPU time 1.42 seconds
Started Mar 07 01:20:32 PM PST 24
Finished Mar 07 01:20:34 PM PST 24
Peak memory 195924 kb
Host smart-aa6fe400-5100-471f-b0ce-dbe5120a8d49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699133519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.1699133519
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.1775271491
Short name T567
Test name
Test status
Simulation time 166487418 ps
CPU time 3.65 seconds
Started Mar 07 01:20:45 PM PST 24
Finished Mar 07 01:20:49 PM PST 24
Peak memory 197928 kb
Host smart-c0349e50-9ee4-45a2-acf6-edbac5e2d518
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775271491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.1775271491
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.734599294
Short name T125
Test name
Test status
Simulation time 417388067 ps
CPU time 0.85 seconds
Started Mar 07 01:20:36 PM PST 24
Finished Mar 07 01:20:37 PM PST 24
Peak memory 197192 kb
Host smart-3dd4ca54-f2fd-4454-b62e-7e473da4d376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734599294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.734599294
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.738843670
Short name T575
Test name
Test status
Simulation time 358996213 ps
CPU time 1.23 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:20:37 PM PST 24
Peak memory 196496 kb
Host smart-e2401882-8167-4bda-a309-1edb47101df1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738843670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.738843670
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1112979110
Short name T294
Test name
Test status
Simulation time 11101245551 ps
CPU time 149.54 seconds
Started Mar 07 01:20:50 PM PST 24
Finished Mar 07 01:23:21 PM PST 24
Peak memory 198344 kb
Host smart-9bcc93fe-ef71-4904-98c1-4c315c1ffa0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112979110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1112979110
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1541357570
Short name T364
Test name
Test status
Simulation time 37426981 ps
CPU time 0.65 seconds
Started Mar 07 01:20:49 PM PST 24
Finished Mar 07 01:20:50 PM PST 24
Peak memory 194080 kb
Host smart-da372b6b-c983-459c-a3f9-0a34b974e83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541357570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1541357570
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.452494281
Short name T281
Test name
Test status
Simulation time 43875287 ps
CPU time 0.99 seconds
Started Mar 07 01:20:45 PM PST 24
Finished Mar 07 01:20:46 PM PST 24
Peak memory 196836 kb
Host smart-52d0e4b8-cfcb-4201-aec3-7caa93bac442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452494281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.452494281
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.846346442
Short name T54
Test name
Test status
Simulation time 3663254103 ps
CPU time 25.72 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:21:12 PM PST 24
Peak memory 197664 kb
Host smart-dba21fce-519c-4481-88c2-7386da1bf099
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846346442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.846346442
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1328250413
Short name T508
Test name
Test status
Simulation time 90564139 ps
CPU time 0.68 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:20:46 PM PST 24
Peak memory 195424 kb
Host smart-5faddab4-e068-47d9-8f75-677624126022
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328250413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1328250413
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.5667082
Short name T344
Test name
Test status
Simulation time 71152082 ps
CPU time 0.66 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 194260 kb
Host smart-7628cf67-e4fa-4b26-b9aa-f1ae3eb51755
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5667082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.5667082
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.1444514096
Short name T216
Test name
Test status
Simulation time 90158850 ps
CPU time 3.46 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:51 PM PST 24
Peak memory 198260 kb
Host smart-768400f8-c2ed-4651-a78f-9bbab095a30e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444514096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.1444514096
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1651632977
Short name T550
Test name
Test status
Simulation time 115655157 ps
CPU time 2.38 seconds
Started Mar 07 01:20:49 PM PST 24
Finished Mar 07 01:20:52 PM PST 24
Peak memory 196904 kb
Host smart-3ad5057f-1749-4502-b493-cffba400d499
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651632977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1651632977
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1898218554
Short name T74
Test name
Test status
Simulation time 276974714 ps
CPU time 0.86 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:20:47 PM PST 24
Peak memory 196064 kb
Host smart-513e15c8-ab5e-4875-bff1-89f659b9d061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898218554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1898218554
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.242893374
Short name T675
Test name
Test status
Simulation time 41978295 ps
CPU time 0.63 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:49 PM PST 24
Peak memory 195012 kb
Host smart-c59cb6ef-d5bc-43b0-8bb3-1e9586b7c377
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242893374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.242893374
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3794458109
Short name T719
Test name
Test status
Simulation time 177952842 ps
CPU time 1.82 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:20:49 PM PST 24
Peak memory 198064 kb
Host smart-215daaeb-779c-41aa-aa16-1c997b82b205
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794458109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3794458109
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1127931686
Short name T182
Test name
Test status
Simulation time 126699939 ps
CPU time 1.16 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:20:47 PM PST 24
Peak memory 196660 kb
Host smart-cd7c7411-fe67-41f4-af69-45e01fd5ead1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127931686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1127931686
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1214571806
Short name T571
Test name
Test status
Simulation time 157739646 ps
CPU time 1.12 seconds
Started Mar 07 01:20:50 PM PST 24
Finished Mar 07 01:20:52 PM PST 24
Peak memory 195852 kb
Host smart-239b9880-b402-41f3-b381-c5bc73873c96
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214571806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1214571806
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.871320902
Short name T640
Test name
Test status
Simulation time 14482906791 ps
CPU time 186.94 seconds
Started Mar 07 01:20:49 PM PST 24
Finished Mar 07 01:23:57 PM PST 24
Peak memory 198368 kb
Host smart-16a74ec0-7a21-40e4-8009-6e487279128d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871320902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.871320902
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.4266908325
Short name T506
Test name
Test status
Simulation time 43291229699 ps
CPU time 584.09 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:30:31 PM PST 24
Peak memory 198520 kb
Host smart-288df040-328c-407e-a71d-dde043221da3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4266908325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.4266908325
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.207328854
Short name T650
Test name
Test status
Simulation time 29705135 ps
CPU time 0.58 seconds
Started Mar 07 01:20:45 PM PST 24
Finished Mar 07 01:20:46 PM PST 24
Peak memory 194108 kb
Host smart-1ce7e9eb-2b0e-4810-8db5-1864652502f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207328854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.207328854
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2062507672
Short name T440
Test name
Test status
Simulation time 20972022 ps
CPU time 0.72 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 194300 kb
Host smart-12675e9c-a1c1-4203-bf5b-3ec183b315a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062507672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2062507672
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.618019108
Short name T287
Test name
Test status
Simulation time 133962452 ps
CPU time 7.12 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:55 PM PST 24
Peak memory 195604 kb
Host smart-83a8c8a6-542e-46f3-bc4b-d6ff69a52098
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618019108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stres
s.618019108
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2247627348
Short name T113
Test name
Test status
Simulation time 227444863 ps
CPU time 1.01 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:20:47 PM PST 24
Peak memory 198116 kb
Host smart-8df1f5f2-33c3-4814-9ddf-f65077f055cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247627348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2247627348
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.4105904159
Short name T350
Test name
Test status
Simulation time 55583234 ps
CPU time 1.1 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 195996 kb
Host smart-1d6ca1bb-5739-42ab-ac68-1ad0fcc8b29e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105904159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.4105904159
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.4127536315
Short name T79
Test name
Test status
Simulation time 1122499343 ps
CPU time 3.26 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:52 PM PST 24
Peak memory 198252 kb
Host smart-77942664-6377-4a3c-aadc-74232df50b21
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127536315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.4127536315
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.833603463
Short name T580
Test name
Test status
Simulation time 135300579 ps
CPU time 3.13 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:20:49 PM PST 24
Peak memory 197428 kb
Host smart-364434f3-e3a7-470b-8d2f-360a1ffad20b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833603463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
833603463
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3059467246
Short name T148
Test name
Test status
Simulation time 14029603 ps
CPU time 0.69 seconds
Started Mar 07 01:20:50 PM PST 24
Finished Mar 07 01:20:51 PM PST 24
Peak memory 195424 kb
Host smart-b93cf146-b58d-4662-8746-d8edebf908dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059467246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3059467246
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3797219776
Short name T388
Test name
Test status
Simulation time 18158557 ps
CPU time 0.68 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:20:46 PM PST 24
Peak memory 194408 kb
Host smart-d0589666-7672-4614-a782-31e83feb7fcd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797219776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3797219776
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3785453015
Short name T599
Test name
Test status
Simulation time 111786220 ps
CPU time 1.49 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:49 PM PST 24
Peak memory 198064 kb
Host smart-4cd37e72-2292-47d3-9326-e0f5ac6a808b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785453015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3785453015
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3183970270
Short name T237
Test name
Test status
Simulation time 78395045 ps
CPU time 1.36 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:49 PM PST 24
Peak memory 196996 kb
Host smart-943d8ee6-d9e9-4a46-89f3-52f5258a57c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183970270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3183970270
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2799432096
Short name T660
Test name
Test status
Simulation time 38201788 ps
CPU time 0.92 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:49 PM PST 24
Peak memory 195972 kb
Host smart-6292d55d-42e1-4b12-adc3-22a09274b4c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799432096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2799432096
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.2025004056
Short name T214
Test name
Test status
Simulation time 36246281689 ps
CPU time 120.95 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:22:47 PM PST 24
Peak memory 198380 kb
Host smart-86edd461-f7ea-4155-a478-31bba3730972
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025004056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.2025004056
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.418925663
Short name T36
Test name
Test status
Simulation time 154753622748 ps
CPU time 3058.56 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 02:11:46 PM PST 24
Peak memory 198496 kb
Host smart-762ac800-be8d-4d5b-98fe-1f35d1e38c26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=418925663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.418925663
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2942303898
Short name T624
Test name
Test status
Simulation time 38477194 ps
CPU time 0.6 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 194056 kb
Host smart-e40b4355-3987-4680-89d1-6d9daeb2655a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942303898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2942303898
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.499762120
Short name T606
Test name
Test status
Simulation time 26594136 ps
CPU time 0.83 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:49 PM PST 24
Peak memory 196156 kb
Host smart-c70fe522-e65b-49b5-9ae7-c9bd20fd7177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499762120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.499762120
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.4184019
Short name T218
Test name
Test status
Simulation time 3825021817 ps
CPU time 26.61 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:21:15 PM PST 24
Peak memory 196856 kb
Host smart-d57b51ed-343c-4676-825b-3f6709671d06
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_s
tress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stress.4184019
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.649158050
Short name T438
Test name
Test status
Simulation time 237070850 ps
CPU time 0.94 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 197868 kb
Host smart-15111e58-1b9d-4d2f-9209-dd4872543703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649158050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.649158050
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3027704086
Short name T591
Test name
Test status
Simulation time 91856708 ps
CPU time 0.85 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 196728 kb
Host smart-5d7ced1c-88c1-447b-a248-cad06492220b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027704086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3027704086
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.1722799031
Short name T157
Test name
Test status
Simulation time 140136389 ps
CPU time 1.73 seconds
Started Mar 07 01:20:50 PM PST 24
Finished Mar 07 01:20:52 PM PST 24
Peak memory 198104 kb
Host smart-9bbedcc5-8200-4699-85e5-e80f45727e4e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722799031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.1722799031
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1631426415
Short name T155
Test name
Test status
Simulation time 212766285 ps
CPU time 1.49 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:50 PM PST 24
Peak memory 196196 kb
Host smart-e0f08edf-bbc7-4162-9712-afc9542bfc08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631426415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1631426415
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3749018927
Short name T167
Test name
Test status
Simulation time 103195714 ps
CPU time 1.37 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:50 PM PST 24
Peak memory 198136 kb
Host smart-97263f2b-27cc-4384-8f93-2495c03e07e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749018927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3749018927
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.827924187
Short name T486
Test name
Test status
Simulation time 166374220 ps
CPU time 1.04 seconds
Started Mar 07 01:20:49 PM PST 24
Finished Mar 07 01:20:51 PM PST 24
Peak memory 195948 kb
Host smart-a64be536-b151-40af-a960-45c4e107a75b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827924187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.827924187
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.638302681
Short name T2
Test name
Test status
Simulation time 452262852 ps
CPU time 5.24 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:20:51 PM PST 24
Peak memory 198220 kb
Host smart-ff454673-1779-4bb7-be5a-89fb60178ba3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638302681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.638302681
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.4166452888
Short name T547
Test name
Test status
Simulation time 295050849 ps
CPU time 1.42 seconds
Started Mar 07 01:20:45 PM PST 24
Finished Mar 07 01:20:47 PM PST 24
Peak memory 196804 kb
Host smart-b4afab23-dd26-43b8-a207-a8ea1f4b326f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166452888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.4166452888
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3945732555
Short name T467
Test name
Test status
Simulation time 159896738 ps
CPU time 1.14 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 195616 kb
Host smart-a006f5e5-5896-408f-9c65-939d2ed119fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945732555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3945732555
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.2970998735
Short name T527
Test name
Test status
Simulation time 12735750490 ps
CPU time 38.31 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:21:25 PM PST 24
Peak memory 198324 kb
Host smart-590ab515-260c-4194-a2a1-7a6c46d06d80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970998735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.2970998735
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3378627913
Short name T448
Test name
Test status
Simulation time 169794661 ps
CPU time 0.87 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 196572 kb
Host smart-0f2497fa-c4b0-4142-b9ac-2a74bc6ac781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378627913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3378627913
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2992639072
Short name T380
Test name
Test status
Simulation time 2766036743 ps
CPU time 4.7 seconds
Started Mar 07 01:20:52 PM PST 24
Finished Mar 07 01:20:56 PM PST 24
Peak memory 196552 kb
Host smart-154773c9-92fa-4544-a7aa-24432a7107e5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992639072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2992639072
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3749808207
Short name T405
Test name
Test status
Simulation time 128775405 ps
CPU time 0.93 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 197856 kb
Host smart-69792586-1d5d-465f-b248-4ff2b1baf159
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749808207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3749808207
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3923464079
Short name T534
Test name
Test status
Simulation time 94677142 ps
CPU time 0.94 seconds
Started Mar 07 01:20:45 PM PST 24
Finished Mar 07 01:20:46 PM PST 24
Peak memory 196872 kb
Host smart-f00174b3-ff0b-4676-80d9-bd7b920729ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923464079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3923464079
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2846324756
Short name T555
Test name
Test status
Simulation time 59389549 ps
CPU time 2.33 seconds
Started Mar 07 01:20:50 PM PST 24
Finished Mar 07 01:20:53 PM PST 24
Peak memory 198236 kb
Host smart-57b0e67f-e4dd-4f81-add4-f7c8442ee409
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846324756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2846324756
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.4175885011
Short name T635
Test name
Test status
Simulation time 60374457 ps
CPU time 0.86 seconds
Started Mar 07 01:20:52 PM PST 24
Finished Mar 07 01:20:53 PM PST 24
Peak memory 194592 kb
Host smart-27bf620b-e6f5-4d19-8782-9890d7498836
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175885011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.4175885011
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.2307303265
Short name T338
Test name
Test status
Simulation time 36529803 ps
CPU time 0.91 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 196180 kb
Host smart-05d4bde1-0b15-4dff-b96d-3e5d22a5425a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307303265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.2307303265
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.3741723343
Short name T452
Test name
Test status
Simulation time 35592373 ps
CPU time 0.99 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:49 PM PST 24
Peak memory 196164 kb
Host smart-5e4600c5-7436-474b-a5c9-a9a1c698eb36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741723343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.3741723343
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.1616688784
Short name T607
Test name
Test status
Simulation time 1235915166 ps
CPU time 5.33 seconds
Started Mar 07 01:20:50 PM PST 24
Finished Mar 07 01:20:56 PM PST 24
Peak memory 198068 kb
Host smart-756f82ba-01c6-4387-8a34-8b9a520f5b7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616688784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.1616688784
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.1961079254
Short name T152
Test name
Test status
Simulation time 151226423 ps
CPU time 0.87 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:20:47 PM PST 24
Peak memory 195644 kb
Host smart-5cc0d227-0e07-4f8e-a177-1d29193d7966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961079254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.1961079254
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.490915938
Short name T516
Test name
Test status
Simulation time 37242181 ps
CPU time 1.12 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:20:48 PM PST 24
Peak memory 195908 kb
Host smart-50ac95ef-9eca-4775-9b9d-265bdf2ec517
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490915938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.490915938
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2280722689
Short name T569
Test name
Test status
Simulation time 27494700549 ps
CPU time 184.36 seconds
Started Mar 07 01:20:46 PM PST 24
Finished Mar 07 01:23:50 PM PST 24
Peak memory 198400 kb
Host smart-f97a2e78-8ed9-45a5-b5b8-1b1be54c2c29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280722689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2280722689
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.125572548
Short name T108
Test name
Test status
Simulation time 295510177503 ps
CPU time 1879.31 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:52:07 PM PST 24
Peak memory 198456 kb
Host smart-dbb37d07-3091-47e3-8ec3-2861960c2d91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=125572548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.125572548
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2292442044
Short name T413
Test name
Test status
Simulation time 37893736 ps
CPU time 0.62 seconds
Started Mar 07 01:21:03 PM PST 24
Finished Mar 07 01:21:04 PM PST 24
Peak memory 194068 kb
Host smart-3acd93a7-e8c8-4085-a955-b8fddec38941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292442044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2292442044
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.125816869
Short name T654
Test name
Test status
Simulation time 120639174 ps
CPU time 0.92 seconds
Started Mar 07 01:20:51 PM PST 24
Finished Mar 07 01:20:52 PM PST 24
Peak memory 196800 kb
Host smart-27e037fe-edd5-44e2-b66b-705d46183394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125816869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.125816869
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3809492280
Short name T653
Test name
Test status
Simulation time 4377845512 ps
CPU time 19.2 seconds
Started Mar 07 01:20:51 PM PST 24
Finished Mar 07 01:21:11 PM PST 24
Peak memory 198332 kb
Host smart-fbda7c5b-17df-44f2-930f-e68295854799
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809492280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3809492280
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.4152857564
Short name T680
Test name
Test status
Simulation time 86901604 ps
CPU time 1.13 seconds
Started Mar 07 01:20:58 PM PST 24
Finished Mar 07 01:21:00 PM PST 24
Peak memory 196752 kb
Host smart-a9856fe8-6ef0-4ced-8380-707d3fe63195
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152857564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.4152857564
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2930094068
Short name T146
Test name
Test status
Simulation time 39501311 ps
CPU time 1.05 seconds
Started Mar 07 01:20:49 PM PST 24
Finished Mar 07 01:20:50 PM PST 24
Peak memory 195796 kb
Host smart-cda44a68-ce55-4727-8452-b853f0f8ce2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930094068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2930094068
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2507515355
Short name T643
Test name
Test status
Simulation time 55856275 ps
CPU time 1.45 seconds
Started Mar 07 01:20:49 PM PST 24
Finished Mar 07 01:20:51 PM PST 24
Peak memory 197920 kb
Host smart-288f3a34-7092-40f4-bce3-0953c8403761
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507515355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2507515355
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.839483144
Short name T678
Test name
Test status
Simulation time 157610506 ps
CPU time 3.45 seconds
Started Mar 07 01:20:47 PM PST 24
Finished Mar 07 01:20:51 PM PST 24
Peak memory 196724 kb
Host smart-4af9fa2d-c9d9-44b0-af0e-184e149354cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839483144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger.
839483144
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2072706567
Short name T431
Test name
Test status
Simulation time 57366730 ps
CPU time 1.17 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:50 PM PST 24
Peak memory 196668 kb
Host smart-3c59ec45-4b28-4c25-b5b9-d07e16263cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072706567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2072706567
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3049377949
Short name T444
Test name
Test status
Simulation time 54502664 ps
CPU time 1.08 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:49 PM PST 24
Peak memory 196016 kb
Host smart-bcfd130c-dec6-42ee-9774-333c12153fd5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049377949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3049377949
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.2243953081
Short name T251
Test name
Test status
Simulation time 29542759 ps
CPU time 1.3 seconds
Started Mar 07 01:20:51 PM PST 24
Finished Mar 07 01:20:53 PM PST 24
Peak memory 198024 kb
Host smart-ac694409-f737-47f2-8181-f5dff01324b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243953081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.2243953081
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2023889810
Short name T542
Test name
Test status
Simulation time 64284860 ps
CPU time 1.09 seconds
Started Mar 07 01:20:51 PM PST 24
Finished Mar 07 01:20:52 PM PST 24
Peak memory 196684 kb
Host smart-55dbbe1f-63d3-4257-940c-56703e85b7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023889810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2023889810
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3496753949
Short name T188
Test name
Test status
Simulation time 1365677693 ps
CPU time 1.46 seconds
Started Mar 07 01:20:48 PM PST 24
Finished Mar 07 01:20:50 PM PST 24
Peak memory 196872 kb
Host smart-3c71c114-13af-4d31-8887-a5059b8d8562
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496753949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3496753949
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2921195249
Short name T8
Test name
Test status
Simulation time 20442232690 ps
CPU time 231.58 seconds
Started Mar 07 01:20:56 PM PST 24
Finished Mar 07 01:24:48 PM PST 24
Peak memory 198388 kb
Host smart-dba45b36-d3db-4ede-a31e-49b5d48afa7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921195249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2921195249
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2449749249
Short name T80
Test name
Test status
Simulation time 387290606437 ps
CPU time 2438.24 seconds
Started Mar 07 01:21:02 PM PST 24
Finished Mar 07 02:01:40 PM PST 24
Peak memory 198472 kb
Host smart-f7e33447-57fd-40ad-a4fc-2d014ffc1986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2449749249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2449749249
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.492409258
Short name T266
Test name
Test status
Simulation time 61457608 ps
CPU time 0.56 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 195860 kb
Host smart-6e7ed5df-bf9f-478d-87b1-fcc7d392bd17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492409258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.492409258
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.870894709
Short name T318
Test name
Test status
Simulation time 13141853 ps
CPU time 0.63 seconds
Started Mar 07 01:21:01 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 194060 kb
Host smart-02060f29-260d-46b0-b983-d288c867af0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870894709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.870894709
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2497754184
Short name T655
Test name
Test status
Simulation time 812455008 ps
CPU time 23.04 seconds
Started Mar 07 01:21:01 PM PST 24
Finished Mar 07 01:21:24 PM PST 24
Peak memory 196452 kb
Host smart-cc33e586-2a56-4b44-b432-e03ed379579f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497754184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2497754184
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.2296892749
Short name T288
Test name
Test status
Simulation time 29468225 ps
CPU time 0.63 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 194556 kb
Host smart-3a82c9bf-9859-499d-b8be-f3b816b3ae75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296892749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.2296892749
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2925908683
Short name T648
Test name
Test status
Simulation time 118667488 ps
CPU time 1.22 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 195896 kb
Host smart-45b175f7-78f5-4529-abbb-2676f88f9982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925908683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2925908683
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.863230085
Short name T638
Test name
Test status
Simulation time 371860010 ps
CPU time 2.39 seconds
Started Mar 07 01:21:03 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 198216 kb
Host smart-651cada9-1e5c-4c4c-9b95-b420ed22b7fc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863230085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.gpio_intr_with_filter_rand_intr_event.863230085
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.281488427
Short name T284
Test name
Test status
Simulation time 128236585 ps
CPU time 1.02 seconds
Started Mar 07 01:20:59 PM PST 24
Finished Mar 07 01:21:00 PM PST 24
Peak memory 196364 kb
Host smart-1a6cf682-ec60-46a7-ae33-d6a82a2d5ad8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281488427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
281488427
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1561816963
Short name T718
Test name
Test status
Simulation time 305309019 ps
CPU time 0.96 seconds
Started Mar 07 01:20:59 PM PST 24
Finished Mar 07 01:21:00 PM PST 24
Peak memory 196036 kb
Host smart-d570c2d0-2618-45b0-8f49-be796a7b13e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561816963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1561816963
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2411361274
Short name T22
Test name
Test status
Simulation time 50395310 ps
CPU time 1.05 seconds
Started Mar 07 01:21:03 PM PST 24
Finished Mar 07 01:21:04 PM PST 24
Peak memory 196160 kb
Host smart-7ec5c658-7f50-4643-8d10-4229f781d10e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411361274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2411361274
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2652681354
Short name T341
Test name
Test status
Simulation time 89117934 ps
CPU time 1.38 seconds
Started Mar 07 01:20:57 PM PST 24
Finished Mar 07 01:20:59 PM PST 24
Peak memory 198152 kb
Host smart-c8e6a329-bc12-4026-8219-de3f06c52a3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652681354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2652681354
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.3886113202
Short name T631
Test name
Test status
Simulation time 321840383 ps
CPU time 1.34 seconds
Started Mar 07 01:20:57 PM PST 24
Finished Mar 07 01:20:58 PM PST 24
Peak memory 195696 kb
Host smart-4461124d-68d8-4d15-bc68-dd6e302fd63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886113202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.3886113202
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.2864154459
Short name T14
Test name
Test status
Simulation time 79508932 ps
CPU time 0.97 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 196608 kb
Host smart-2e3b2e64-9f3d-4f8a-9310-0edc05924dd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864154459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.2864154459
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.566020711
Short name T610
Test name
Test status
Simulation time 58567700709 ps
CPU time 163.41 seconds
Started Mar 07 01:20:57 PM PST 24
Finished Mar 07 01:23:41 PM PST 24
Peak memory 198348 kb
Host smart-ef252404-6108-4dbc-ae2c-4cdcef39f8aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566020711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.566020711
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1729018038
Short name T700
Test name
Test status
Simulation time 58369909629 ps
CPU time 1014.95 seconds
Started Mar 07 01:20:56 PM PST 24
Finished Mar 07 01:37:51 PM PST 24
Peak memory 198444 kb
Host smart-adc8ca86-6b9a-406d-9995-42922877a0e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1729018038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1729018038
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1373535789
Short name T582
Test name
Test status
Simulation time 18927123 ps
CPU time 0.55 seconds
Started Mar 07 01:20:12 PM PST 24
Finished Mar 07 01:20:12 PM PST 24
Peak memory 194092 kb
Host smart-41e54456-e0d1-47b1-9fd0-18465f3077aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373535789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1373535789
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.3456507434
Short name T373
Test name
Test status
Simulation time 90296323 ps
CPU time 0.73 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 195352 kb
Host smart-fc60bcb9-a88f-4c38-b053-c83894b11e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456507434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.3456507434
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3186249111
Short name T71
Test name
Test status
Simulation time 7245359883 ps
CPU time 23.74 seconds
Started Mar 07 01:20:06 PM PST 24
Finished Mar 07 01:20:31 PM PST 24
Peak memory 198280 kb
Host smart-4524873f-a33d-4ad6-b912-68fc51e43938
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186249111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3186249111
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.886852241
Short name T124
Test name
Test status
Simulation time 130136884 ps
CPU time 0.61 seconds
Started Mar 07 01:20:12 PM PST 24
Finished Mar 07 01:20:13 PM PST 24
Peak memory 194856 kb
Host smart-bc29aede-c84b-43b5-b3d1-ac5499a7aae4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886852241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.886852241
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.689357257
Short name T174
Test name
Test status
Simulation time 259494241 ps
CPU time 1.22 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 195976 kb
Host smart-8eebcf3a-083a-4e15-b713-45cd9494af1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689357257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.689357257
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.27044702
Short name T15
Test name
Test status
Simulation time 370636752 ps
CPU time 1.44 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 196916 kb
Host smart-b147d5a4-1d82-449a-adef-eade6113cd5f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27044702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.gpio_intr_with_filter_rand_intr_event.27044702
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3524525837
Short name T286
Test name
Test status
Simulation time 230769127 ps
CPU time 1.47 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 196852 kb
Host smart-d14e50b4-4ccc-498f-b365-c16bfe00b629
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524525837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3524525837
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3634272126
Short name T419
Test name
Test status
Simulation time 20445415 ps
CPU time 0.78 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 195532 kb
Host smart-9038eb79-d4c1-4ffa-be29-f0a3b5e18592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634272126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3634272126
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1787653767
Short name T651
Test name
Test status
Simulation time 306884353 ps
CPU time 0.87 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 196148 kb
Host smart-15b381e7-d4b8-4887-8635-f9fa4b3fcb3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787653767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1787653767
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.163211324
Short name T346
Test name
Test status
Simulation time 411274816 ps
CPU time 2.77 seconds
Started Mar 07 01:20:02 PM PST 24
Finished Mar 07 01:20:05 PM PST 24
Peak memory 198144 kb
Host smart-621dbdfc-eb0c-4e24-a900-d371b76a47b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163211324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.163211324
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1390955956
Short name T41
Test name
Test status
Simulation time 556963133 ps
CPU time 1 seconds
Started Mar 07 01:20:14 PM PST 24
Finished Mar 07 01:20:15 PM PST 24
Peak memory 214900 kb
Host smart-a6ac87d3-80ee-4709-bcc5-15f2992131e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390955956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1390955956
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2818946219
Short name T309
Test name
Test status
Simulation time 30965436 ps
CPU time 0.91 seconds
Started Mar 07 01:20:07 PM PST 24
Finished Mar 07 01:20:08 PM PST 24
Peak memory 196168 kb
Host smart-962935fd-5c7d-479b-90ac-90aec92b99c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818946219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2818946219
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3610637058
Short name T381
Test name
Test status
Simulation time 509822964 ps
CPU time 1.09 seconds
Started Mar 07 01:20:05 PM PST 24
Finished Mar 07 01:20:06 PM PST 24
Peak memory 195872 kb
Host smart-00b064d2-66a8-462d-b8d4-05c72886ab9d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610637058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3610637058
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.556371839
Short name T621
Test name
Test status
Simulation time 17771189632 ps
CPU time 146.65 seconds
Started Mar 07 01:20:10 PM PST 24
Finished Mar 07 01:22:37 PM PST 24
Peak memory 198328 kb
Host smart-ef429664-f015-40bf-aeaf-a5ac7bd46d73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556371839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.556371839
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.392186823
Short name T150
Test name
Test status
Simulation time 13871815 ps
CPU time 0.58 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 194308 kb
Host smart-2d6c7905-5ffc-4089-8006-42d9f19472bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392186823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.392186823
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2709753112
Short name T247
Test name
Test status
Simulation time 113644472 ps
CPU time 0.84 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 195604 kb
Host smart-f2f742fa-a950-4bc2-bb55-7d96e2d54f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709753112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2709753112
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3681168197
Short name T139
Test name
Test status
Simulation time 451081188 ps
CPU time 6.15 seconds
Started Mar 07 01:20:59 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 195676 kb
Host smart-57c35325-e151-419a-a78c-b410474537e9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681168197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3681168197
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2065665888
Short name T77
Test name
Test status
Simulation time 211910600 ps
CPU time 0.99 seconds
Started Mar 07 01:20:58 PM PST 24
Finished Mar 07 01:20:59 PM PST 24
Peak memory 196508 kb
Host smart-cc6f2647-ba5f-43e2-b72f-14e630cee440
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065665888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2065665888
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.611168178
Short name T202
Test name
Test status
Simulation time 90082734 ps
CPU time 0.94 seconds
Started Mar 07 01:20:59 PM PST 24
Finished Mar 07 01:21:00 PM PST 24
Peak memory 196788 kb
Host smart-46f1d90e-40ed-4caf-9b78-cfe49fae3117
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611168178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.611168178
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.1970577942
Short name T366
Test name
Test status
Simulation time 243864579 ps
CPU time 2.56 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:03 PM PST 24
Peak memory 197860 kb
Host smart-f52ea1f1-40de-446e-809d-9210be8dba2a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970577942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.1970577942
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.457782059
Short name T574
Test name
Test status
Simulation time 37891336 ps
CPU time 0.94 seconds
Started Mar 07 01:20:59 PM PST 24
Finished Mar 07 01:21:00 PM PST 24
Peak memory 195668 kb
Host smart-08ffaf54-8b9e-4481-918a-760ff54a32ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457782059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
457782059
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1379492267
Short name T322
Test name
Test status
Simulation time 54366120 ps
CPU time 1.22 seconds
Started Mar 07 01:20:57 PM PST 24
Finished Mar 07 01:20:58 PM PST 24
Peak memory 196772 kb
Host smart-6654fc78-6919-4da6-82a3-a2562a617e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379492267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1379492267
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.1745373885
Short name T497
Test name
Test status
Simulation time 14018544 ps
CPU time 0.62 seconds
Started Mar 07 01:20:59 PM PST 24
Finished Mar 07 01:21:00 PM PST 24
Peak memory 194260 kb
Host smart-19015bb1-aada-4d57-809c-f5ee5e95210c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745373885 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.1745373885
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2334711066
Short name T206
Test name
Test status
Simulation time 772864891 ps
CPU time 5.53 seconds
Started Mar 07 01:20:58 PM PST 24
Finished Mar 07 01:21:03 PM PST 24
Peak memory 198180 kb
Host smart-95c5c0d3-53b1-4fc5-89f0-d48101830483
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334711066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2334711066
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.4219442746
Short name T121
Test name
Test status
Simulation time 45185991 ps
CPU time 0.97 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:02 PM PST 24
Peak memory 196212 kb
Host smart-e6015920-99ba-4f7f-8acc-6939867e92a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219442746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.4219442746
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1261274228
Short name T705
Test name
Test status
Simulation time 219520467 ps
CPU time 1.13 seconds
Started Mar 07 01:20:57 PM PST 24
Finished Mar 07 01:20:58 PM PST 24
Peak memory 196552 kb
Host smart-b7aeb0bc-79c9-440b-a904-08c8f9fc4bb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261274228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1261274228
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1776511142
Short name T691
Test name
Test status
Simulation time 3633332784 ps
CPU time 73.6 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:22:17 PM PST 24
Peak memory 198344 kb
Host smart-032558e8-0c80-4b7e-aea7-44f58b85425f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776511142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1776511142
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3385326667
Short name T473
Test name
Test status
Simulation time 39260332 ps
CPU time 0.56 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 194084 kb
Host smart-57ba2fa9-a16d-4119-abf0-b01b635326fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385326667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3385326667
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3099200923
Short name T18
Test name
Test status
Simulation time 20768863 ps
CPU time 0.59 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:00 PM PST 24
Peak memory 194100 kb
Host smart-46489888-2ae0-4383-8fc7-5bc32d63d9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099200923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3099200923
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2573721868
Short name T710
Test name
Test status
Simulation time 793801449 ps
CPU time 19.82 seconds
Started Mar 07 01:21:01 PM PST 24
Finished Mar 07 01:21:21 PM PST 24
Peak memory 198112 kb
Host smart-6d96a01c-8c6d-4140-a661-36b22cb53285
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573721868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2573721868
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.809964009
Short name T703
Test name
Test status
Simulation time 149270494 ps
CPU time 0.73 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 194728 kb
Host smart-da24c0ea-ca51-444e-a2c7-e64932b91bac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809964009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.809964009
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2157458130
Short name T278
Test name
Test status
Simulation time 91641127 ps
CPU time 1.05 seconds
Started Mar 07 01:21:01 PM PST 24
Finished Mar 07 01:21:02 PM PST 24
Peak memory 196996 kb
Host smart-2d8b7731-694a-4a5b-af22-68e8303bc2b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157458130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2157458130
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.10292690
Short name T246
Test name
Test status
Simulation time 773560781 ps
CPU time 2.61 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:02 PM PST 24
Peak memory 198084 kb
Host smart-c5e49e4a-dd17-4481-9f94-10ca2acd0ecf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10292690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 21.gpio_intr_with_filter_rand_intr_event.10292690
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3094481353
Short name T706
Test name
Test status
Simulation time 169130563 ps
CPU time 1.18 seconds
Started Mar 07 01:21:01 PM PST 24
Finished Mar 07 01:21:02 PM PST 24
Peak memory 195856 kb
Host smart-2b263e30-9975-4cda-b8d3-8434b60b099b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094481353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3094481353
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3160533683
Short name T153
Test name
Test status
Simulation time 75095471 ps
CPU time 0.72 seconds
Started Mar 07 01:20:59 PM PST 24
Finished Mar 07 01:21:00 PM PST 24
Peak memory 194416 kb
Host smart-87d47fba-f06c-4ae7-acb5-6cd0edf2dbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160533683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3160533683
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.35625706
Short name T236
Test name
Test status
Simulation time 115780504 ps
CPU time 1.14 seconds
Started Mar 07 01:20:58 PM PST 24
Finished Mar 07 01:21:00 PM PST 24
Peak memory 197016 kb
Host smart-107976a2-064d-419e-b424-4366736a2216
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35625706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullup_
pulldown.35625706
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3203079024
Short name T274
Test name
Test status
Simulation time 331983547 ps
CPU time 5.55 seconds
Started Mar 07 01:21:01 PM PST 24
Finished Mar 07 01:21:07 PM PST 24
Peak memory 197932 kb
Host smart-db5866bd-e580-482d-bc48-6ef366f44728
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203079024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3203079024
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.10367483
Short name T191
Test name
Test status
Simulation time 37121375 ps
CPU time 1.2 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 195908 kb
Host smart-fa24c013-4e80-4cfe-a654-e4bb063c7f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10367483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.10367483
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.2878656906
Short name T544
Test name
Test status
Simulation time 35854135 ps
CPU time 1 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 195824 kb
Host smart-11d129f7-e86e-4311-aefb-15a687ad8fad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878656906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.2878656906
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.336703598
Short name T332
Test name
Test status
Simulation time 13620053006 ps
CPU time 196.23 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:24:20 PM PST 24
Peak memory 198296 kb
Host smart-23dd79e3-39d2-43bd-ad44-b09fa69471b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336703598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.336703598
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.1278502214
Short name T392
Test name
Test status
Simulation time 16070843 ps
CPU time 0.57 seconds
Started Mar 07 01:21:02 PM PST 24
Finished Mar 07 01:21:02 PM PST 24
Peak memory 194124 kb
Host smart-de4620a4-4f21-4bd2-b197-16f10e94bbbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278502214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.1278502214
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2024600188
Short name T252
Test name
Test status
Simulation time 41047794 ps
CPU time 0.81 seconds
Started Mar 07 01:21:02 PM PST 24
Finished Mar 07 01:21:03 PM PST 24
Peak memory 196020 kb
Host smart-91d20d9a-0399-441d-8d49-0fc3e7eb31f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024600188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2024600188
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.4219494152
Short name T425
Test name
Test status
Simulation time 3271370608 ps
CPU time 28.11 seconds
Started Mar 07 01:21:02 PM PST 24
Finished Mar 07 01:21:30 PM PST 24
Peak memory 197676 kb
Host smart-0da70c43-c724-4d96-b9a3-3ebf8b7db244
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219494152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.4219494152
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2544944573
Short name T503
Test name
Test status
Simulation time 292524494 ps
CPU time 0.98 seconds
Started Mar 07 01:21:02 PM PST 24
Finished Mar 07 01:21:03 PM PST 24
Peak memory 197864 kb
Host smart-edbc8772-0b44-4cd6-b4b2-aeacbddaac2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544944573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2544944573
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.1948010447
Short name T289
Test name
Test status
Simulation time 30814156 ps
CPU time 1 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 196584 kb
Host smart-5bc982fa-5962-44f6-866c-ff85d3d8e2f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948010447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.1948010447
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1033621058
Short name T329
Test name
Test status
Simulation time 64728396 ps
CPU time 1.93 seconds
Started Mar 07 01:21:03 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 198208 kb
Host smart-e6b39ab1-3907-453d-b5d1-b67042d7654d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033621058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1033621058
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2515633123
Short name T585
Test name
Test status
Simulation time 24332057 ps
CPU time 0.87 seconds
Started Mar 07 01:21:02 PM PST 24
Finished Mar 07 01:21:03 PM PST 24
Peak memory 195552 kb
Host smart-06e5be8a-3c6b-43a8-844b-ef2e646c723c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515633123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2515633123
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2120570065
Short name T663
Test name
Test status
Simulation time 56477287 ps
CPU time 1.09 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 196200 kb
Host smart-cc977c11-e152-4e00-bfd2-e27d8d4b4333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120570065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2120570065
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1168358195
Short name T450
Test name
Test status
Simulation time 58037360 ps
CPU time 1.23 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:02 PM PST 24
Peak memory 197140 kb
Host smart-8f49486e-38f5-45d5-884b-bd8fe19e8d36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168358195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1168358195
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1116170572
Short name T235
Test name
Test status
Simulation time 457814771 ps
CPU time 2.06 seconds
Started Mar 07 01:21:01 PM PST 24
Finished Mar 07 01:21:03 PM PST 24
Peak memory 198044 kb
Host smart-b0d9d791-6ba1-48c0-844a-108ec216508b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116170572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1116170572
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2115310468
Short name T312
Test name
Test status
Simulation time 23969533 ps
CPU time 0.72 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 194188 kb
Host smart-88434173-8a29-464a-b64a-333c3e467ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115310468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2115310468
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.362503741
Short name T622
Test name
Test status
Simulation time 142372349 ps
CPU time 1.06 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 195872 kb
Host smart-5e04fb10-5bdc-4422-baa7-6b1b5831395c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362503741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.362503741
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.880763329
Short name T9
Test name
Test status
Simulation time 3283386968 ps
CPU time 40.16 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:40 PM PST 24
Peak memory 198328 kb
Host smart-cc3bcba7-8788-4161-9e74-f8f604b3f86d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880763329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.g
pio_stress_all.880763329
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.2996875634
Short name T70
Test name
Test status
Simulation time 288472589141 ps
CPU time 855.57 seconds
Started Mar 07 01:21:01 PM PST 24
Finished Mar 07 01:35:17 PM PST 24
Peak memory 198464 kb
Host smart-32f977f8-c5c2-4b9c-8ff3-17ac6d83ddc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2996875634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.2996875634
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1045893442
Short name T336
Test name
Test status
Simulation time 42849554 ps
CPU time 0.58 seconds
Started Mar 07 01:21:13 PM PST 24
Finished Mar 07 01:21:14 PM PST 24
Peak memory 194888 kb
Host smart-3cf60c20-84cf-4330-b249-d793c89f3257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045893442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1045893442
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3174511219
Short name T347
Test name
Test status
Simulation time 103255323 ps
CPU time 0.78 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:21:06 PM PST 24
Peak memory 195356 kb
Host smart-f698fa3b-7bf4-46f1-bfd6-90d138bc5214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174511219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3174511219
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2895657207
Short name T507
Test name
Test status
Simulation time 1262994864 ps
CPU time 16.49 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:21:22 PM PST 24
Peak memory 195716 kb
Host smart-a8a240a6-14ce-4d20-b9b2-94750937ef33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895657207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2895657207
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1939679454
Short name T128
Test name
Test status
Simulation time 53935029 ps
CPU time 0.83 seconds
Started Mar 07 01:21:05 PM PST 24
Finished Mar 07 01:21:06 PM PST 24
Peak memory 195908 kb
Host smart-e0c5aea5-88fc-488f-9b8b-576a9b8ec9cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939679454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1939679454
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.233837538
Short name T134
Test name
Test status
Simulation time 27030679 ps
CPU time 0.68 seconds
Started Mar 07 01:21:05 PM PST 24
Finished Mar 07 01:21:06 PM PST 24
Peak memory 194492 kb
Host smart-fafae49a-3d26-4d07-8bd1-af46deca30bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233837538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.233837538
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.753158528
Short name T271
Test name
Test status
Simulation time 44643204 ps
CPU time 1.89 seconds
Started Mar 07 01:21:05 PM PST 24
Finished Mar 07 01:21:07 PM PST 24
Peak memory 198100 kb
Host smart-4ba7931d-702e-4a19-9e99-a1fa8a8c87e1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753158528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.gpio_intr_with_filter_rand_intr_event.753158528
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1026686635
Short name T187
Test name
Test status
Simulation time 393152846 ps
CPU time 1.67 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:21:07 PM PST 24
Peak memory 196208 kb
Host smart-1790c18f-1a13-48aa-b6be-0791ca986949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026686635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1026686635
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.410271579
Short name T686
Test name
Test status
Simulation time 61527921 ps
CPU time 1.41 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 197176 kb
Host smart-6c1fafbd-dd4f-452b-9824-20e789f73ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410271579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.410271579
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2356947605
Short name T679
Test name
Test status
Simulation time 21718819 ps
CPU time 0.82 seconds
Started Mar 07 01:21:05 PM PST 24
Finished Mar 07 01:21:06 PM PST 24
Peak memory 195348 kb
Host smart-6b6bee75-d60c-48b5-afda-2647738afdf1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356947605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2356947605
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.4042938028
Short name T10
Test name
Test status
Simulation time 294318610 ps
CPU time 3.62 seconds
Started Mar 07 01:21:10 PM PST 24
Finished Mar 07 01:21:14 PM PST 24
Peak memory 198148 kb
Host smart-16aad2be-78c7-4ea2-9898-240ab7582363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042938028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.4042938028
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.932149297
Short name T129
Test name
Test status
Simulation time 38168998 ps
CPU time 0.89 seconds
Started Mar 07 01:21:02 PM PST 24
Finished Mar 07 01:21:02 PM PST 24
Peak memory 196532 kb
Host smart-3cb0efb6-6e38-47d8-b4a8-f7384f33baac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932149297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.932149297
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3277456526
Short name T445
Test name
Test status
Simulation time 483578152 ps
CPU time 1.17 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:21:08 PM PST 24
Peak memory 195672 kb
Host smart-f439085a-7278-42c2-9e35-a397fdca5b20
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277456526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3277456526
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2541194125
Short name T499
Test name
Test status
Simulation time 8065460623 ps
CPU time 111.48 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:22:55 PM PST 24
Peak memory 198368 kb
Host smart-b1a380d1-cf09-457a-a527-180c15f0cc1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541194125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2541194125
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.4213469107
Short name T62
Test name
Test status
Simulation time 99955929740 ps
CPU time 713.11 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:32:57 PM PST 24
Peak memory 198416 kb
Host smart-c9455510-71cb-458d-a916-f4f85d669c9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4213469107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.4213469107
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2777000552
Short name T583
Test name
Test status
Simulation time 43889662 ps
CPU time 0.59 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:21:07 PM PST 24
Peak memory 194060 kb
Host smart-23736a54-564a-4419-b77f-33ad68c4a098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777000552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2777000552
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3740880846
Short name T510
Test name
Test status
Simulation time 36990893 ps
CPU time 0.87 seconds
Started Mar 07 01:21:11 PM PST 24
Finished Mar 07 01:21:12 PM PST 24
Peak memory 197240 kb
Host smart-a74a2757-9826-4ea8-be5b-0245b6ed28dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740880846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3740880846
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1406951160
Short name T662
Test name
Test status
Simulation time 558493768 ps
CPU time 27.05 seconds
Started Mar 07 01:21:01 PM PST 24
Finished Mar 07 01:21:28 PM PST 24
Peak memory 196656 kb
Host smart-b6868a8d-4288-4543-9c06-cca41ddb992d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406951160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1406951160
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.216849137
Short name T230
Test name
Test status
Simulation time 46764495 ps
CPU time 0.87 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 196112 kb
Host smart-7fb17c5c-9e88-4b25-89be-7649630bdfab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216849137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.216849137
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3508005713
Short name T356
Test name
Test status
Simulation time 202986004 ps
CPU time 0.98 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:02 PM PST 24
Peak memory 196192 kb
Host smart-24efb1a7-0ebe-4d78-9553-c33b2f770c9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508005713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3508005713
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1177979723
Short name T176
Test name
Test status
Simulation time 96872413 ps
CPU time 3.91 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:04 PM PST 24
Peak memory 198104 kb
Host smart-0bae3bb5-2d23-4da0-9411-e2388bd9dbf3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177979723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1177979723
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3511677056
Short name T73
Test name
Test status
Simulation time 888795366 ps
CPU time 2.96 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:03 PM PST 24
Peak memory 195896 kb
Host smart-bd73912c-bcaf-41f9-806c-5162dd942c48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511677056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3511677056
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3334280007
Short name T688
Test name
Test status
Simulation time 251915022 ps
CPU time 1.08 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 196688 kb
Host smart-12b37005-256f-4898-b036-12458920c006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334280007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3334280007
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2434760439
Short name T25
Test name
Test status
Simulation time 34567112 ps
CPU time 1.12 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:21:08 PM PST 24
Peak memory 195952 kb
Host smart-05ca8cdc-3f68-47c2-99eb-71d694ad67cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434760439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2434760439
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.4174141142
Short name T367
Test name
Test status
Simulation time 106264002 ps
CPU time 1.68 seconds
Started Mar 07 01:21:01 PM PST 24
Finished Mar 07 01:21:03 PM PST 24
Peak memory 198132 kb
Host smart-a2bf58ec-41c8-4eaf-9c7f-63bddddcad61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174141142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.4174141142
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2048238301
Short name T260
Test name
Test status
Simulation time 35137528 ps
CPU time 0.96 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:21:08 PM PST 24
Peak memory 195340 kb
Host smart-76cabea1-baac-497f-873a-6d6a4fd80713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048238301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2048238301
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1178752495
Short name T265
Test name
Test status
Simulation time 35889701 ps
CPU time 1.13 seconds
Started Mar 07 01:21:13 PM PST 24
Finished Mar 07 01:21:15 PM PST 24
Peak memory 195960 kb
Host smart-1c9a682c-d933-4027-b1f4-0c12990337a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178752495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1178752495
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2236100278
Short name T365
Test name
Test status
Simulation time 21223236424 ps
CPU time 159.54 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:23:40 PM PST 24
Peak memory 198416 kb
Host smart-5ce00387-6626-4379-b259-1ff70a9c17c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236100278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2236100278
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2929627744
Short name T60
Test name
Test status
Simulation time 366674273859 ps
CPU time 834.75 seconds
Started Mar 07 01:20:59 PM PST 24
Finished Mar 07 01:34:54 PM PST 24
Peak memory 198404 kb
Host smart-3d089625-c89e-48f0-b025-fec603d66a31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2929627744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2929627744
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.3682270462
Short name T335
Test name
Test status
Simulation time 15147855 ps
CPU time 0.61 seconds
Started Mar 07 01:21:19 PM PST 24
Finished Mar 07 01:21:20 PM PST 24
Peak memory 194324 kb
Host smart-4fb2edc3-4e34-4a70-ac24-3669d62cfa11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682270462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.3682270462
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3614759875
Short name T255
Test name
Test status
Simulation time 50580276 ps
CPU time 0.63 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:21:07 PM PST 24
Peak memory 194700 kb
Host smart-115d6c3a-33b0-4393-a3f8-16cc3df57fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614759875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3614759875
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.3581139211
Short name T348
Test name
Test status
Simulation time 1835572895 ps
CPU time 24.42 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:21:30 PM PST 24
Peak memory 195668 kb
Host smart-53b06d63-adc6-4f5b-b42f-db2755894093
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581139211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.3581139211
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1522031173
Short name T694
Test name
Test status
Simulation time 74249843 ps
CPU time 1.03 seconds
Started Mar 07 01:21:13 PM PST 24
Finished Mar 07 01:21:14 PM PST 24
Peak memory 196836 kb
Host smart-0745bf8c-3e85-4070-92b1-bd113126f3c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522031173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1522031173
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.51613533
Short name T334
Test name
Test status
Simulation time 70322665 ps
CPU time 1.21 seconds
Started Mar 07 01:21:00 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 196928 kb
Host smart-dec42e0a-4d28-4ffd-9ef5-848f033b4b5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51613533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.51613533
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2272960991
Short name T269
Test name
Test status
Simulation time 80782231 ps
CPU time 1 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 196148 kb
Host smart-7b50e598-6fbf-47ca-ae19-93d011dea947
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272960991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2272960991
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.3193193514
Short name T489
Test name
Test status
Simulation time 230419088 ps
CPU time 2.54 seconds
Started Mar 07 01:21:10 PM PST 24
Finished Mar 07 01:21:12 PM PST 24
Peak memory 198208 kb
Host smart-5a015033-f64d-4dd9-85d9-d2cb4da7018a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193193514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.3193193514
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.2793618120
Short name T259
Test name
Test status
Simulation time 368176698 ps
CPU time 1.05 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:21:08 PM PST 24
Peak memory 196940 kb
Host smart-c6f20a1e-3c59-4433-aff6-0096555c34b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793618120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.2793618120
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2178957904
Short name T645
Test name
Test status
Simulation time 128961368 ps
CPU time 1.33 seconds
Started Mar 07 01:21:01 PM PST 24
Finished Mar 07 01:21:02 PM PST 24
Peak memory 197252 kb
Host smart-d44e92c2-3443-4807-af94-4c3522858330
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178957904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2178957904
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1427963109
Short name T6
Test name
Test status
Simulation time 500740493 ps
CPU time 4.39 seconds
Started Mar 07 01:21:14 PM PST 24
Finished Mar 07 01:21:18 PM PST 24
Peak memory 197964 kb
Host smart-869f02af-4615-4270-9d6c-b5f24ed3c188
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427963109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1427963109
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3010761070
Short name T268
Test name
Test status
Simulation time 113157225 ps
CPU time 1.07 seconds
Started Mar 07 01:21:03 PM PST 24
Finished Mar 07 01:21:04 PM PST 24
Peak memory 195832 kb
Host smart-0fa32f71-3eb8-40f7-b75c-f2a2574a451d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010761070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3010761070
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.267174870
Short name T339
Test name
Test status
Simulation time 76152055 ps
CPU time 1.27 seconds
Started Mar 07 01:20:59 PM PST 24
Finished Mar 07 01:21:01 PM PST 24
Peak memory 197000 kb
Host smart-b4939eda-5f55-4ec0-9364-483d1d6d5a7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267174870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.267174870
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3710461437
Short name T669
Test name
Test status
Simulation time 32853784859 ps
CPU time 200.62 seconds
Started Mar 07 01:21:14 PM PST 24
Finished Mar 07 01:24:35 PM PST 24
Peak memory 198340 kb
Host smart-193c6ce5-2604-4e97-a736-95f2625ea27f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710461437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3710461437
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.3565141541
Short name T717
Test name
Test status
Simulation time 14273013 ps
CPU time 0.6 seconds
Started Mar 07 01:21:13 PM PST 24
Finished Mar 07 01:21:13 PM PST 24
Peak memory 194812 kb
Host smart-a6e762d7-080e-4972-8037-dc0b6e140050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565141541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.3565141541
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2501349190
Short name T185
Test name
Test status
Simulation time 163790663 ps
CPU time 0.83 seconds
Started Mar 07 01:21:13 PM PST 24
Finished Mar 07 01:21:14 PM PST 24
Peak memory 195592 kb
Host smart-d6ed6f31-745e-4b2b-933b-7c10b43d812f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501349190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2501349190
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.359723066
Short name T183
Test name
Test status
Simulation time 458960538 ps
CPU time 23.07 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:21:29 PM PST 24
Peak memory 195668 kb
Host smart-c18c883f-aeea-459e-8dc9-4012e288b12e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359723066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.359723066
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.736559815
Short name T234
Test name
Test status
Simulation time 66958148 ps
CPU time 0.97 seconds
Started Mar 07 01:21:09 PM PST 24
Finished Mar 07 01:21:10 PM PST 24
Peak memory 197984 kb
Host smart-5034088e-5a77-40f7-af16-cdbbe4c19dca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736559815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.736559815
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1170170684
Short name T692
Test name
Test status
Simulation time 287428794 ps
CPU time 1.52 seconds
Started Mar 07 01:21:09 PM PST 24
Finished Mar 07 01:21:11 PM PST 24
Peak memory 197300 kb
Host smart-a0c902f6-8a6c-451f-b863-bcd35fb6c205
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170170684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1170170684
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.1163927351
Short name T383
Test name
Test status
Simulation time 124833287 ps
CPU time 3.35 seconds
Started Mar 07 01:21:12 PM PST 24
Finished Mar 07 01:21:16 PM PST 24
Peak memory 198100 kb
Host smart-017ef91a-2cee-4834-b1f3-3d2b0cb58f34
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163927351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.1163927351
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2152899481
Short name T657
Test name
Test status
Simulation time 144246325 ps
CPU time 3.15 seconds
Started Mar 07 01:21:15 PM PST 24
Finished Mar 07 01:21:18 PM PST 24
Peak memory 198220 kb
Host smart-faf6ec4f-59b9-4b73-8fac-3ee89d24778b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152899481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2152899481
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1660431728
Short name T204
Test name
Test status
Simulation time 257785142 ps
CPU time 1.09 seconds
Started Mar 07 01:21:17 PM PST 24
Finished Mar 07 01:21:18 PM PST 24
Peak memory 196120 kb
Host smart-892854a0-1249-433d-8015-f2cf428eb490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660431728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1660431728
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1172955709
Short name T478
Test name
Test status
Simulation time 40458445 ps
CPU time 1.06 seconds
Started Mar 07 01:21:04 PM PST 24
Finished Mar 07 01:21:05 PM PST 24
Peak memory 196868 kb
Host smart-139d4053-f43c-4174-84f7-69c7e4c62fea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172955709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1172955709
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.197708406
Short name T422
Test name
Test status
Simulation time 106883444 ps
CPU time 2.48 seconds
Started Mar 07 01:21:07 PM PST 24
Finished Mar 07 01:21:10 PM PST 24
Peak memory 197956 kb
Host smart-afa72b5d-0b56-400d-804b-4631f87e9b95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197708406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.197708406
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1704735173
Short name T156
Test name
Test status
Simulation time 107044579 ps
CPU time 0.98 seconds
Started Mar 07 01:21:19 PM PST 24
Finished Mar 07 01:21:20 PM PST 24
Peak memory 195664 kb
Host smart-bf745467-ea6a-4269-b423-a81aa0e7f71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704735173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1704735173
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2440907654
Short name T300
Test name
Test status
Simulation time 31364647 ps
CPU time 1.06 seconds
Started Mar 07 01:21:15 PM PST 24
Finished Mar 07 01:21:16 PM PST 24
Peak memory 195856 kb
Host smart-5686349b-2ba5-4c3b-8f35-4202b338a249
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440907654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2440907654
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.332404657
Short name T4
Test name
Test status
Simulation time 88092959236 ps
CPU time 153.96 seconds
Started Mar 07 01:21:10 PM PST 24
Finished Mar 07 01:23:44 PM PST 24
Peak memory 198328 kb
Host smart-25a35c3c-8b76-481d-8fea-2ab880a7af61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332404657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.g
pio_stress_all.332404657
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.159181052
Short name T436
Test name
Test status
Simulation time 323503562479 ps
CPU time 1577.38 seconds
Started Mar 07 01:21:06 PM PST 24
Finished Mar 07 01:47:23 PM PST 24
Peak memory 198496 kb
Host smart-1ebaa6e5-20e8-4e4d-94df-fcd774c3214e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=159181052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.159181052
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1472396613
Short name T307
Test name
Test status
Simulation time 45566056 ps
CPU time 0.54 seconds
Started Mar 07 01:21:30 PM PST 24
Finished Mar 07 01:21:31 PM PST 24
Peak memory 194132 kb
Host smart-c22b03df-814d-4a78-a5ae-f48014916dd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472396613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1472396613
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3725633042
Short name T589
Test name
Test status
Simulation time 84946514 ps
CPU time 0.72 seconds
Started Mar 07 01:21:13 PM PST 24
Finished Mar 07 01:21:14 PM PST 24
Peak memory 194152 kb
Host smart-8c36577c-e0cb-4eec-a178-fdc24f1dc45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725633042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3725633042
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.854293869
Short name T361
Test name
Test status
Simulation time 449818202 ps
CPU time 11.52 seconds
Started Mar 07 01:21:13 PM PST 24
Finished Mar 07 01:21:24 PM PST 24
Peak memory 195764 kb
Host smart-04d32430-12a7-4ba4-a661-277bbff0533f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854293869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stres
s.854293869
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3149220918
Short name T587
Test name
Test status
Simulation time 65424113 ps
CPU time 1.03 seconds
Started Mar 07 01:21:12 PM PST 24
Finished Mar 07 01:21:14 PM PST 24
Peak memory 196748 kb
Host smart-ade12e9f-75a6-46ff-ad4b-26568e39388c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149220918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3149220918
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.807003980
Short name T209
Test name
Test status
Simulation time 89968812 ps
CPU time 1.57 seconds
Started Mar 07 01:21:20 PM PST 24
Finished Mar 07 01:21:22 PM PST 24
Peak memory 198108 kb
Host smart-ad47b549-1f7e-463a-9392-eda75de22054
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807003980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.807003980
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.4074415387
Short name T231
Test name
Test status
Simulation time 238620172 ps
CPU time 2.14 seconds
Started Mar 07 01:21:19 PM PST 24
Finished Mar 07 01:21:21 PM PST 24
Peak memory 198184 kb
Host smart-021fc944-6310-4dd4-9a58-d245ede62cea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074415387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.4074415387
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3052557453
Short name T217
Test name
Test status
Simulation time 240223396 ps
CPU time 2.44 seconds
Started Mar 07 01:21:05 PM PST 24
Finished Mar 07 01:21:07 PM PST 24
Peak memory 197324 kb
Host smart-0bf98bb5-8cdb-4e7a-ad13-52fa8346101d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052557453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3052557453
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2590221271
Short name T407
Test name
Test status
Simulation time 44300724 ps
CPU time 1.08 seconds
Started Mar 07 01:21:11 PM PST 24
Finished Mar 07 01:21:12 PM PST 24
Peak memory 196916 kb
Host smart-50894c6b-30ac-45bb-9843-0f6ce60c6d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590221271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2590221271
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3732895007
Short name T321
Test name
Test status
Simulation time 129835653 ps
CPU time 1.25 seconds
Started Mar 07 01:21:15 PM PST 24
Finished Mar 07 01:21:16 PM PST 24
Peak memory 197276 kb
Host smart-4f6a94dc-1bd0-4825-975c-135d77b1a974
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732895007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3732895007
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2497853582
Short name T162
Test name
Test status
Simulation time 626255073 ps
CPU time 4.62 seconds
Started Mar 07 01:21:13 PM PST 24
Finished Mar 07 01:21:18 PM PST 24
Peak memory 198116 kb
Host smart-f10227c7-3172-4ff0-9ace-4d27ef822794
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497853582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2497853582
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.4199850489
Short name T28
Test name
Test status
Simulation time 237541666 ps
CPU time 1.07 seconds
Started Mar 07 01:21:12 PM PST 24
Finished Mar 07 01:21:13 PM PST 24
Peak memory 196748 kb
Host smart-82834962-892b-42c0-b3dd-7e1132610805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199850489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.4199850489
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.992623713
Short name T592
Test name
Test status
Simulation time 133950049 ps
CPU time 0.99 seconds
Started Mar 07 01:21:09 PM PST 24
Finished Mar 07 01:21:11 PM PST 24
Peak memory 195884 kb
Host smart-cd9e5de4-acc6-4594-b5df-b9cab5881d49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992623713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.992623713
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1786808280
Short name T540
Test name
Test status
Simulation time 13932592875 ps
CPU time 49 seconds
Started Mar 07 01:21:09 PM PST 24
Finished Mar 07 01:21:58 PM PST 24
Peak memory 198264 kb
Host smart-f104e562-dd28-487c-931f-f8def0e676c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786808280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1786808280
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.562869279
Short name T676
Test name
Test status
Simulation time 73593171226 ps
CPU time 531.43 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:30:09 PM PST 24
Peak memory 198516 kb
Host smart-b2a82cf5-d63b-4dda-baae-6020a8766eca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=562869279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.562869279
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.2804736421
Short name T132
Test name
Test status
Simulation time 11526912 ps
CPU time 0.52 seconds
Started Mar 07 01:21:13 PM PST 24
Finished Mar 07 01:21:14 PM PST 24
Peak memory 192864 kb
Host smart-33bb4c28-cdad-466c-bc98-53081a8e2e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804736421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.2804736421
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1297800429
Short name T66
Test name
Test status
Simulation time 64390823 ps
CPU time 0.68 seconds
Started Mar 07 01:21:19 PM PST 24
Finished Mar 07 01:21:20 PM PST 24
Peak memory 194276 kb
Host smart-3d2710f9-5ced-4c34-98be-f1ec532f16ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297800429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1297800429
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.2521459811
Short name T629
Test name
Test status
Simulation time 2655412247 ps
CPU time 23.95 seconds
Started Mar 07 01:21:07 PM PST 24
Finished Mar 07 01:21:31 PM PST 24
Peak memory 197180 kb
Host smart-6b44e3b7-4575-41eb-8748-9279bbf44665
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521459811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.2521459811
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.3734163099
Short name T239
Test name
Test status
Simulation time 142262967 ps
CPU time 0.69 seconds
Started Mar 07 01:21:09 PM PST 24
Finished Mar 07 01:21:10 PM PST 24
Peak memory 194840 kb
Host smart-c799b244-45ac-49b0-9085-75d229e05eac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734163099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.3734163099
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.1446302825
Short name T468
Test name
Test status
Simulation time 223636444 ps
CPU time 1.06 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 195888 kb
Host smart-fd177007-8c7d-4da4-8285-9ff120610d30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446302825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.1446302825
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.393454767
Short name T219
Test name
Test status
Simulation time 69680784 ps
CPU time 1.62 seconds
Started Mar 07 01:21:20 PM PST 24
Finished Mar 07 01:21:22 PM PST 24
Peak memory 196544 kb
Host smart-d5b785f1-9522-4891-bba5-3719b1f7948c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393454767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.393454767
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2929779121
Short name T449
Test name
Test status
Simulation time 391975459 ps
CPU time 2.44 seconds
Started Mar 07 01:21:20 PM PST 24
Finished Mar 07 01:21:22 PM PST 24
Peak memory 197248 kb
Host smart-d870e613-90a9-4cad-a36b-302c1d2d8a4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929779121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2929779121
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2543449348
Short name T275
Test name
Test status
Simulation time 138759715 ps
CPU time 0.99 seconds
Started Mar 07 01:21:20 PM PST 24
Finished Mar 07 01:21:21 PM PST 24
Peak memory 195620 kb
Host smart-f98dd504-d214-4c8a-bb65-fae835a3ed56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543449348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2543449348
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.3667173673
Short name T362
Test name
Test status
Simulation time 76505263 ps
CPU time 0.75 seconds
Started Mar 07 01:21:20 PM PST 24
Finished Mar 07 01:21:21 PM PST 24
Peak memory 196148 kb
Host smart-ef8de889-a2aa-48b0-8cd5-16460a68f667
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667173673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.3667173673
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2434354634
Short name T520
Test name
Test status
Simulation time 78782760 ps
CPU time 3.71 seconds
Started Mar 07 01:21:09 PM PST 24
Finished Mar 07 01:21:13 PM PST 24
Peak memory 198128 kb
Host smart-09247ce1-fd7b-40fe-8b1d-0ef0e8907c2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434354634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2434354634
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.223067656
Short name T333
Test name
Test status
Simulation time 660422123 ps
CPU time 1.29 seconds
Started Mar 07 01:21:17 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 196880 kb
Host smart-1711b271-6b8b-4e54-8fc0-ccf3853704fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223067656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.223067656
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.291553936
Short name T56
Test name
Test status
Simulation time 99031843 ps
CPU time 0.8 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 195272 kb
Host smart-fbf31a58-be30-425a-98b4-dfdb239a9f43
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291553936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.291553936
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3751458284
Short name T481
Test name
Test status
Simulation time 37302101050 ps
CPU time 119.35 seconds
Started Mar 07 01:21:20 PM PST 24
Finished Mar 07 01:23:19 PM PST 24
Peak memory 198176 kb
Host smart-ad6a27f3-eb3b-43dd-b0b8-56850a59bccc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751458284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3751458284
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.676908617
Short name T614
Test name
Test status
Simulation time 45064318 ps
CPU time 0.6 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 194164 kb
Host smart-10e9cc70-eac5-40e8-b557-a057c999f543
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676908617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.676908617
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.4251953764
Short name T138
Test name
Test status
Simulation time 82574167 ps
CPU time 0.68 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:18 PM PST 24
Peak memory 195044 kb
Host smart-fd7b3dd3-f280-42f4-afec-12c0bbd3e170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251953764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.4251953764
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.4114583809
Short name T553
Test name
Test status
Simulation time 1122975812 ps
CPU time 17.83 seconds
Started Mar 07 01:21:16 PM PST 24
Finished Mar 07 01:21:34 PM PST 24
Peak memory 196996 kb
Host smart-6fae6a0a-dfe6-4064-bd8f-2f564ae15cb8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114583809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.4114583809
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.874093484
Short name T665
Test name
Test status
Simulation time 69093652 ps
CPU time 1.12 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 198060 kb
Host smart-3949ae83-5c8a-4c08-bab1-446f2f050168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874093484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.874093484
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1079084089
Short name T233
Test name
Test status
Simulation time 47809806 ps
CPU time 1.36 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 197360 kb
Host smart-15c76c54-66b0-4456-bc62-1b95097c4c77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079084089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1079084089
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2930852486
Short name T493
Test name
Test status
Simulation time 59906736 ps
CPU time 2.57 seconds
Started Mar 07 01:21:16 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 198120 kb
Host smart-f6f66923-b0c8-4e63-9b01-29abb86f9cb4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930852486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2930852486
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3659093445
Short name T391
Test name
Test status
Simulation time 142113185 ps
CPU time 3.19 seconds
Started Mar 07 01:21:15 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 197076 kb
Host smart-fdafd1c7-f0d3-4c78-b14b-efa0ca0581d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659093445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3659093445
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1997027060
Short name T144
Test name
Test status
Simulation time 123171456 ps
CPU time 0.7 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:18 PM PST 24
Peak memory 196160 kb
Host smart-6bfda3b8-c67a-4784-9843-cba4bd064896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997027060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1997027060
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2210588481
Short name T480
Test name
Test status
Simulation time 143947372 ps
CPU time 0.7 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:18 PM PST 24
Peak memory 195052 kb
Host smart-aca6a64c-53d4-430b-b50f-562cff4f0fec
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210588481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2210588481
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1392119853
Short name T368
Test name
Test status
Simulation time 1474354425 ps
CPU time 5.7 seconds
Started Mar 07 01:21:13 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 198164 kb
Host smart-6ef251e7-7c68-4995-bcff-5718d0eec543
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392119853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1392119853
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1733441844
Short name T374
Test name
Test status
Simulation time 78787214 ps
CPU time 1.31 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 196324 kb
Host smart-e95404d6-b4cd-423a-83ee-6a6839c4ee0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733441844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1733441844
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2695803431
Short name T487
Test name
Test status
Simulation time 234866854 ps
CPU time 1.11 seconds
Started Mar 07 01:21:13 PM PST 24
Finished Mar 07 01:21:14 PM PST 24
Peak memory 196440 kb
Host smart-744dbee3-98c2-4234-9a6b-2f6ec8c24095
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695803431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2695803431
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1205655007
Short name T492
Test name
Test status
Simulation time 13256306782 ps
CPU time 74.65 seconds
Started Mar 07 01:21:17 PM PST 24
Finished Mar 07 01:22:31 PM PST 24
Peak memory 198344 kb
Host smart-7f958e50-3d81-4798-a7d3-0ccea904de54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205655007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1205655007
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.588293616
Short name T44
Test name
Test status
Simulation time 124898803 ps
CPU time 0.64 seconds
Started Mar 07 01:20:11 PM PST 24
Finished Mar 07 01:20:12 PM PST 24
Peak memory 194064 kb
Host smart-19970d46-8097-48a2-9e58-fa0bb7c06207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588293616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.588293616
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.741719721
Short name T409
Test name
Test status
Simulation time 103772913 ps
CPU time 0.77 seconds
Started Mar 07 01:20:23 PM PST 24
Finished Mar 07 01:20:24 PM PST 24
Peak memory 194316 kb
Host smart-78188856-8de1-401c-b007-862e0e16db58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741719721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.741719721
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3852796517
Short name T199
Test name
Test status
Simulation time 514300137 ps
CPU time 18.36 seconds
Started Mar 07 01:20:12 PM PST 24
Finished Mar 07 01:20:31 PM PST 24
Peak memory 197188 kb
Host smart-a3a6039b-3a30-44b8-9d90-ad4c37df9630
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852796517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3852796517
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1212225183
Short name T114
Test name
Test status
Simulation time 157615300 ps
CPU time 0.79 seconds
Started Mar 07 01:20:12 PM PST 24
Finished Mar 07 01:20:13 PM PST 24
Peak memory 195908 kb
Host smart-e6862dc6-5061-46c0-ada7-409b34c22535
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212225183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1212225183
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.91888815
Short name T459
Test name
Test status
Simulation time 48100213 ps
CPU time 1.06 seconds
Started Mar 07 01:20:09 PM PST 24
Finished Mar 07 01:20:11 PM PST 24
Peak memory 195884 kb
Host smart-92ac2509-e58c-4427-a005-d08e3ec8089f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91888815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.91888815
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.588829929
Short name T170
Test name
Test status
Simulation time 25675041 ps
CPU time 1.1 seconds
Started Mar 07 01:20:17 PM PST 24
Finished Mar 07 01:20:19 PM PST 24
Peak memory 198000 kb
Host smart-58ab1e3d-ced5-4fbe-be7c-bd043dec3fc2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588829929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.588829929
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2409591591
Short name T426
Test name
Test status
Simulation time 133519799 ps
CPU time 0.96 seconds
Started Mar 07 01:20:11 PM PST 24
Finished Mar 07 01:20:12 PM PST 24
Peak memory 195632 kb
Host smart-aef71555-a0a5-48f0-95cd-e66ecaf30771
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409591591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2409591591
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3356406448
Short name T171
Test name
Test status
Simulation time 189014625 ps
CPU time 1.11 seconds
Started Mar 07 01:20:09 PM PST 24
Finished Mar 07 01:20:11 PM PST 24
Peak memory 195992 kb
Host smart-ce7385b6-1327-45be-9609-3b9fb43ea5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356406448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3356406448
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1427076501
Short name T521
Test name
Test status
Simulation time 94833837 ps
CPU time 1.08 seconds
Started Mar 07 01:20:11 PM PST 24
Finished Mar 07 01:20:13 PM PST 24
Peak memory 196040 kb
Host smart-c477e09c-ccf8-4294-8790-e01c7b05c20f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427076501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1427076501
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3877009732
Short name T130
Test name
Test status
Simulation time 97561815 ps
CPU time 3.56 seconds
Started Mar 07 01:20:11 PM PST 24
Finished Mar 07 01:20:15 PM PST 24
Peak memory 198136 kb
Host smart-22055eba-2913-4787-898c-653b1e35e59e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877009732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3877009732
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.1755459278
Short name T52
Test name
Test status
Simulation time 153116628 ps
CPU time 1.03 seconds
Started Mar 07 01:20:16 PM PST 24
Finished Mar 07 01:20:18 PM PST 24
Peak memory 215032 kb
Host smart-c21972f7-513b-4150-a192-b3770d81372f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755459278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.1755459278
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3057830452
Short name T434
Test name
Test status
Simulation time 286145882 ps
CPU time 1.12 seconds
Started Mar 07 01:20:12 PM PST 24
Finished Mar 07 01:20:13 PM PST 24
Peak memory 195852 kb
Host smart-4da091ff-7915-4e60-877d-00bc07b4985e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057830452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3057830452
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3730717426
Short name T201
Test name
Test status
Simulation time 59080670 ps
CPU time 1.01 seconds
Started Mar 07 01:20:23 PM PST 24
Finished Mar 07 01:20:24 PM PST 24
Peak memory 195708 kb
Host smart-9a2f88ae-77f6-492c-8724-1466c44ac910
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730717426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3730717426
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.646532336
Short name T76
Test name
Test status
Simulation time 24877391492 ps
CPU time 170.63 seconds
Started Mar 07 01:20:13 PM PST 24
Finished Mar 07 01:23:04 PM PST 24
Peak memory 198376 kb
Host smart-1d15872e-0270-456a-9d13-4ae29b554b46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646532336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.646532336
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.1181896387
Short name T685
Test name
Test status
Simulation time 105006539782 ps
CPU time 1602.44 seconds
Started Mar 07 01:20:12 PM PST 24
Finished Mar 07 01:46:55 PM PST 24
Peak memory 198460 kb
Host smart-6dd652ae-8712-4287-9476-d8380c0e3b9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1181896387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.1181896387
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1831945737
Short name T561
Test name
Test status
Simulation time 15574359 ps
CPU time 0.57 seconds
Started Mar 07 01:21:16 PM PST 24
Finished Mar 07 01:21:17 PM PST 24
Peak memory 194024 kb
Host smart-7aec2fb6-e6ca-44ff-9709-bcbc2d714165
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831945737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1831945737
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1361445273
Short name T406
Test name
Test status
Simulation time 51023349 ps
CPU time 0.61 seconds
Started Mar 07 01:21:17 PM PST 24
Finished Mar 07 01:21:18 PM PST 24
Peak memory 194600 kb
Host smart-669dcbce-287e-4e0d-a537-4a8895450227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361445273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1361445273
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2745171805
Short name T485
Test name
Test status
Simulation time 490363352 ps
CPU time 24.1 seconds
Started Mar 07 01:21:17 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 197108 kb
Host smart-ab52b05e-2443-443e-be5f-2d223f176499
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745171805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2745171805
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3447960556
Short name T611
Test name
Test status
Simulation time 54253870 ps
CPU time 0.78 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 196000 kb
Host smart-29aa20a1-4f3a-4a8f-a6d7-2ecfc3914949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447960556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3447960556
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.405070619
Short name T290
Test name
Test status
Simulation time 42753084 ps
CPU time 0.68 seconds
Started Mar 07 01:21:15 PM PST 24
Finished Mar 07 01:21:16 PM PST 24
Peak memory 194312 kb
Host smart-235e713e-0c5d-43fe-ae26-1f1fa8223b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405070619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.405070619
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.915521646
Short name T560
Test name
Test status
Simulation time 95634246 ps
CPU time 1.54 seconds
Started Mar 07 01:21:19 PM PST 24
Finished Mar 07 01:21:21 PM PST 24
Peak memory 195924 kb
Host smart-031bd8eb-a633-45b6-afdb-babfb2aa0c94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915521646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger.
915521646
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2646142436
Short name T109
Test name
Test status
Simulation time 20427288 ps
CPU time 0.85 seconds
Started Mar 07 01:21:17 PM PST 24
Finished Mar 07 01:21:18 PM PST 24
Peak memory 196832 kb
Host smart-c9eaafda-e17f-47fb-814b-50998732775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646142436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2646142436
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1474196321
Short name T181
Test name
Test status
Simulation time 65643666 ps
CPU time 0.74 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 195644 kb
Host smart-cfd70db5-5119-40fe-aa16-320e3f24bafb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474196321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1474196321
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2068644243
Short name T184
Test name
Test status
Simulation time 437226243 ps
CPU time 4.66 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:23 PM PST 24
Peak memory 198136 kb
Host smart-8051fa23-8067-4448-9913-938d9fb9771c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068644243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2068644243
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.714846070
Short name T549
Test name
Test status
Simulation time 105349859 ps
CPU time 0.89 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 197040 kb
Host smart-3bc40cad-e933-4907-9e10-4a679f5cd037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714846070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.714846070
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2851044088
Short name T72
Test name
Test status
Simulation time 29942807 ps
CPU time 0.78 seconds
Started Mar 07 01:21:22 PM PST 24
Finished Mar 07 01:21:23 PM PST 24
Peak memory 195960 kb
Host smart-e7316a8b-3b75-4a92-86a4-62383f909486
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851044088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2851044088
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.75507810
Short name T716
Test name
Test status
Simulation time 6950469631 ps
CPU time 172.96 seconds
Started Mar 07 01:21:16 PM PST 24
Finished Mar 07 01:24:10 PM PST 24
Peak memory 198252 kb
Host smart-59c77e80-5894-44cd-9876-4ad6306914c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75507810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gp
io_stress_all.75507810
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1596739139
Short name T389
Test name
Test status
Simulation time 37269817 ps
CPU time 0.56 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 194064 kb
Host smart-a3500173-94eb-4376-b945-68c5e28b741e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596739139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1596739139
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3668345309
Short name T131
Test name
Test status
Simulation time 74992853 ps
CPU time 0.75 seconds
Started Mar 07 01:21:21 PM PST 24
Finished Mar 07 01:21:22 PM PST 24
Peak memory 195264 kb
Host smart-aee5a802-5543-4210-98ce-3b91e55aa8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668345309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3668345309
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3016145537
Short name T408
Test name
Test status
Simulation time 2994610724 ps
CPU time 22.24 seconds
Started Mar 07 01:21:20 PM PST 24
Finished Mar 07 01:21:42 PM PST 24
Peak memory 198268 kb
Host smart-f9c7e8fd-a7a6-46da-8dc6-8589881ef2d7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016145537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3016145537
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3010846048
Short name T189
Test name
Test status
Simulation time 236400765 ps
CPU time 0.88 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 195948 kb
Host smart-12e18c7f-396d-4f07-954b-4d950f92ca13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010846048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3010846048
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.17055372
Short name T360
Test name
Test status
Simulation time 171764080 ps
CPU time 0.78 seconds
Started Mar 07 01:21:19 PM PST 24
Finished Mar 07 01:21:20 PM PST 24
Peak memory 195500 kb
Host smart-796ccacd-dbd4-402c-887f-61509d6295f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17055372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.17055372
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2042773581
Short name T617
Test name
Test status
Simulation time 34331116 ps
CPU time 1 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 196376 kb
Host smart-d544ba1f-dda9-474d-a87c-d9fcf44e52b7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042773581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2042773581
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.468094112
Short name T513
Test name
Test status
Simulation time 534232837 ps
CPU time 1.49 seconds
Started Mar 07 01:21:16 PM PST 24
Finished Mar 07 01:21:18 PM PST 24
Peak memory 196348 kb
Host smart-91f4973b-3b2b-493c-a7a0-0ac32feeb073
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468094112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
468094112
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3284683708
Short name T111
Test name
Test status
Simulation time 117967855 ps
CPU time 0.69 seconds
Started Mar 07 01:21:22 PM PST 24
Finished Mar 07 01:21:23 PM PST 24
Peak memory 195244 kb
Host smart-909b57b8-28b7-425b-a837-22cb2b2c787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284683708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3284683708
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1332591878
Short name T397
Test name
Test status
Simulation time 65540534 ps
CPU time 0.69 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 194296 kb
Host smart-e8a6c7e0-8028-4f40-b123-a824ced49b3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332591878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1332591878
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3949609390
Short name T311
Test name
Test status
Simulation time 86230048 ps
CPU time 3.96 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:22 PM PST 24
Peak memory 198148 kb
Host smart-6ed4604b-780a-4fa8-9f83-44201ea1117a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949609390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3949609390
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.4093485436
Short name T369
Test name
Test status
Simulation time 603013553 ps
CPU time 1.23 seconds
Started Mar 07 01:21:20 PM PST 24
Finished Mar 07 01:21:21 PM PST 24
Peak memory 195700 kb
Host smart-b81899b8-98a4-40da-b86e-b4bd549eb71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093485436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.4093485436
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3261395249
Short name T634
Test name
Test status
Simulation time 78714839 ps
CPU time 1.04 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 195724 kb
Host smart-9f813faa-7f3f-41ed-8d92-a36832a2ab71
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261395249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3261395249
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.2584633702
Short name T154
Test name
Test status
Simulation time 20631503291 ps
CPU time 147.44 seconds
Started Mar 07 01:21:20 PM PST 24
Finished Mar 07 01:23:48 PM PST 24
Peak memory 198296 kb
Host smart-290c1c4e-0e13-48f5-a9b6-f72bbd66725a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584633702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.2584633702
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2158433680
Short name T64
Test name
Test status
Simulation time 46632063394 ps
CPU time 680.57 seconds
Started Mar 07 01:21:19 PM PST 24
Finished Mar 07 01:32:40 PM PST 24
Peak memory 198412 kb
Host smart-ff7beaab-4adb-4e16-9d10-eded3ae563b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2158433680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2158433680
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1773127268
Short name T244
Test name
Test status
Simulation time 11769718 ps
CPU time 0.57 seconds
Started Mar 07 01:21:27 PM PST 24
Finished Mar 07 01:21:28 PM PST 24
Peak memory 194084 kb
Host smart-c7ec5614-04c9-4b9e-b881-da30e6a7b55c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773127268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1773127268
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.873143573
Short name T221
Test name
Test status
Simulation time 522138819 ps
CPU time 0.8 seconds
Started Mar 07 01:21:22 PM PST 24
Finished Mar 07 01:21:22 PM PST 24
Peak memory 195460 kb
Host smart-e29635f8-03c2-4101-9918-00c7a2ef23e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873143573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.873143573
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2880699813
Short name T320
Test name
Test status
Simulation time 1768512230 ps
CPU time 13.72 seconds
Started Mar 07 01:21:29 PM PST 24
Finished Mar 07 01:21:43 PM PST 24
Peak memory 198168 kb
Host smart-312210e0-b6e8-41c1-a73c-78445daf91d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880699813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2880699813
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.993854437
Short name T395
Test name
Test status
Simulation time 80466803 ps
CPU time 1.07 seconds
Started Mar 07 01:21:26 PM PST 24
Finished Mar 07 01:21:28 PM PST 24
Peak memory 196640 kb
Host smart-3a568320-db43-4d16-8eb2-e87bf376da7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993854437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.993854437
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3873580365
Short name T414
Test name
Test status
Simulation time 30651549 ps
CPU time 1.03 seconds
Started Mar 07 01:21:16 PM PST 24
Finished Mar 07 01:21:17 PM PST 24
Peak memory 197036 kb
Host smart-560d4636-22ad-4bd0-a67f-ce7be65d1e43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873580365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3873580365
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3215240642
Short name T532
Test name
Test status
Simulation time 232667554 ps
CPU time 2.29 seconds
Started Mar 07 01:21:16 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 198188 kb
Host smart-5981e6ef-2000-4901-bc18-641d9a1ce6db
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215240642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3215240642
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3654179654
Short name T399
Test name
Test status
Simulation time 157629860 ps
CPU time 3.04 seconds
Started Mar 07 01:21:20 PM PST 24
Finished Mar 07 01:21:23 PM PST 24
Peak memory 198148 kb
Host smart-d2d4f884-920b-4617-b091-ef6122669187
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654179654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3654179654
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2460629138
Short name T498
Test name
Test status
Simulation time 23798923 ps
CPU time 0.7 seconds
Started Mar 07 01:21:20 PM PST 24
Finished Mar 07 01:21:21 PM PST 24
Peak memory 194432 kb
Host smart-b801024b-47ed-4f61-b9e3-ac63d0e34ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460629138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2460629138
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.4241057597
Short name T551
Test name
Test status
Simulation time 37837151 ps
CPU time 1.02 seconds
Started Mar 07 01:21:24 PM PST 24
Finished Mar 07 01:21:25 PM PST 24
Peak memory 195920 kb
Host smart-e16a912b-e7df-468d-a026-7836d029014a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241057597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.4241057597
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3219497843
Short name T709
Test name
Test status
Simulation time 3870273115 ps
CPU time 4.93 seconds
Started Mar 07 01:21:26 PM PST 24
Finished Mar 07 01:21:31 PM PST 24
Peak memory 198276 kb
Host smart-6885455a-2ac1-4662-bb5f-e02a3426fd4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219497843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3219497843
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3973204288
Short name T363
Test name
Test status
Simulation time 219635741 ps
CPU time 1.13 seconds
Started Mar 07 01:21:18 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 195936 kb
Host smart-3273e729-8eef-49ae-a284-67c6c3611184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973204288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3973204288
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.2328760196
Short name T301
Test name
Test status
Simulation time 92421657 ps
CPU time 1.14 seconds
Started Mar 07 01:21:17 PM PST 24
Finished Mar 07 01:21:19 PM PST 24
Peak memory 195932 kb
Host smart-295de77e-cc77-4038-afa4-f5115fdd85a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328760196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.2328760196
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.423207539
Short name T273
Test name
Test status
Simulation time 2329150545 ps
CPU time 65.73 seconds
Started Mar 07 01:21:27 PM PST 24
Finished Mar 07 01:22:34 PM PST 24
Peak memory 198348 kb
Host smart-2da40194-f919-484f-9e7a-510f3378c51e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423207539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.423207539
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.46693799
Short name T210
Test name
Test status
Simulation time 90927903514 ps
CPU time 1152.67 seconds
Started Mar 07 01:21:30 PM PST 24
Finished Mar 07 01:40:45 PM PST 24
Peak memory 198392 kb
Host smart-813231d1-2b68-423f-9b95-1507f9a155ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=46693799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.46693799
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.3979658433
Short name T279
Test name
Test status
Simulation time 76614858 ps
CPU time 0.56 seconds
Started Mar 07 01:21:29 PM PST 24
Finished Mar 07 01:21:31 PM PST 24
Peak memory 194092 kb
Host smart-fe463d0f-8672-416b-8796-7ad10b0a8e21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979658433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.3979658433
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1647245607
Short name T331
Test name
Test status
Simulation time 32521438 ps
CPU time 0.83 seconds
Started Mar 07 01:21:34 PM PST 24
Finished Mar 07 01:21:35 PM PST 24
Peak memory 196048 kb
Host smart-5270bd0a-1a63-4010-adee-08c6827f2be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647245607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1647245607
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1631344627
Short name T243
Test name
Test status
Simulation time 877020308 ps
CPU time 25.21 seconds
Started Mar 07 01:21:28 PM PST 24
Finished Mar 07 01:21:55 PM PST 24
Peak memory 196900 kb
Host smart-4adb152c-7064-499d-a478-4fe095afe637
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631344627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1631344627
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.2393991881
Short name T588
Test name
Test status
Simulation time 148345804 ps
CPU time 0.73 seconds
Started Mar 07 01:21:27 PM PST 24
Finished Mar 07 01:21:28 PM PST 24
Peak memory 195936 kb
Host smart-8056a534-f01a-405e-9bdd-1d6c51aa8f59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393991881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.2393991881
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1261430825
Short name T112
Test name
Test status
Simulation time 44352320 ps
CPU time 1.18 seconds
Started Mar 07 01:21:30 PM PST 24
Finished Mar 07 01:21:33 PM PST 24
Peak memory 196008 kb
Host smart-5ac820da-2b35-4bda-887e-4574b17b8ee0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261430825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1261430825
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1425830036
Short name T358
Test name
Test status
Simulation time 47942059 ps
CPU time 2.07 seconds
Started Mar 07 01:21:28 PM PST 24
Finished Mar 07 01:21:31 PM PST 24
Peak memory 198240 kb
Host smart-0d2453f5-4bb5-473c-bb6f-d1dd8bb468ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425830036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1425830036
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3410533091
Short name T661
Test name
Test status
Simulation time 252126439 ps
CPU time 3.63 seconds
Started Mar 07 01:21:31 PM PST 24
Finished Mar 07 01:21:36 PM PST 24
Peak memory 198220 kb
Host smart-bbd4c69d-0bd9-4cb8-9881-8b90980f148a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410533091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3410533091
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3394367759
Short name T682
Test name
Test status
Simulation time 48738553 ps
CPU time 1.1 seconds
Started Mar 07 01:21:26 PM PST 24
Finished Mar 07 01:21:28 PM PST 24
Peak memory 196176 kb
Host smart-7fee1ccc-dd4b-4348-8d24-3edabf647919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394367759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3394367759
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2009970652
Short name T690
Test name
Test status
Simulation time 28176434 ps
CPU time 1.16 seconds
Started Mar 07 01:21:34 PM PST 24
Finished Mar 07 01:21:35 PM PST 24
Peak memory 196136 kb
Host smart-642b4ee7-4018-436c-9e9b-bc37253619e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009970652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2009970652
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2033907139
Short name T504
Test name
Test status
Simulation time 413374557 ps
CPU time 4.98 seconds
Started Mar 07 01:21:27 PM PST 24
Finished Mar 07 01:21:34 PM PST 24
Peak memory 198128 kb
Host smart-8f91e4c0-3af5-461d-b5ec-db405072eebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033907139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2033907139
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3001352011
Short name T564
Test name
Test status
Simulation time 301854864 ps
CPU time 1.01 seconds
Started Mar 07 01:21:30 PM PST 24
Finished Mar 07 01:21:33 PM PST 24
Peak memory 195924 kb
Host smart-8a9f0915-d19a-40c1-867e-19b616fd114e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001352011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3001352011
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3610319460
Short name T536
Test name
Test status
Simulation time 150687379 ps
CPU time 1.35 seconds
Started Mar 07 01:21:28 PM PST 24
Finished Mar 07 01:21:30 PM PST 24
Peak memory 196820 kb
Host smart-8a39ad6e-1a8c-4a9c-b275-8d79cb336dc6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610319460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3610319460
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.2094430459
Short name T238
Test name
Test status
Simulation time 97949151609 ps
CPU time 139.59 seconds
Started Mar 07 01:21:31 PM PST 24
Finished Mar 07 01:23:52 PM PST 24
Peak memory 198388 kb
Host smart-cc3c6abe-9a93-41e2-ab93-25c9fa4041f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094430459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.2094430459
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.2106601976
Short name T416
Test name
Test status
Simulation time 47529262645 ps
CPU time 1218.66 seconds
Started Mar 07 01:21:32 PM PST 24
Finished Mar 07 01:41:51 PM PST 24
Peak memory 198472 kb
Host smart-64462611-3d1a-4eac-9778-1c2478b73f38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2106601976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.2106601976
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1506219269
Short name T667
Test name
Test status
Simulation time 22470653 ps
CPU time 0.6 seconds
Started Mar 07 01:21:33 PM PST 24
Finished Mar 07 01:21:34 PM PST 24
Peak memory 194776 kb
Host smart-4ab381aa-caa5-4f64-aa63-2b52426dc885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506219269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1506219269
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.615155050
Short name T359
Test name
Test status
Simulation time 18441932 ps
CPU time 0.76 seconds
Started Mar 07 01:21:34 PM PST 24
Finished Mar 07 01:21:35 PM PST 24
Peak memory 194252 kb
Host smart-b7fad23a-ab26-477a-b81c-cf5562848c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615155050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.615155050
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.2781599529
Short name T528
Test name
Test status
Simulation time 2266203575 ps
CPU time 23.17 seconds
Started Mar 07 01:21:32 PM PST 24
Finished Mar 07 01:21:56 PM PST 24
Peak memory 195824 kb
Host smart-22a93d81-90f3-45aa-b5dd-73c346d286b5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781599529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.2781599529
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3666427619
Short name T248
Test name
Test status
Simulation time 83440489 ps
CPU time 0.84 seconds
Started Mar 07 01:21:34 PM PST 24
Finished Mar 07 01:21:35 PM PST 24
Peak memory 196044 kb
Host smart-c9bae476-f4c3-417c-a207-e5d3ecd4a823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666427619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3666427619
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3746123046
Short name T428
Test name
Test status
Simulation time 174586563 ps
CPU time 1.56 seconds
Started Mar 07 01:21:29 PM PST 24
Finished Mar 07 01:21:32 PM PST 24
Peak memory 198248 kb
Host smart-aa3c58c3-dc10-48f1-a938-98c498f4d5cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746123046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3746123046
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2212414975
Short name T310
Test name
Test status
Simulation time 129212403 ps
CPU time 2.59 seconds
Started Mar 07 01:21:32 PM PST 24
Finished Mar 07 01:21:35 PM PST 24
Peak memory 196392 kb
Host smart-7b15a274-328a-4abe-af2c-b9163efe3a51
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212414975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2212414975
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1510428069
Short name T517
Test name
Test status
Simulation time 176593379 ps
CPU time 3.44 seconds
Started Mar 07 01:21:34 PM PST 24
Finished Mar 07 01:21:38 PM PST 24
Peak memory 197088 kb
Host smart-64d4290a-8150-4a0b-8091-28b2f6f6c0ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510428069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1510428069
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.589621602
Short name T559
Test name
Test status
Simulation time 33300850 ps
CPU time 0.79 seconds
Started Mar 07 01:21:30 PM PST 24
Finished Mar 07 01:21:31 PM PST 24
Peak memory 195596 kb
Host smart-1fa0b711-5c01-46b4-b3cf-c78e7a5e1473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589621602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.589621602
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1896569181
Short name T502
Test name
Test status
Simulation time 232576112 ps
CPU time 1.25 seconds
Started Mar 07 01:21:29 PM PST 24
Finished Mar 07 01:21:31 PM PST 24
Peak memory 197164 kb
Host smart-25c8bbe5-0171-4486-ae84-75093045ebb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896569181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1896569181
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3076627938
Short name T529
Test name
Test status
Simulation time 30313837 ps
CPU time 1.27 seconds
Started Mar 07 01:21:32 PM PST 24
Finished Mar 07 01:21:34 PM PST 24
Peak memory 198148 kb
Host smart-662822b9-97b0-497b-b979-5c25cab39427
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076627938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3076627938
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.2343727739
Short name T649
Test name
Test status
Simulation time 167665657 ps
CPU time 0.87 seconds
Started Mar 07 01:21:27 PM PST 24
Finished Mar 07 01:21:29 PM PST 24
Peak memory 195384 kb
Host smart-0690480e-84aa-441b-8ae4-216d2865e404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343727739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.2343727739
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3301349892
Short name T280
Test name
Test status
Simulation time 51522064 ps
CPU time 1.04 seconds
Started Mar 07 01:21:30 PM PST 24
Finished Mar 07 01:21:33 PM PST 24
Peak memory 195808 kb
Host smart-4b26d445-f660-41b3-a82b-826ace32fcd2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301349892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3301349892
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1221525694
Short name T378
Test name
Test status
Simulation time 25882519947 ps
CPU time 186.78 seconds
Started Mar 07 01:21:31 PM PST 24
Finished Mar 07 01:24:39 PM PST 24
Peak memory 198356 kb
Host smart-931c8e29-c817-4986-905d-c789acf71216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221525694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1221525694
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1576018717
Short name T446
Test name
Test status
Simulation time 41772578572 ps
CPU time 1303.81 seconds
Started Mar 07 01:21:33 PM PST 24
Finished Mar 07 01:43:17 PM PST 24
Peak memory 198388 kb
Host smart-9fc98b39-3dc0-4869-a2d4-a25df1b045fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1576018717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1576018717
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.605552935
Short name T671
Test name
Test status
Simulation time 18491772 ps
CPU time 0.57 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 194956 kb
Host smart-348c6e0f-788a-4f00-b718-b660efced9ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605552935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.605552935
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.3334237312
Short name T282
Test name
Test status
Simulation time 33394102 ps
CPU time 0.7 seconds
Started Mar 07 01:21:33 PM PST 24
Finished Mar 07 01:21:34 PM PST 24
Peak memory 194812 kb
Host smart-7b5c57ad-1842-4fcf-9bae-9bcc154389e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334237312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.3334237312
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2638931001
Short name T355
Test name
Test status
Simulation time 717026386 ps
CPU time 21.57 seconds
Started Mar 07 01:21:35 PM PST 24
Finished Mar 07 01:21:57 PM PST 24
Peak memory 197240 kb
Host smart-9a7ddb81-4545-4d55-902c-10d13fbbd9ac
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638931001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2638931001
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3047255116
Short name T522
Test name
Test status
Simulation time 155964848 ps
CPU time 0.72 seconds
Started Mar 07 01:21:32 PM PST 24
Finished Mar 07 01:21:33 PM PST 24
Peak memory 195964 kb
Host smart-af33fa3c-c68f-42ec-9066-a171b611ea9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047255116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3047255116
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3011244559
Short name T437
Test name
Test status
Simulation time 199590750 ps
CPU time 1.16 seconds
Started Mar 07 01:21:32 PM PST 24
Finished Mar 07 01:21:33 PM PST 24
Peak memory 197008 kb
Host smart-9b9d0d9b-139e-4f74-815c-858026165201
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011244559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3011244559
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3254348679
Short name T283
Test name
Test status
Simulation time 327747680 ps
CPU time 3.41 seconds
Started Mar 07 01:21:32 PM PST 24
Finished Mar 07 01:21:35 PM PST 24
Peak memory 198140 kb
Host smart-b59c210d-d76f-47cb-9ba8-2654366b3fa5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254348679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3254348679
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3076554200
Short name T317
Test name
Test status
Simulation time 186461126 ps
CPU time 3.32 seconds
Started Mar 07 01:21:32 PM PST 24
Finished Mar 07 01:21:35 PM PST 24
Peak memory 196856 kb
Host smart-cfe0382e-6f0e-479d-9a58-62f69b7ddbd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076554200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3076554200
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2595457606
Short name T447
Test name
Test status
Simulation time 57640089 ps
CPU time 1.22 seconds
Started Mar 07 01:21:33 PM PST 24
Finished Mar 07 01:21:34 PM PST 24
Peak memory 197400 kb
Host smart-c2071a92-1bba-49ce-8ca1-b0bcaa1acb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595457606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2595457606
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3523821832
Short name T68
Test name
Test status
Simulation time 23707863 ps
CPU time 0.9 seconds
Started Mar 07 01:21:32 PM PST 24
Finished Mar 07 01:21:33 PM PST 24
Peak memory 196656 kb
Host smart-f169a2b5-16b2-47fb-9237-5b3091287392
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523821832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3523821832
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3754487663
Short name T636
Test name
Test status
Simulation time 1765464877 ps
CPU time 5.41 seconds
Started Mar 07 01:21:33 PM PST 24
Finished Mar 07 01:21:39 PM PST 24
Peak memory 197948 kb
Host smart-fd96736a-9f15-4696-a0bd-0f0eb11c29d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754487663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3754487663
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3326920266
Short name T572
Test name
Test status
Simulation time 179758810 ps
CPU time 0.97 seconds
Started Mar 07 01:21:31 PM PST 24
Finished Mar 07 01:21:33 PM PST 24
Peak memory 196664 kb
Host smart-8e56c78f-8581-41da-a252-ce809afdf119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326920266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3326920266
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3011347024
Short name T285
Test name
Test status
Simulation time 46049918 ps
CPU time 1.1 seconds
Started Mar 07 01:21:33 PM PST 24
Finished Mar 07 01:21:34 PM PST 24
Peak memory 195916 kb
Host smart-fb9c800a-c068-4e71-9eed-0e1a741d0b98
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011347024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3011347024
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.3700517751
Short name T32
Test name
Test status
Simulation time 13506105909 ps
CPU time 46.69 seconds
Started Mar 07 01:21:34 PM PST 24
Finished Mar 07 01:22:22 PM PST 24
Peak memory 198268 kb
Host smart-dc7cdfdc-158a-43eb-a9b5-47a5522ac494
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700517751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.3700517751
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4243162256
Short name T581
Test name
Test status
Simulation time 16335763 ps
CPU time 0.57 seconds
Started Mar 07 01:21:41 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 194192 kb
Host smart-8b74dec1-4ebf-42fd-a983-5f8f4c21e378
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243162256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4243162256
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.2603770262
Short name T136
Test name
Test status
Simulation time 120270579 ps
CPU time 0.8 seconds
Started Mar 07 01:21:42 PM PST 24
Finished Mar 07 01:21:43 PM PST 24
Peak memory 195260 kb
Host smart-b3bd59da-c5d3-4924-8189-64261df3e4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603770262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.2603770262
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.789134677
Short name T453
Test name
Test status
Simulation time 2907630051 ps
CPU time 25.63 seconds
Started Mar 07 01:21:41 PM PST 24
Finished Mar 07 01:22:07 PM PST 24
Peak memory 197224 kb
Host smart-e7a44be6-98e0-4c1c-95b5-237581e86d00
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789134677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.789134677
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1374495100
Short name T75
Test name
Test status
Simulation time 28583703 ps
CPU time 0.67 seconds
Started Mar 07 01:21:37 PM PST 24
Finished Mar 07 01:21:38 PM PST 24
Peak memory 194776 kb
Host smart-f44358ce-a8fe-468a-b495-d4f3cd19f51f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374495100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1374495100
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2074201779
Short name T303
Test name
Test status
Simulation time 49140408 ps
CPU time 1.51 seconds
Started Mar 07 01:21:36 PM PST 24
Finished Mar 07 01:21:37 PM PST 24
Peak memory 197152 kb
Host smart-d2e81f53-1e8a-43a1-a18a-58e9a29ca8f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074201779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2074201779
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2481021493
Short name T641
Test name
Test status
Simulation time 248980826 ps
CPU time 2.81 seconds
Started Mar 07 01:21:37 PM PST 24
Finished Mar 07 01:21:40 PM PST 24
Peak memory 198172 kb
Host smart-a15253fa-1487-4321-a36b-068b039c44c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481021493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2481021493
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.4000892007
Short name T420
Test name
Test status
Simulation time 43156330 ps
CPU time 1.13 seconds
Started Mar 07 01:21:36 PM PST 24
Finished Mar 07 01:21:37 PM PST 24
Peak memory 196440 kb
Host smart-0f001e54-30c7-45da-8b7f-4314611e71c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000892007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.4000892007
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1437605424
Short name T384
Test name
Test status
Simulation time 274560589 ps
CPU time 1.24 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:21:42 PM PST 24
Peak memory 197164 kb
Host smart-05c20af2-7b68-4487-bca6-1baad1f25151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437605424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1437605424
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.764714437
Short name T115
Test name
Test status
Simulation time 42874394 ps
CPU time 0.94 seconds
Started Mar 07 01:21:38 PM PST 24
Finished Mar 07 01:21:39 PM PST 24
Peak memory 196064 kb
Host smart-fa4ece6f-bac1-4ad4-b9ef-b95b8d70ec32
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764714437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullup
_pulldown.764714437
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3810212917
Short name T466
Test name
Test status
Simulation time 509539030 ps
CPU time 6.27 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:21:47 PM PST 24
Peak memory 198140 kb
Host smart-73c983e2-25e8-40c2-a4b2-9f6298e12b7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810212917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3810212917
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1667844734
Short name T135
Test name
Test status
Simulation time 258536260 ps
CPU time 1.54 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:21:42 PM PST 24
Peak memory 196972 kb
Host smart-14a65426-2678-4387-b7d2-6e7f830da6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667844734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1667844734
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1200360586
Short name T400
Test name
Test status
Simulation time 382518758 ps
CPU time 0.88 seconds
Started Mar 07 01:21:39 PM PST 24
Finished Mar 07 01:21:40 PM PST 24
Peak memory 196176 kb
Host smart-4c77ae83-2ed3-41c5-b7d0-e5af7c7a1896
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200360586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1200360586
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.155487551
Short name T488
Test name
Test status
Simulation time 7092601764 ps
CPU time 204.61 seconds
Started Mar 07 01:21:38 PM PST 24
Finished Mar 07 01:25:03 PM PST 24
Peak memory 198352 kb
Host smart-dc6dd556-dacb-47e2-9a5d-8b470d5c514a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155487551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.155487551
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2466853831
Short name T35
Test name
Test status
Simulation time 103791152667 ps
CPU time 1966.45 seconds
Started Mar 07 01:21:38 PM PST 24
Finished Mar 07 01:54:25 PM PST 24
Peak memory 198496 kb
Host smart-ff57e4da-d0e2-4d48-8383-6a86fd161dfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2466853831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2466853831
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2607471691
Short name T484
Test name
Test status
Simulation time 75320383 ps
CPU time 0.59 seconds
Started Mar 07 01:21:43 PM PST 24
Finished Mar 07 01:21:44 PM PST 24
Peak memory 194120 kb
Host smart-a5457f1a-ebaa-433c-bff0-8010a96a24ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607471691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2607471691
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.419272393
Short name T470
Test name
Test status
Simulation time 154314374 ps
CPU time 0.79 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 195308 kb
Host smart-cbe58cf1-5c6c-4db8-b60a-42b5e7f87845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419272393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.419272393
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3653951092
Short name T23
Test name
Test status
Simulation time 70270850 ps
CPU time 3.41 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:21:44 PM PST 24
Peak memory 196392 kb
Host smart-206b6f18-3694-4f8b-852a-3a5e025353aa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653951092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3653951092
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1092806662
Short name T296
Test name
Test status
Simulation time 345877233 ps
CPU time 0.94 seconds
Started Mar 07 01:21:42 PM PST 24
Finished Mar 07 01:21:44 PM PST 24
Peak memory 196144 kb
Host smart-fdd02d6a-e796-46c1-8fc1-8ab2c292d2bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092806662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1092806662
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2899095062
Short name T457
Test name
Test status
Simulation time 578676516 ps
CPU time 1.08 seconds
Started Mar 07 01:21:38 PM PST 24
Finished Mar 07 01:21:39 PM PST 24
Peak memory 196824 kb
Host smart-324e81ce-f504-4d2e-9660-4d55215d6a21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899095062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2899095062
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.3014379109
Short name T642
Test name
Test status
Simulation time 65165845 ps
CPU time 2.62 seconds
Started Mar 07 01:21:38 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 196628 kb
Host smart-f273b516-70ce-42eb-bb5c-d60a8c20fdd8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014379109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.3014379109
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3773743013
Short name T533
Test name
Test status
Simulation time 153018011 ps
CPU time 1.38 seconds
Started Mar 07 01:21:39 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 196232 kb
Host smart-556a3ed0-71a2-49c2-a50a-b5deea5cfcf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773743013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3773743013
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.477254485
Short name T601
Test name
Test status
Simulation time 219913092 ps
CPU time 1.08 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 196172 kb
Host smart-50833b97-48f2-487d-8498-5406a5791f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477254485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.477254485
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3054318277
Short name T602
Test name
Test status
Simulation time 172479308 ps
CPU time 0.87 seconds
Started Mar 07 01:21:38 PM PST 24
Finished Mar 07 01:21:39 PM PST 24
Peak memory 196824 kb
Host smart-00d0071a-59d1-477e-b1cf-e8c9c87b4301
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054318277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3054318277
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1474478280
Short name T656
Test name
Test status
Simulation time 424145876 ps
CPU time 4.81 seconds
Started Mar 07 01:21:41 PM PST 24
Finished Mar 07 01:21:46 PM PST 24
Peak memory 198028 kb
Host smart-0302256b-b667-472b-9f19-6c9270e8d6c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474478280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1474478280
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2082443782
Short name T377
Test name
Test status
Simulation time 92550593 ps
CPU time 0.79 seconds
Started Mar 07 01:21:37 PM PST 24
Finished Mar 07 01:21:38 PM PST 24
Peak memory 195480 kb
Host smart-b8ec5c84-cd58-4015-95fb-42e7e6241883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082443782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2082443782
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.2227162923
Short name T295
Test name
Test status
Simulation time 55255496 ps
CPU time 1.4 seconds
Started Mar 07 01:21:42 PM PST 24
Finished Mar 07 01:21:43 PM PST 24
Peak memory 196872 kb
Host smart-044ab50e-f9c5-4e81-8e19-b4a1ed311174
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227162923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.2227162923
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.493764528
Short name T442
Test name
Test status
Simulation time 42882039706 ps
CPU time 137.07 seconds
Started Mar 07 01:21:39 PM PST 24
Finished Mar 07 01:23:57 PM PST 24
Peak memory 198300 kb
Host smart-816d8322-5148-4bf5-8c86-b42a6d27ae97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493764528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.493764528
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.2287288748
Short name T59
Test name
Test status
Simulation time 509813407801 ps
CPU time 2458.81 seconds
Started Mar 07 01:21:39 PM PST 24
Finished Mar 07 02:02:39 PM PST 24
Peak memory 198464 kb
Host smart-8ba8d4a0-15a6-482b-923c-70b26db85b44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2287288748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.2287288748
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.510859286
Short name T306
Test name
Test status
Simulation time 21830910 ps
CPU time 0.58 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 193972 kb
Host smart-e14e8375-5a69-43a7-b4b0-80d2463c3e6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510859286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.510859286
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1176723552
Short name T647
Test name
Test status
Simulation time 59171949 ps
CPU time 0.87 seconds
Started Mar 07 01:21:38 PM PST 24
Finished Mar 07 01:21:39 PM PST 24
Peak memory 196592 kb
Host smart-aa4606a6-f7b4-454a-b3d0-0990c3ff57c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176723552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1176723552
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3469677021
Short name T677
Test name
Test status
Simulation time 782908238 ps
CPU time 7.52 seconds
Started Mar 07 01:21:41 PM PST 24
Finished Mar 07 01:21:48 PM PST 24
Peak memory 197256 kb
Host smart-956a9a41-4d02-4d44-a10d-13f5694c1f51
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469677021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3469677021
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.611522351
Short name T192
Test name
Test status
Simulation time 251485314 ps
CPU time 1.15 seconds
Started Mar 07 01:21:39 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 198052 kb
Host smart-1978ccf5-97e7-40d6-9752-1e85be7c87c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611522351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.611522351
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.4287235650
Short name T67
Test name
Test status
Simulation time 141346018 ps
CPU time 0.74 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 195376 kb
Host smart-cab5588a-025a-40ca-a7c3-6382c13589c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287235650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.4287235650
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.239902834
Short name T151
Test name
Test status
Simulation time 63473870 ps
CPU time 2.61 seconds
Started Mar 07 01:21:42 PM PST 24
Finished Mar 07 01:21:45 PM PST 24
Peak memory 197076 kb
Host smart-a284dc35-0092-443a-a770-2cdd0a8845f1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239902834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.239902834
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.4175636616
Short name T613
Test name
Test status
Simulation time 99904982 ps
CPU time 1.68 seconds
Started Mar 07 01:21:38 PM PST 24
Finished Mar 07 01:21:40 PM PST 24
Peak memory 196100 kb
Host smart-b7f28003-8aa3-4d66-b79f-a5a2dd1fc744
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175636616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.4175636616
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.3636327325
Short name T324
Test name
Test status
Simulation time 104752601 ps
CPU time 1.1 seconds
Started Mar 07 01:21:37 PM PST 24
Finished Mar 07 01:21:38 PM PST 24
Peak memory 196928 kb
Host smart-7c5234f1-3eeb-4c07-b497-3fd712520c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636327325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.3636327325
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.228137994
Short name T590
Test name
Test status
Simulation time 58434232 ps
CPU time 1.11 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 195876 kb
Host smart-b93a15ae-88ba-4c31-bcef-574de58f5f31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228137994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.228137994
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2550543365
Short name T261
Test name
Test status
Simulation time 425319450 ps
CPU time 5.04 seconds
Started Mar 07 01:21:41 PM PST 24
Finished Mar 07 01:21:47 PM PST 24
Peak memory 198060 kb
Host smart-09d101cf-7a0b-4de0-8f11-2226328339b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550543365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2550543365
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.4153541001
Short name T456
Test name
Test status
Simulation time 87821250 ps
CPU time 1.32 seconds
Started Mar 07 01:21:37 PM PST 24
Finished Mar 07 01:21:39 PM PST 24
Peak memory 196700 kb
Host smart-a7566f8d-da55-45ac-bed1-0aa4b4e123f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153541001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.4153541001
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1428867632
Short name T417
Test name
Test status
Simulation time 63675070 ps
CPU time 0.85 seconds
Started Mar 07 01:21:42 PM PST 24
Finished Mar 07 01:21:44 PM PST 24
Peak memory 195956 kb
Host smart-f97a9051-ffe7-46b2-9981-e56d6b3b170f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428867632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1428867632
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1135461797
Short name T668
Test name
Test status
Simulation time 24533704340 ps
CPU time 161.76 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:24:22 PM PST 24
Peak memory 198248 kb
Host smart-ba8b3166-add8-450d-9a83-0244042cbc4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135461797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1135461797
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_alert_test.2659989963
Short name T194
Test name
Test status
Simulation time 21537423 ps
CPU time 0.56 seconds
Started Mar 07 01:21:55 PM PST 24
Finished Mar 07 01:21:56 PM PST 24
Peak memory 194780 kb
Host smart-bea35f99-abe4-4f29-8c2d-2a5039e2d7c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659989963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.2659989963
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2349928034
Short name T357
Test name
Test status
Simulation time 84711293 ps
CPU time 0.78 seconds
Started Mar 07 01:21:48 PM PST 24
Finished Mar 07 01:21:49 PM PST 24
Peak memory 195468 kb
Host smart-30b4ee67-9994-4e00-859c-ec45bbe5add0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349928034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2349928034
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1575338088
Short name T277
Test name
Test status
Simulation time 545994753 ps
CPU time 19.64 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:22:09 PM PST 24
Peak memory 198088 kb
Host smart-70394df2-cda7-4fba-86e7-947bc318b11b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575338088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1575338088
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2344849850
Short name T687
Test name
Test status
Simulation time 30471355 ps
CPU time 0.71 seconds
Started Mar 07 01:21:52 PM PST 24
Finished Mar 07 01:21:53 PM PST 24
Peak memory 194688 kb
Host smart-90a1dde7-a7ed-483a-a3dd-560373ccc9dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344849850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2344849850
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.2849330279
Short name T672
Test name
Test status
Simulation time 712182542 ps
CPU time 1.39 seconds
Started Mar 07 01:21:48 PM PST 24
Finished Mar 07 01:21:50 PM PST 24
Peak memory 197056 kb
Host smart-d4111509-3ac9-4cca-9059-a872ae6498f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849330279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.2849330279
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.448408753
Short name T526
Test name
Test status
Simulation time 61192508 ps
CPU time 2.27 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:53 PM PST 24
Peak memory 196380 kb
Host smart-a0326edb-fabc-4c41-8b40-fa46ceb26546
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448408753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.448408753
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.3519301272
Short name T619
Test name
Test status
Simulation time 209135153 ps
CPU time 1.4 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:21:51 PM PST 24
Peak memory 196820 kb
Host smart-76f9f5ae-9a7d-41b3-8ac3-a09599e58281
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519301272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.3519301272
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1307344290
Short name T379
Test name
Test status
Simulation time 50053192 ps
CPU time 0.71 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:52 PM PST 24
Peak memory 195204 kb
Host smart-3cc76386-bf20-46d7-a59c-b60c863f7fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307344290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1307344290
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.83845816
Short name T418
Test name
Test status
Simulation time 44850836 ps
CPU time 0.93 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:21:50 PM PST 24
Peak memory 196116 kb
Host smart-f3a04826-17ac-4c27-ad34-1e201ea4ac87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83845816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullup_
pulldown.83845816
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3685128123
Short name T345
Test name
Test status
Simulation time 1124293090 ps
CPU time 4.35 seconds
Started Mar 07 01:21:47 PM PST 24
Finished Mar 07 01:21:52 PM PST 24
Peak memory 198120 kb
Host smart-de536521-f180-475c-af02-c9e3dc0e043f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685128123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3685128123
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.1996578240
Short name T30
Test name
Test status
Simulation time 53641579 ps
CPU time 0.99 seconds
Started Mar 07 01:21:42 PM PST 24
Finished Mar 07 01:21:44 PM PST 24
Peak memory 196568 kb
Host smart-e2b1d861-6f58-457a-bcb2-35ff1891b1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996578240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.1996578240
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.2866956677
Short name T161
Test name
Test status
Simulation time 112794387 ps
CPU time 1.04 seconds
Started Mar 07 01:21:40 PM PST 24
Finished Mar 07 01:21:41 PM PST 24
Peak memory 195820 kb
Host smart-1bb593d4-52f0-491b-b3ea-650bf7edfd24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866956677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.2866956677
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.4119724883
Short name T463
Test name
Test status
Simulation time 6269639501 ps
CPU time 81.8 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:23:11 PM PST 24
Peak memory 198312 kb
Host smart-02cfe0f7-1f0e-4626-94a0-e0bf4b4348e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119724883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.4119724883
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.364375197
Short name T110
Test name
Test status
Simulation time 13021583 ps
CPU time 0.6 seconds
Started Mar 07 01:20:15 PM PST 24
Finished Mar 07 01:20:16 PM PST 24
Peak memory 193560 kb
Host smart-74783a45-8794-4949-8784-1ba3987a46d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364375197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.364375197
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1665942369
Short name T531
Test name
Test status
Simulation time 30582947 ps
CPU time 0.89 seconds
Started Mar 07 01:20:10 PM PST 24
Finished Mar 07 01:20:11 PM PST 24
Peak memory 195728 kb
Host smart-9f9e04fb-de92-4382-9154-4ba043719e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665942369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1665942369
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2084676290
Short name T412
Test name
Test status
Simulation time 1088752745 ps
CPU time 19.92 seconds
Started Mar 07 01:20:14 PM PST 24
Finished Mar 07 01:20:34 PM PST 24
Peak memory 197040 kb
Host smart-8d3ccdf1-e9df-45e8-b9d4-3df23314337f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084676290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2084676290
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2095036643
Short name T197
Test name
Test status
Simulation time 195427731 ps
CPU time 0.91 seconds
Started Mar 07 01:20:11 PM PST 24
Finished Mar 07 01:20:12 PM PST 24
Peak memory 197332 kb
Host smart-83820e24-b24b-4f37-bed9-9bf256696bf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095036643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2095036643
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3704266528
Short name T681
Test name
Test status
Simulation time 33935858 ps
CPU time 0.79 seconds
Started Mar 07 01:20:11 PM PST 24
Finished Mar 07 01:20:12 PM PST 24
Peak memory 196260 kb
Host smart-5feead0a-8e74-4fa9-864f-89efcc3e0363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704266528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3704266528
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.964061487
Short name T21
Test name
Test status
Simulation time 51766791 ps
CPU time 2.19 seconds
Started Mar 07 01:20:11 PM PST 24
Finished Mar 07 01:20:14 PM PST 24
Peak memory 198208 kb
Host smart-6e760d36-e05e-4caa-81c6-df866e006984
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964061487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.964061487
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.4063294540
Short name T313
Test name
Test status
Simulation time 127785099 ps
CPU time 2.5 seconds
Started Mar 07 01:20:11 PM PST 24
Finished Mar 07 01:20:14 PM PST 24
Peak memory 195960 kb
Host smart-93865ae6-557a-4a7a-895a-31dae84d64c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063294540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
4063294540
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1027979921
Short name T702
Test name
Test status
Simulation time 61707535 ps
CPU time 0.85 seconds
Started Mar 07 01:20:14 PM PST 24
Finished Mar 07 01:20:15 PM PST 24
Peak memory 196636 kb
Host smart-136ffe2d-81e5-42f3-890f-538a857b0ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027979921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1027979921
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2181264084
Short name T683
Test name
Test status
Simulation time 352794493 ps
CPU time 0.91 seconds
Started Mar 07 01:20:15 PM PST 24
Finished Mar 07 01:20:17 PM PST 24
Peak memory 196732 kb
Host smart-732e295e-d771-4709-b406-c624fe0dbac0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181264084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2181264084
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2776828568
Short name T208
Test name
Test status
Simulation time 1262580992 ps
CPU time 4.72 seconds
Started Mar 07 01:20:12 PM PST 24
Finished Mar 07 01:20:17 PM PST 24
Peak memory 197992 kb
Host smart-ac1e6183-9c19-4194-897b-5f90f5323eef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776828568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2776828568
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.603159337
Short name T42
Test name
Test status
Simulation time 60272682 ps
CPU time 0.88 seconds
Started Mar 07 01:20:20 PM PST 24
Finished Mar 07 01:20:22 PM PST 24
Peak memory 213744 kb
Host smart-82d9e203-b723-48b6-b727-43012950fc8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603159337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.603159337
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.2373791025
Short name T477
Test name
Test status
Simulation time 71627178 ps
CPU time 1.22 seconds
Started Mar 07 01:20:16 PM PST 24
Finished Mar 07 01:20:18 PM PST 24
Peak memory 195664 kb
Host smart-343b8c1c-6cca-46d7-aaf8-ef55fadadcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373791025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.2373791025
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1604413626
Short name T552
Test name
Test status
Simulation time 148735924 ps
CPU time 1.16 seconds
Started Mar 07 01:20:20 PM PST 24
Finished Mar 07 01:20:22 PM PST 24
Peak memory 195704 kb
Host smart-b4e76370-0f04-4b86-b4ce-3f73d93d0e7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604413626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1604413626
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2590143443
Short name T618
Test name
Test status
Simulation time 40672013218 ps
CPU time 153.47 seconds
Started Mar 07 01:20:13 PM PST 24
Finished Mar 07 01:22:46 PM PST 24
Peak memory 198264 kb
Host smart-da8c35ef-335c-46f6-8bdb-4b09c7d70bc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590143443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2590143443
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.2255711390
Short name T557
Test name
Test status
Simulation time 39467372 ps
CPU time 0.58 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:21:50 PM PST 24
Peak memory 194304 kb
Host smart-ddf6ca0f-cd49-41c6-a836-8d02e5ad81e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255711390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.2255711390
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3859341367
Short name T227
Test name
Test status
Simulation time 84421778 ps
CPU time 0.78 seconds
Started Mar 07 01:21:53 PM PST 24
Finished Mar 07 01:21:54 PM PST 24
Peak memory 196008 kb
Host smart-6b0190d2-1b54-44d5-8547-6ca226ddea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859341367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3859341367
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3355060309
Short name T427
Test name
Test status
Simulation time 466036486 ps
CPU time 23.7 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:22:13 PM PST 24
Peak memory 196832 kb
Host smart-d199a486-77b5-46a7-971c-29a192fe9b4b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355060309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3355060309
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.444806757
Short name T20
Test name
Test status
Simulation time 128630861 ps
CPU time 0.66 seconds
Started Mar 07 01:21:48 PM PST 24
Finished Mar 07 01:21:49 PM PST 24
Peak memory 194680 kb
Host smart-17af9509-ea53-4ce1-a57a-da671fe0d2cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444806757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.444806757
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2517754241
Short name T469
Test name
Test status
Simulation time 155515836 ps
CPU time 1.14 seconds
Started Mar 07 01:21:57 PM PST 24
Finished Mar 07 01:21:59 PM PST 24
Peak memory 196264 kb
Host smart-1bce3819-1113-44ad-8568-1b0e6e9c976a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517754241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2517754241
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.628370141
Short name T410
Test name
Test status
Simulation time 167339726 ps
CPU time 3.51 seconds
Started Mar 07 01:21:55 PM PST 24
Finished Mar 07 01:21:58 PM PST 24
Peak memory 196628 kb
Host smart-5cbee42c-5694-42bb-abd1-44e356c7b623
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628370141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.628370141
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2967626867
Short name T24
Test name
Test status
Simulation time 55783215 ps
CPU time 1.34 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:52 PM PST 24
Peak memory 197660 kb
Host smart-64e6b62a-68bd-4be3-9156-a3096e1d2386
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967626867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2967626867
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.28820786
Short name T228
Test name
Test status
Simulation time 48872035 ps
CPU time 0.63 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:51 PM PST 24
Peak memory 194388 kb
Host smart-16f34909-493b-4497-8f15-fb08b000b896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28820786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.28820786
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1304556877
Short name T323
Test name
Test status
Simulation time 28908657 ps
CPU time 1.1 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:21:51 PM PST 24
Peak memory 196780 kb
Host smart-1164e2e1-800f-44da-b47d-156b92fad87d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304556877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1304556877
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.3682308250
Short name T158
Test name
Test status
Simulation time 123267960 ps
CPU time 5.87 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:21:55 PM PST 24
Peak memory 197980 kb
Host smart-c2d34e30-9b87-42c7-b049-ad424d53d028
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682308250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.3682308250
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.2577858904
Short name T215
Test name
Test status
Simulation time 30613022 ps
CPU time 0.93 seconds
Started Mar 07 01:21:48 PM PST 24
Finished Mar 07 01:21:49 PM PST 24
Peak memory 195844 kb
Host smart-54a831a3-b84d-4d3d-8851-bddc1c54e605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577858904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.2577858904
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2745563670
Short name T509
Test name
Test status
Simulation time 121449816 ps
CPU time 1.12 seconds
Started Mar 07 01:21:52 PM PST 24
Finished Mar 07 01:21:53 PM PST 24
Peak memory 195836 kb
Host smart-3b194061-2bb2-4238-92dd-62677a12c41a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745563670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2745563670
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3999863172
Short name T598
Test name
Test status
Simulation time 6972485664 ps
CPU time 47.5 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:22:38 PM PST 24
Peak memory 198332 kb
Host smart-99364883-4234-47f5-9797-a21e0633abcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999863172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3999863172
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2321567560
Short name T666
Test name
Test status
Simulation time 15069985 ps
CPU time 0.59 seconds
Started Mar 07 01:21:58 PM PST 24
Finished Mar 07 01:21:59 PM PST 24
Peak memory 194292 kb
Host smart-c0b8a228-2508-466b-90ee-72fffadc9217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321567560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2321567560
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2520838907
Short name T147
Test name
Test status
Simulation time 137722520 ps
CPU time 0.84 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:51 PM PST 24
Peak memory 195436 kb
Host smart-634c5c68-599d-4f37-9c24-1d4a544cd460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520838907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2520838907
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1400467130
Short name T584
Test name
Test status
Simulation time 749882298 ps
CPU time 7.1 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:57 PM PST 24
Peak memory 195732 kb
Host smart-2e99fff2-de76-4619-ae3f-da425f9fbca6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400467130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1400467130
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.38684633
Short name T241
Test name
Test status
Simulation time 128268050 ps
CPU time 1 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:51 PM PST 24
Peak memory 196608 kb
Host smart-3fc05885-909f-4c23-aa6b-10680c0cf405
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38684633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.38684633
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1855833648
Short name T523
Test name
Test status
Simulation time 328612656 ps
CPU time 1.27 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:52 PM PST 24
Peak memory 196304 kb
Host smart-fb270cdd-2284-4b97-b184-8c72acb3ac4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855833648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1855833648
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3384337897
Short name T254
Test name
Test status
Simulation time 46464097 ps
CPU time 1.06 seconds
Started Mar 07 01:21:45 PM PST 24
Finished Mar 07 01:21:46 PM PST 24
Peak memory 197588 kb
Host smart-c15d4627-6b82-426e-92df-2eccbaf635a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384337897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3384337897
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.48383828
Short name T78
Test name
Test status
Simulation time 397853692 ps
CPU time 3.05 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:54 PM PST 24
Peak memory 195976 kb
Host smart-2bacc2f1-9b9b-4a60-94ee-95e660b05c7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48383828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.48383828
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3015962706
Short name T458
Test name
Test status
Simulation time 37830434 ps
CPU time 1.06 seconds
Started Mar 07 01:21:58 PM PST 24
Finished Mar 07 01:22:00 PM PST 24
Peak memory 196172 kb
Host smart-e73c49cb-cb71-4fbc-b66a-43a072a1bbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015962706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3015962706
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.3357532281
Short name T352
Test name
Test status
Simulation time 82193162 ps
CPU time 0.92 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:21:51 PM PST 24
Peak memory 195952 kb
Host smart-01911595-244a-4e72-88b5-ab21eaf917f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357532281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.3357532281
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1261838871
Short name T423
Test name
Test status
Simulation time 2896289424 ps
CPU time 5.19 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:55 PM PST 24
Peak memory 198280 kb
Host smart-725cd33e-5091-4d83-b4f8-80f11c0aad8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261838871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1261838871
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1311925044
Short name T276
Test name
Test status
Simulation time 63848286 ps
CPU time 1.21 seconds
Started Mar 07 01:21:47 PM PST 24
Finished Mar 07 01:21:49 PM PST 24
Peak memory 197272 kb
Host smart-2d79b089-64fe-4164-804c-7212c0f159ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311925044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1311925044
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2734078025
Short name T142
Test name
Test status
Simulation time 45548712 ps
CPU time 0.92 seconds
Started Mar 07 01:21:55 PM PST 24
Finished Mar 07 01:21:57 PM PST 24
Peak memory 196252 kb
Host smart-39db1b76-dd61-4682-9f7b-12e59de90e3d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734078025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2734078025
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2114447889
Short name T169
Test name
Test status
Simulation time 5676218885 ps
CPU time 86.44 seconds
Started Mar 07 01:21:57 PM PST 24
Finished Mar 07 01:23:24 PM PST 24
Peak memory 198368 kb
Host smart-bc07349a-217e-4c4e-8770-a892efe336d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114447889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2114447889
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.4093751161
Short name T58
Test name
Test status
Simulation time 37489496762 ps
CPU time 914.47 seconds
Started Mar 07 01:21:54 PM PST 24
Finished Mar 07 01:37:09 PM PST 24
Peak memory 198496 kb
Host smart-43274b35-f3f7-41b4-bb81-8e83c7a54e8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4093751161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.4093751161
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.83858648
Short name T242
Test name
Test status
Simulation time 25567872 ps
CPU time 0.56 seconds
Started Mar 07 01:21:47 PM PST 24
Finished Mar 07 01:21:48 PM PST 24
Peak memory 194340 kb
Host smart-45b0959f-062c-4d46-9d28-fe5c51921b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83858648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.83858648
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2700162985
Short name T133
Test name
Test status
Simulation time 125281870 ps
CPU time 0.93 seconds
Started Mar 07 01:21:52 PM PST 24
Finished Mar 07 01:21:53 PM PST 24
Peak memory 196988 kb
Host smart-470e44a4-c569-4fda-87f6-5a7c676d9848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700162985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2700162985
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.138790404
Short name T439
Test name
Test status
Simulation time 1781280656 ps
CPU time 22.78 seconds
Started Mar 07 01:21:52 PM PST 24
Finished Mar 07 01:22:15 PM PST 24
Peak memory 195832 kb
Host smart-2240b160-24f4-4241-a3e1-c4b37f1de1a3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138790404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.138790404
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2826972373
Short name T721
Test name
Test status
Simulation time 83963135 ps
CPU time 1.1 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:52 PM PST 24
Peak memory 196820 kb
Host smart-3c053d09-8d2a-4e49-8255-9675ad125634
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826972373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2826972373
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.45288306
Short name T264
Test name
Test status
Simulation time 43885525 ps
CPU time 1.26 seconds
Started Mar 07 01:21:58 PM PST 24
Finished Mar 07 01:22:00 PM PST 24
Peak memory 196280 kb
Host smart-a748a8e5-3633-4b62-bbf1-4e9ed64a0d90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45288306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.45288306
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.37044910
Short name T627
Test name
Test status
Simulation time 76912393 ps
CPU time 1.58 seconds
Started Mar 07 01:21:52 PM PST 24
Finished Mar 07 01:21:54 PM PST 24
Peak memory 197084 kb
Host smart-38d4d068-3010-4401-aed0-8cf5f012468f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37044910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 42.gpio_intr_with_filter_rand_intr_event.37044910
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1599970936
Short name T673
Test name
Test status
Simulation time 135284338 ps
CPU time 2.8 seconds
Started Mar 07 01:21:48 PM PST 24
Finished Mar 07 01:21:51 PM PST 24
Peak memory 195976 kb
Host smart-afaadf9d-5530-4fe9-a755-8d2d329c9ce5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599970936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1599970936
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2109403378
Short name T222
Test name
Test status
Simulation time 51381618 ps
CPU time 1.12 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:53 PM PST 24
Peak memory 196896 kb
Host smart-69075d58-6745-484a-a903-eb412bbe6635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109403378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2109403378
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.2164169115
Short name T697
Test name
Test status
Simulation time 246305748 ps
CPU time 1.28 seconds
Started Mar 07 01:21:53 PM PST 24
Finished Mar 07 01:21:55 PM PST 24
Peak memory 196732 kb
Host smart-4c8103a8-9acd-4681-9103-d1cfb0f45924
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164169115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.2164169115
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.1479052537
Short name T539
Test name
Test status
Simulation time 69689206 ps
CPU time 3.3 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:54 PM PST 24
Peak memory 198140 kb
Host smart-3a5939e8-fcc1-4b07-917c-d739074eda8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479052537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.1479052537
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3981613444
Short name T173
Test name
Test status
Simulation time 67023225 ps
CPU time 1.55 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:53 PM PST 24
Peak memory 198124 kb
Host smart-2b757168-f5ee-4402-bab7-1424ff3e24c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981613444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3981613444
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3146275453
Short name T370
Test name
Test status
Simulation time 427461774 ps
CPU time 1.34 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:53 PM PST 24
Peak memory 195636 kb
Host smart-0ea6ab7d-6eb3-492d-8b2f-ece6e3beee84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146275453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3146275453
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.4279104471
Short name T465
Test name
Test status
Simulation time 15953440299 ps
CPU time 174.73 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:24:47 PM PST 24
Peak memory 198320 kb
Host smart-5e270a7b-697e-440e-b71d-561124322495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279104471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.4279104471
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3616160693
Short name T61
Test name
Test status
Simulation time 159916019714 ps
CPU time 2056.73 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:56:06 PM PST 24
Peak memory 198504 kb
Host smart-e6eddbb3-18b4-43a6-a495-6c1fb1b0073a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3616160693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3616160693
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.614614136
Short name T245
Test name
Test status
Simulation time 32791062 ps
CPU time 0.58 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:50 PM PST 24
Peak memory 194112 kb
Host smart-a1ea9306-3084-4d5d-9f7b-5925229e5517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614614136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.614614136
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.186248836
Short name T604
Test name
Test status
Simulation time 15121381 ps
CPU time 0.61 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:51 PM PST 24
Peak memory 193916 kb
Host smart-8989adbd-ceac-48c1-b5a3-eb8be502d62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186248836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.186248836
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1798342556
Short name T699
Test name
Test status
Simulation time 1705688119 ps
CPU time 27.28 seconds
Started Mar 07 01:21:54 PM PST 24
Finished Mar 07 01:22:22 PM PST 24
Peak memory 198148 kb
Host smart-fb8d55ac-ee71-4bdc-89c5-efa3dbbaf520
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798342556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1798342556
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2729772393
Short name T511
Test name
Test status
Simulation time 146541062 ps
CPU time 1.05 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:21:50 PM PST 24
Peak memory 197968 kb
Host smart-28352ffe-a408-41e7-a9a0-a901add1d32e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729772393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2729772393
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1702713670
Short name T646
Test name
Test status
Simulation time 35655548 ps
CPU time 0.83 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:51 PM PST 24
Peak memory 196752 kb
Host smart-bce58403-de96-466a-85df-dad284fd6ca6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702713670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1702713670
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.825662985
Short name T11
Test name
Test status
Simulation time 88333330 ps
CPU time 1.01 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:21:50 PM PST 24
Peak memory 197144 kb
Host smart-decc25df-485e-4e41-8726-ec859387b00b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825662985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.825662985
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2703404568
Short name T637
Test name
Test status
Simulation time 80479178 ps
CPU time 0.83 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:52 PM PST 24
Peak memory 194480 kb
Host smart-3a4acc52-1620-48de-9e4e-97ff62e6010c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703404568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2703404568
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.1388625322
Short name T639
Test name
Test status
Simulation time 131100785 ps
CPU time 1.29 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:52 PM PST 24
Peak memory 198144 kb
Host smart-bd2abe81-686b-4da4-a853-2e983063daf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388625322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.1388625322
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.3697965661
Short name T479
Test name
Test status
Simulation time 287189484 ps
CPU time 1.28 seconds
Started Mar 07 01:21:47 PM PST 24
Finished Mar 07 01:21:49 PM PST 24
Peak memory 197032 kb
Host smart-77e39b63-bb18-43a4-803d-6890a3678ccf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697965661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.3697965661
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3964857245
Short name T351
Test name
Test status
Simulation time 617551200 ps
CPU time 4.57 seconds
Started Mar 07 01:21:49 PM PST 24
Finished Mar 07 01:21:54 PM PST 24
Peak memory 198116 kb
Host smart-91330258-cc90-4781-a125-298fc7fbe977
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964857245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3964857245
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2856063789
Short name T630
Test name
Test status
Simulation time 71484957 ps
CPU time 1.09 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:51 PM PST 24
Peak memory 196600 kb
Host smart-bad2ba68-ebf9-459a-b0de-5be66e61b95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856063789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2856063789
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.3003250259
Short name T27
Test name
Test status
Simulation time 60501195 ps
CPU time 1.01 seconds
Started Mar 07 01:21:55 PM PST 24
Finished Mar 07 01:21:57 PM PST 24
Peak memory 195864 kb
Host smart-34077d4c-8b86-447f-8a6f-8f203dcadf4a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003250259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.3003250259
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.10062523
Short name T612
Test name
Test status
Simulation time 31578782323 ps
CPU time 212.21 seconds
Started Mar 07 01:22:00 PM PST 24
Finished Mar 07 01:25:33 PM PST 24
Peak memory 198408 kb
Host smart-3d66ecc6-bb7f-47da-8d51-fcd92ee424e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10062523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gp
io_stress_all.10062523
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1828370203
Short name T140
Test name
Test status
Simulation time 62333387 ps
CPU time 0.64 seconds
Started Mar 07 01:22:05 PM PST 24
Finished Mar 07 01:22:08 PM PST 24
Peak memory 194192 kb
Host smart-14192263-c9a8-4e8b-803c-60c2dfd19b67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828370203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1828370203
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2480730218
Short name T537
Test name
Test status
Simulation time 122749864 ps
CPU time 0.71 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:53 PM PST 24
Peak memory 195544 kb
Host smart-0500dfba-c002-4e27-a388-7fb369f3f637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480730218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2480730218
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3210848049
Short name T177
Test name
Test status
Simulation time 2060681295 ps
CPU time 15.44 seconds
Started Mar 07 01:21:56 PM PST 24
Finished Mar 07 01:22:12 PM PST 24
Peak memory 197012 kb
Host smart-d1dc5618-2161-4556-85cf-34560bc767ff
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210848049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3210848049
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1336040450
Short name T658
Test name
Test status
Simulation time 90572208 ps
CPU time 1.05 seconds
Started Mar 07 01:22:01 PM PST 24
Finished Mar 07 01:22:03 PM PST 24
Peak memory 198092 kb
Host smart-8161bcf4-e7dd-41bc-acec-c19cddc9e362
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336040450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1336040450
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2741605380
Short name T396
Test name
Test status
Simulation time 138381753 ps
CPU time 0.88 seconds
Started Mar 07 01:21:51 PM PST 24
Finished Mar 07 01:21:53 PM PST 24
Peak memory 196508 kb
Host smart-a6102f0e-34e1-47d1-8ccd-8dcf1aeaa8a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741605380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2741605380
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.683000078
Short name T429
Test name
Test status
Simulation time 112638357 ps
CPU time 1.23 seconds
Started Mar 07 01:21:52 PM PST 24
Finished Mar 07 01:21:53 PM PST 24
Peak memory 196760 kb
Host smart-90055dff-279a-4692-937c-9d8ee8de5254
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683000078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.683000078
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.287521927
Short name T562
Test name
Test status
Simulation time 189856981 ps
CPU time 2.43 seconds
Started Mar 07 01:21:58 PM PST 24
Finished Mar 07 01:22:01 PM PST 24
Peak memory 197128 kb
Host smart-c8d21170-cec8-4557-b5a2-9debb45aab18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287521927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
287521927
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2926058819
Short name T117
Test name
Test status
Simulation time 50848697 ps
CPU time 1.05 seconds
Started Mar 07 01:21:57 PM PST 24
Finished Mar 07 01:21:59 PM PST 24
Peak memory 196688 kb
Host smart-98776d3a-4350-4c03-8400-9990ce40804b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926058819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2926058819
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.1007781800
Short name T343
Test name
Test status
Simulation time 39967179 ps
CPU time 0.85 seconds
Started Mar 07 01:21:55 PM PST 24
Finished Mar 07 01:21:57 PM PST 24
Peak memory 196808 kb
Host smart-89427e15-6ad3-48ef-be3e-f55cc46fd3ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007781800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.1007781800
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1212572459
Short name T433
Test name
Test status
Simulation time 655902741 ps
CPU time 1.71 seconds
Started Mar 07 01:21:56 PM PST 24
Finished Mar 07 01:21:58 PM PST 24
Peak memory 198124 kb
Host smart-005d8a3e-5893-414f-8b3b-4518be60f0d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212572459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1212572459
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2135784827
Short name T179
Test name
Test status
Simulation time 45196299 ps
CPU time 1.01 seconds
Started Mar 07 01:22:01 PM PST 24
Finished Mar 07 01:22:03 PM PST 24
Peak memory 196640 kb
Host smart-a3bda7e2-7184-488d-b7f7-778433ff1f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135784827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2135784827
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3050646051
Short name T696
Test name
Test status
Simulation time 261276060 ps
CPU time 1.26 seconds
Started Mar 07 01:21:50 PM PST 24
Finished Mar 07 01:21:51 PM PST 24
Peak memory 195868 kb
Host smart-8ecd2467-d598-4c2b-9ea7-c82d958c5696
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050646051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3050646051
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.2275889654
Short name T172
Test name
Test status
Simulation time 3384951445 ps
CPU time 46.64 seconds
Started Mar 07 01:21:56 PM PST 24
Finished Mar 07 01:22:43 PM PST 24
Peak memory 198244 kb
Host smart-709dfd69-9b6c-44b4-a52c-defa3927aa7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275889654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.2275889654
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3171455475
Short name T519
Test name
Test status
Simulation time 52443946 ps
CPU time 0.58 seconds
Started Mar 07 01:22:09 PM PST 24
Finished Mar 07 01:22:10 PM PST 24
Peak memory 194284 kb
Host smart-ba8c20cc-9077-4bf4-bb5e-675c8d345253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171455475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3171455475
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.894229611
Short name T701
Test name
Test status
Simulation time 24258006 ps
CPU time 0.81 seconds
Started Mar 07 01:21:57 PM PST 24
Finished Mar 07 01:21:59 PM PST 24
Peak memory 196144 kb
Host smart-8858d443-4c5f-47ae-9893-c131dc2b3d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894229611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.894229611
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.932462459
Short name T225
Test name
Test status
Simulation time 1004763828 ps
CPU time 30.13 seconds
Started Mar 07 01:22:07 PM PST 24
Finished Mar 07 01:22:38 PM PST 24
Peak memory 198128 kb
Host smart-3da2a1a5-8328-406f-9263-6b3d72d0d9ef
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932462459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stres
s.932462459
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2682668902
Short name T13
Test name
Test status
Simulation time 36924572 ps
CPU time 0.76 seconds
Started Mar 07 01:21:58 PM PST 24
Finished Mar 07 01:22:00 PM PST 24
Peak memory 196616 kb
Host smart-875611dd-2dd7-436e-9e16-4d863010b433
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682668902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2682668902
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1372850524
Short name T382
Test name
Test status
Simulation time 96865297 ps
CPU time 0.95 seconds
Started Mar 07 01:22:03 PM PST 24
Finished Mar 07 01:22:05 PM PST 24
Peak memory 196820 kb
Host smart-d88766e1-e15f-410f-9f47-27983a71ecca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372850524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1372850524
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2237919862
Short name T250
Test name
Test status
Simulation time 139502470 ps
CPU time 2.58 seconds
Started Mar 07 01:22:00 PM PST 24
Finished Mar 07 01:22:03 PM PST 24
Peak memory 196416 kb
Host smart-f5edd8e0-34b8-43bb-b1fa-a47be17e9a38
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237919862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2237919862
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1897581606
Short name T568
Test name
Test status
Simulation time 242347133 ps
CPU time 2.3 seconds
Started Mar 07 01:21:58 PM PST 24
Finished Mar 07 01:22:01 PM PST 24
Peak memory 196024 kb
Host smart-0c4ee9fa-9599-4144-acf5-d93f615af095
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897581606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1897581606
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.29590
Short name T220
Test name
Test status
Simulation time 39938523 ps
CPU time 0.99 seconds
Started Mar 07 01:22:09 PM PST 24
Finished Mar 07 01:22:10 PM PST 24
Peak memory 196124 kb
Host smart-dce99772-a5d8-478c-83fd-ba7c19720054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.29590
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.209720413
Short name T12
Test name
Test status
Simulation time 17350977 ps
CPU time 0.76 seconds
Started Mar 07 01:21:57 PM PST 24
Finished Mar 07 01:21:58 PM PST 24
Peak memory 196096 kb
Host smart-3f2133a7-aa35-4d38-963f-8b79a29fd391
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209720413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.209720413
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1713596702
Short name T543
Test name
Test status
Simulation time 311911148 ps
CPU time 3.35 seconds
Started Mar 07 01:22:02 PM PST 24
Finished Mar 07 01:22:06 PM PST 24
Peak memory 198116 kb
Host smart-4e721049-f58b-4c5f-9d55-c6e71a814891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713596702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1713596702
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.3880216249
Short name T65
Test name
Test status
Simulation time 91306717 ps
CPU time 1.36 seconds
Started Mar 07 01:21:59 PM PST 24
Finished Mar 07 01:22:01 PM PST 24
Peak memory 198068 kb
Host smart-a77d4ff4-798e-4cc4-9348-6f99f43bab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880216249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.3880216249
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.1667885818
Short name T143
Test name
Test status
Simulation time 51791967 ps
CPU time 1 seconds
Started Mar 07 01:22:02 PM PST 24
Finished Mar 07 01:22:04 PM PST 24
Peak memory 196616 kb
Host smart-7f8f70c6-b988-44c7-b473-bf6fcc65f1d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667885818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.1667885818
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.846534845
Short name T712
Test name
Test status
Simulation time 13261356448 ps
CPU time 163.26 seconds
Started Mar 07 01:21:57 PM PST 24
Finished Mar 07 01:24:42 PM PST 24
Peak memory 198276 kb
Host smart-21711c12-22b7-4a43-bb1a-c38ceb55ea97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846534845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.846534845
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1443746035
Short name T472
Test name
Test status
Simulation time 13810921 ps
CPU time 0.62 seconds
Started Mar 07 01:22:08 PM PST 24
Finished Mar 07 01:22:10 PM PST 24
Peak memory 194316 kb
Host smart-58097cb7-643f-4f3c-9cc8-c5cc5b01aa1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443746035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1443746035
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1913164400
Short name T596
Test name
Test status
Simulation time 299485010 ps
CPU time 0.83 seconds
Started Mar 07 01:22:00 PM PST 24
Finished Mar 07 01:22:02 PM PST 24
Peak memory 197280 kb
Host smart-13bc2803-a9d0-4484-ba86-0095d3da8cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913164400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1913164400
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2916517774
Short name T546
Test name
Test status
Simulation time 208739314 ps
CPU time 6.01 seconds
Started Mar 07 01:22:00 PM PST 24
Finished Mar 07 01:22:07 PM PST 24
Peak memory 198128 kb
Host smart-a0bba58d-c758-4273-a53d-1df252203383
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916517774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2916517774
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3538782068
Short name T441
Test name
Test status
Simulation time 196250805 ps
CPU time 0.87 seconds
Started Mar 07 01:21:57 PM PST 24
Finished Mar 07 01:21:59 PM PST 24
Peak memory 197984 kb
Host smart-1a71ec34-8541-4c21-82e2-2e2f4594e7cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538782068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3538782068
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.604591880
Short name T664
Test name
Test status
Simulation time 262208171 ps
CPU time 1.04 seconds
Started Mar 07 01:22:05 PM PST 24
Finished Mar 07 01:22:06 PM PST 24
Peak memory 195944 kb
Host smart-950a1df8-26e5-4b64-b365-756826eef556
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604591880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.604591880
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3199722349
Short name T211
Test name
Test status
Simulation time 108194714 ps
CPU time 1.16 seconds
Started Mar 07 01:22:02 PM PST 24
Finished Mar 07 01:22:04 PM PST 24
Peak memory 196868 kb
Host smart-fc4a95d8-9005-4146-98d2-14904efdb205
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199722349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3199722349
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1815380430
Short name T605
Test name
Test status
Simulation time 107277313 ps
CPU time 3.4 seconds
Started Mar 07 01:21:59 PM PST 24
Finished Mar 07 01:22:04 PM PST 24
Peak memory 197124 kb
Host smart-e5d442f0-32e8-450d-bb91-a5114321905c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815380430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1815380430
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1452310923
Short name T149
Test name
Test status
Simulation time 354237684 ps
CPU time 1.12 seconds
Started Mar 07 01:22:05 PM PST 24
Finished Mar 07 01:22:06 PM PST 24
Peak memory 195960 kb
Host smart-31afe458-c5e9-4f03-9045-fd336c08cd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452310923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1452310923
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2166680964
Short name T659
Test name
Test status
Simulation time 95371813 ps
CPU time 0.8 seconds
Started Mar 07 01:21:57 PM PST 24
Finished Mar 07 01:21:58 PM PST 24
Peak memory 195588 kb
Host smart-8d0bb605-785c-4ad3-97ec-12dd070248e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166680964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2166680964
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2191833823
Short name T292
Test name
Test status
Simulation time 78170462 ps
CPU time 3.45 seconds
Started Mar 07 01:22:05 PM PST 24
Finished Mar 07 01:22:10 PM PST 24
Peak memory 198000 kb
Host smart-42dabd4d-02df-4f71-95f7-877b89523c08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191833823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2191833823
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.372795587
Short name T541
Test name
Test status
Simulation time 303330760 ps
CPU time 1.01 seconds
Started Mar 07 01:21:57 PM PST 24
Finished Mar 07 01:21:59 PM PST 24
Peak memory 195664 kb
Host smart-3df514d8-4f9a-4df3-a53d-21dcd9ff7428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372795587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.372795587
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3922601195
Short name T195
Test name
Test status
Simulation time 192123427 ps
CPU time 1.05 seconds
Started Mar 07 01:21:59 PM PST 24
Finished Mar 07 01:22:01 PM PST 24
Peak memory 196588 kb
Host smart-a0b3fb14-cee7-4e4c-9bbe-f66e486dfbbc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922601195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3922601195
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3496788318
Short name T342
Test name
Test status
Simulation time 9738298693 ps
CPU time 131.32 seconds
Started Mar 07 01:22:07 PM PST 24
Finished Mar 07 01:24:19 PM PST 24
Peak memory 198256 kb
Host smart-7823cd15-fdb0-4c6b-aa9a-82dbddec3b90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496788318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3496788318
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2291714765
Short name T620
Test name
Test status
Simulation time 10725637 ps
CPU time 0.58 seconds
Started Mar 07 01:22:07 PM PST 24
Finished Mar 07 01:22:09 PM PST 24
Peak memory 194060 kb
Host smart-3cf3cb5a-5363-4ec1-b39d-ce881ad901ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291714765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2291714765
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.136290495
Short name T26
Test name
Test status
Simulation time 42330809 ps
CPU time 0.68 seconds
Started Mar 07 01:22:05 PM PST 24
Finished Mar 07 01:22:06 PM PST 24
Peak memory 194264 kb
Host smart-1457d0c3-5fb7-495e-a873-3f8e970c0156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136290495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.136290495
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2903393179
Short name T122
Test name
Test status
Simulation time 965402873 ps
CPU time 7.67 seconds
Started Mar 07 01:21:57 PM PST 24
Finished Mar 07 01:22:06 PM PST 24
Peak memory 198188 kb
Host smart-be5dc9fc-2ed7-4137-8b68-402d9cfce7d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903393179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2903393179
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.986292040
Short name T514
Test name
Test status
Simulation time 332906814 ps
CPU time 1.07 seconds
Started Mar 07 01:22:08 PM PST 24
Finished Mar 07 01:22:09 PM PST 24
Peak memory 197888 kb
Host smart-46e4331a-edeb-42c6-aabb-7d1025596d50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986292040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.986292040
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1691197308
Short name T304
Test name
Test status
Simulation time 223212962 ps
CPU time 1.17 seconds
Started Mar 07 01:22:00 PM PST 24
Finished Mar 07 01:22:02 PM PST 24
Peak memory 197212 kb
Host smart-901bf2ec-d5e3-4154-b586-5e6c98776a29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691197308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1691197308
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.1728864374
Short name T180
Test name
Test status
Simulation time 286247570 ps
CPU time 1.89 seconds
Started Mar 07 01:21:59 PM PST 24
Finished Mar 07 01:22:02 PM PST 24
Peak memory 198240 kb
Host smart-ffefe9ac-642a-4f29-a592-ff3ca8b487ef
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728864374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.1728864374
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.657141042
Short name T495
Test name
Test status
Simulation time 369591067 ps
CPU time 2.13 seconds
Started Mar 07 01:22:00 PM PST 24
Finished Mar 07 01:22:03 PM PST 24
Peak memory 197164 kb
Host smart-1d316924-e094-4a27-9bb5-a9472db33565
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657141042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
657141042
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1409911862
Short name T240
Test name
Test status
Simulation time 38183029 ps
CPU time 1.2 seconds
Started Mar 07 01:22:05 PM PST 24
Finished Mar 07 01:22:07 PM PST 24
Peak memory 196156 kb
Host smart-3c95c1cf-507d-43d9-a6a2-fb9568aab8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409911862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1409911862
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2550025560
Short name T462
Test name
Test status
Simulation time 107356997 ps
CPU time 1.09 seconds
Started Mar 07 01:22:03 PM PST 24
Finished Mar 07 01:22:05 PM PST 24
Peak memory 196028 kb
Host smart-77cb99ba-0d95-4fdc-98d1-bcd6c99690bd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550025560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2550025560
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2867396093
Short name T432
Test name
Test status
Simulation time 613586206 ps
CPU time 2.31 seconds
Started Mar 07 01:22:01 PM PST 24
Finished Mar 07 01:22:04 PM PST 24
Peak memory 198232 kb
Host smart-807841c7-64fa-445d-bbe9-0ed065df0eec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867396093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2867396093
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.4242046157
Short name T538
Test name
Test status
Simulation time 184978471 ps
CPU time 0.87 seconds
Started Mar 07 01:22:02 PM PST 24
Finished Mar 07 01:22:04 PM PST 24
Peak memory 196256 kb
Host smart-8d66b30f-33cb-40fa-b9a2-67244c3f9a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242046157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.4242046157
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.87404966
Short name T579
Test name
Test status
Simulation time 72211551 ps
CPU time 1.14 seconds
Started Mar 07 01:21:58 PM PST 24
Finished Mar 07 01:22:00 PM PST 24
Peak memory 195912 kb
Host smart-6182abb7-2006-4926-8599-5a1c8f1b975a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87404966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.87404966
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.3468998748
Short name T5
Test name
Test status
Simulation time 5487743863 ps
CPU time 59.02 seconds
Started Mar 07 01:22:05 PM PST 24
Finished Mar 07 01:23:05 PM PST 24
Peak memory 198312 kb
Host smart-ca185f00-d417-4d02-9595-031d45f01dff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468998748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.3468998748
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3858695151
Short name T633
Test name
Test status
Simulation time 21871924933 ps
CPU time 301.19 seconds
Started Mar 07 01:22:05 PM PST 24
Finished Mar 07 01:27:07 PM PST 24
Peak memory 198444 kb
Host smart-792d6b03-cfa8-42f4-b220-799b455ca801
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3858695151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3858695151
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.706956156
Short name T670
Test name
Test status
Simulation time 12237651 ps
CPU time 0.55 seconds
Started Mar 07 01:22:06 PM PST 24
Finished Mar 07 01:22:08 PM PST 24
Peak memory 194064 kb
Host smart-6d8b4201-e65d-4f36-a281-472c7f60c430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706956156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.706956156
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.4028350462
Short name T308
Test name
Test status
Simulation time 19487692 ps
CPU time 0.66 seconds
Started Mar 07 01:22:05 PM PST 24
Finished Mar 07 01:22:06 PM PST 24
Peak memory 194304 kb
Host smart-fb38e483-6863-4581-b6f7-60dcb11547cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028350462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.4028350462
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1074522793
Short name T193
Test name
Test status
Simulation time 3012532657 ps
CPU time 25.12 seconds
Started Mar 07 01:22:00 PM PST 24
Finished Mar 07 01:22:26 PM PST 24
Peak memory 197112 kb
Host smart-a1122f8d-0bef-41f9-abd4-f3fb30d44f34
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074522793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1074522793
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1581864857
Short name T476
Test name
Test status
Simulation time 35304153 ps
CPU time 0.69 seconds
Started Mar 07 01:22:07 PM PST 24
Finished Mar 07 01:22:08 PM PST 24
Peak memory 194836 kb
Host smart-e3914f70-52f6-427a-bd7e-c06cf7fd3210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581864857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1581864857
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.859431221
Short name T644
Test name
Test status
Simulation time 166059178 ps
CPU time 0.67 seconds
Started Mar 07 01:22:07 PM PST 24
Finished Mar 07 01:22:09 PM PST 24
Peak memory 194384 kb
Host smart-3cc2edb7-4c2d-4a03-bd92-e9caefd4f6c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859431221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.859431221
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.3046082955
Short name T576
Test name
Test status
Simulation time 24996106 ps
CPU time 1.05 seconds
Started Mar 07 01:22:05 PM PST 24
Finished Mar 07 01:22:06 PM PST 24
Peak memory 197052 kb
Host smart-a0a66809-5d11-4837-b13b-84f7d6852003
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046082955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.3046082955
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3725485647
Short name T711
Test name
Test status
Simulation time 46901156 ps
CPU time 0.95 seconds
Started Mar 07 01:21:58 PM PST 24
Finished Mar 07 01:22:00 PM PST 24
Peak memory 195548 kb
Host smart-fe4b9f0d-d397-4d1b-a9d3-37e86692b7c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725485647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3725485647
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3875828330
Short name T707
Test name
Test status
Simulation time 84688299 ps
CPU time 0.98 seconds
Started Mar 07 01:22:04 PM PST 24
Finished Mar 07 01:22:06 PM PST 24
Peak memory 196200 kb
Host smart-f855f985-c3ad-4bc1-8e23-52997a98a1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875828330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3875828330
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2981007361
Short name T708
Test name
Test status
Simulation time 95079511 ps
CPU time 1.21 seconds
Started Mar 07 01:22:03 PM PST 24
Finished Mar 07 01:22:05 PM PST 24
Peak memory 197244 kb
Host smart-cb8a2908-b46f-481e-ac99-ae1f5951fc10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981007361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2981007361
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.4161509465
Short name T577
Test name
Test status
Simulation time 1207560371 ps
CPU time 1.98 seconds
Started Mar 07 01:21:56 PM PST 24
Finished Mar 07 01:21:59 PM PST 24
Peak memory 198104 kb
Host smart-0d833f3a-87d5-49fc-9993-ca6cf2f2425a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161509465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.4161509465
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3202957684
Short name T349
Test name
Test status
Simulation time 102395573 ps
CPU time 1.38 seconds
Started Mar 07 01:22:02 PM PST 24
Finished Mar 07 01:22:05 PM PST 24
Peak memory 196888 kb
Host smart-dd9c6457-4cc6-46ac-87c4-1849df264388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202957684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3202957684
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3289471116
Short name T267
Test name
Test status
Simulation time 78739883 ps
CPU time 1.28 seconds
Started Mar 07 01:22:08 PM PST 24
Finished Mar 07 01:22:10 PM PST 24
Peak memory 196868 kb
Host smart-63d0df12-6401-4315-b0be-ceb3799b75ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289471116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3289471116
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1097697883
Short name T33
Test name
Test status
Simulation time 9534799629 ps
CPU time 57.53 seconds
Started Mar 07 01:22:05 PM PST 24
Finished Mar 07 01:23:05 PM PST 24
Peak memory 198324 kb
Host smart-06833b25-618c-43b6-8c1e-33e307754b79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097697883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1097697883
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1246489539
Short name T376
Test name
Test status
Simulation time 39350926 ps
CPU time 0.56 seconds
Started Mar 07 01:22:08 PM PST 24
Finished Mar 07 01:22:09 PM PST 24
Peak memory 194040 kb
Host smart-667797e1-5947-443b-b791-9aa1726921b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246489539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1246489539
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.307524217
Short name T126
Test name
Test status
Simulation time 124478746 ps
CPU time 0.9 seconds
Started Mar 07 01:22:09 PM PST 24
Finished Mar 07 01:22:10 PM PST 24
Peak memory 197276 kb
Host smart-c3460554-5c78-456b-bbaf-74500317b264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307524217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.307524217
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1150985081
Short name T390
Test name
Test status
Simulation time 1387034191 ps
CPU time 13.51 seconds
Started Mar 07 01:22:10 PM PST 24
Finished Mar 07 01:22:24 PM PST 24
Peak memory 197084 kb
Host smart-dec9ac65-ecdf-49d8-9b4f-7dc9258d6c9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150985081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1150985081
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1683182431
Short name T315
Test name
Test status
Simulation time 86434157 ps
CPU time 0.69 seconds
Started Mar 07 01:22:12 PM PST 24
Finished Mar 07 01:22:13 PM PST 24
Peak memory 194784 kb
Host smart-4da42374-4740-4ace-b9c5-6048b82becd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683182431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1683182431
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1414226876
Short name T704
Test name
Test status
Simulation time 40941809 ps
CPU time 0.89 seconds
Started Mar 07 01:22:09 PM PST 24
Finished Mar 07 01:22:10 PM PST 24
Peak memory 196784 kb
Host smart-94117f8c-cb4e-459f-a3cb-f303455430e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414226876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1414226876
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3723723969
Short name T168
Test name
Test status
Simulation time 64667829 ps
CPU time 1.43 seconds
Started Mar 07 01:22:08 PM PST 24
Finished Mar 07 01:22:10 PM PST 24
Peak memory 196400 kb
Host smart-55625e0a-ca92-4c50-a040-0baf5c7c9894
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723723969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3723723969
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3294382884
Short name T213
Test name
Test status
Simulation time 101118849 ps
CPU time 1.76 seconds
Started Mar 07 01:22:07 PM PST 24
Finished Mar 07 01:22:10 PM PST 24
Peak memory 196788 kb
Host smart-6c333327-5eb4-4f41-9c8f-aad2335d6d60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294382884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3294382884
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.998878542
Short name T715
Test name
Test status
Simulation time 40591117 ps
CPU time 0.93 seconds
Started Mar 07 01:22:12 PM PST 24
Finished Mar 07 01:22:13 PM PST 24
Peak memory 196940 kb
Host smart-22213eff-80a1-4296-a8fe-2c73e5d757ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998878542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.998878542
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.1303191436
Short name T159
Test name
Test status
Simulation time 103539926 ps
CPU time 0.86 seconds
Started Mar 07 01:22:06 PM PST 24
Finished Mar 07 01:22:08 PM PST 24
Peak memory 196424 kb
Host smart-6d619222-446f-4485-ac87-68011b2718a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303191436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.1303191436
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2025681591
Short name T632
Test name
Test status
Simulation time 344734943 ps
CPU time 1.91 seconds
Started Mar 07 01:22:09 PM PST 24
Finished Mar 07 01:22:11 PM PST 24
Peak memory 198152 kb
Host smart-17100044-61c1-4c40-8146-c61df2b245af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025681591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2025681591
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3450414906
Short name T494
Test name
Test status
Simulation time 260547958 ps
CPU time 1.15 seconds
Started Mar 07 01:22:07 PM PST 24
Finished Mar 07 01:22:09 PM PST 24
Peak memory 195752 kb
Host smart-5168b689-2a6b-4e72-bd44-fd68d1a489ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450414906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3450414906
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.253732367
Short name T496
Test name
Test status
Simulation time 65960580 ps
CPU time 1.05 seconds
Started Mar 07 01:22:08 PM PST 24
Finished Mar 07 01:22:10 PM PST 24
Peak memory 195640 kb
Host smart-0b834151-e450-4a95-9df7-ee88e056a57c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253732367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.253732367
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.792651305
Short name T573
Test name
Test status
Simulation time 13778856772 ps
CPU time 200.94 seconds
Started Mar 07 01:22:08 PM PST 24
Finished Mar 07 01:25:29 PM PST 24
Peak memory 198348 kb
Host smart-49431b7c-739f-43cf-87ee-7baff5749627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792651305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.g
pio_stress_all.792651305
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.3245129923
Short name T483
Test name
Test status
Simulation time 267299114549 ps
CPU time 1268.34 seconds
Started Mar 07 01:22:13 PM PST 24
Finished Mar 07 01:43:21 PM PST 24
Peak memory 198448 kb
Host smart-a7a1ef5b-b1f7-4526-8d52-cad0d035cdb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3245129923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.3245129923
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2420784262
Short name T566
Test name
Test status
Simulation time 67037385 ps
CPU time 0.57 seconds
Started Mar 07 01:20:23 PM PST 24
Finished Mar 07 01:20:24 PM PST 24
Peak memory 194312 kb
Host smart-151f83d3-8354-4dd2-bb1c-b0bc82d77839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420784262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2420784262
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3076633679
Short name T524
Test name
Test status
Simulation time 161679667 ps
CPU time 0.97 seconds
Started Mar 07 01:20:16 PM PST 24
Finished Mar 07 01:20:17 PM PST 24
Peak memory 196808 kb
Host smart-1121d391-b249-47ff-8094-4da423af2314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076633679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3076633679
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3365957498
Short name T299
Test name
Test status
Simulation time 516979171 ps
CPU time 13.76 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:36 PM PST 24
Peak memory 197172 kb
Host smart-0e592936-e4b8-4634-ae17-b988b4b2a4ca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365957498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3365957498
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.2366632174
Short name T455
Test name
Test status
Simulation time 22182793 ps
CPU time 0.64 seconds
Started Mar 07 01:20:13 PM PST 24
Finished Mar 07 01:20:14 PM PST 24
Peak memory 194496 kb
Host smart-3ffb27ab-1813-4182-ad65-77cf09f5b414
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366632174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.2366632174
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1436278875
Short name T443
Test name
Test status
Simulation time 54576312 ps
CPU time 1.02 seconds
Started Mar 07 01:20:23 PM PST 24
Finished Mar 07 01:20:25 PM PST 24
Peak memory 195944 kb
Host smart-95e31718-c153-44ba-9414-d0d539ee0a24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436278875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1436278875
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3970231506
Short name T305
Test name
Test status
Simulation time 94853178 ps
CPU time 2.32 seconds
Started Mar 07 01:20:23 PM PST 24
Finished Mar 07 01:20:26 PM PST 24
Peak memory 198248 kb
Host smart-fcf6a55e-af4b-4918-bf60-e79b373126c1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970231506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3970231506
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.4091423137
Short name T293
Test name
Test status
Simulation time 973887996 ps
CPU time 3.29 seconds
Started Mar 07 01:20:14 PM PST 24
Finished Mar 07 01:20:18 PM PST 24
Peak memory 196664 kb
Host smart-6913170d-80b7-4c32-af05-6323832f0c48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091423137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
4091423137
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.9210072
Short name T625
Test name
Test status
Simulation time 67147550 ps
CPU time 1.35 seconds
Started Mar 07 01:20:16 PM PST 24
Finished Mar 07 01:20:19 PM PST 24
Peak memory 198208 kb
Host smart-0166d6e0-a628-4cd9-ac1c-1c885c937b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9210072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.9210072
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.4185510327
Short name T319
Test name
Test status
Simulation time 268454346 ps
CPU time 1.05 seconds
Started Mar 07 01:20:16 PM PST 24
Finished Mar 07 01:20:18 PM PST 24
Peak memory 196632 kb
Host smart-68834d69-d62c-4c47-be02-b2c0ae335975
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185510327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.4185510327
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1277851237
Short name T518
Test name
Test status
Simulation time 190642995 ps
CPU time 2.27 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:25 PM PST 24
Peak memory 198148 kb
Host smart-9c6dbe2b-e0bf-4b88-ba0b-0c253ff26485
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277851237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1277851237
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1570078951
Short name T224
Test name
Test status
Simulation time 24954506 ps
CPU time 0.92 seconds
Started Mar 07 01:20:13 PM PST 24
Finished Mar 07 01:20:14 PM PST 24
Peak memory 196252 kb
Host smart-39d3a0df-ee03-4083-8b75-b5b59165f5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570078951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1570078951
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.4223066694
Short name T401
Test name
Test status
Simulation time 76183615 ps
CPU time 1.33 seconds
Started Mar 07 01:20:12 PM PST 24
Finished Mar 07 01:20:14 PM PST 24
Peak memory 196656 kb
Host smart-c0e03385-b854-4520-869b-256cdcb12705
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223066694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.4223066694
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.291196192
Short name T595
Test name
Test status
Simulation time 16947584337 ps
CPU time 239.65 seconds
Started Mar 07 01:20:23 PM PST 24
Finished Mar 07 01:24:23 PM PST 24
Peak memory 198344 kb
Host smart-797b8bd2-8fc3-4f99-a7c3-fe4fff23b099
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291196192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.291196192
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.852346351
Short name T160
Test name
Test status
Simulation time 27545667 ps
CPU time 0.62 seconds
Started Mar 07 01:20:16 PM PST 24
Finished Mar 07 01:20:17 PM PST 24
Peak memory 194992 kb
Host smart-b6168fb7-4fd1-4402-83be-b5623189b65d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852346351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.852346351
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3194338876
Short name T695
Test name
Test status
Simulation time 51978074 ps
CPU time 0.84 seconds
Started Mar 07 01:20:17 PM PST 24
Finished Mar 07 01:20:19 PM PST 24
Peak memory 197056 kb
Host smart-e228a391-ddbd-4edf-abd1-f6f57ceebe5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194338876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3194338876
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3713045505
Short name T232
Test name
Test status
Simulation time 255044716 ps
CPU time 9.39 seconds
Started Mar 07 01:20:16 PM PST 24
Finished Mar 07 01:20:27 PM PST 24
Peak memory 196752 kb
Host smart-68454e9f-1a57-4777-a82d-125f91e866db
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713045505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3713045505
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.925458252
Short name T258
Test name
Test status
Simulation time 70348610 ps
CPU time 0.95 seconds
Started Mar 07 01:20:11 PM PST 24
Finished Mar 07 01:20:12 PM PST 24
Peak memory 197956 kb
Host smart-9f461afd-bd94-4eca-8e1e-43e43e0d6938
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925458252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.925458252
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1252181172
Short name T196
Test name
Test status
Simulation time 168726216 ps
CPU time 1.56 seconds
Started Mar 07 01:20:14 PM PST 24
Finished Mar 07 01:20:16 PM PST 24
Peak memory 198120 kb
Host smart-0209890e-d3b2-4235-a4ae-ac9d1cb1f592
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252181172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1252181172
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.2558842518
Short name T411
Test name
Test status
Simulation time 370802059 ps
CPU time 2.59 seconds
Started Mar 07 01:20:17 PM PST 24
Finished Mar 07 01:20:21 PM PST 24
Peak memory 198192 kb
Host smart-e5c5d8ca-7afd-430b-881a-e80a852df5f4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558842518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.2558842518
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3045135654
Short name T127
Test name
Test status
Simulation time 399945323 ps
CPU time 3.21 seconds
Started Mar 07 01:20:17 PM PST 24
Finished Mar 07 01:20:21 PM PST 24
Peak memory 198188 kb
Host smart-1c907f8d-71b2-4342-b682-be50edc86d95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045135654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3045135654
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.2475917901
Short name T525
Test name
Test status
Simulation time 65393388 ps
CPU time 1.24 seconds
Started Mar 07 01:20:15 PM PST 24
Finished Mar 07 01:20:17 PM PST 24
Peak memory 198168 kb
Host smart-51759076-ddd6-4544-90eb-a1e161e10c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475917901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.2475917901
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.2821191131
Short name T223
Test name
Test status
Simulation time 102667409 ps
CPU time 0.71 seconds
Started Mar 07 01:20:14 PM PST 24
Finished Mar 07 01:20:15 PM PST 24
Peak memory 194208 kb
Host smart-3c7f6298-7586-413d-a17a-e06e18fa024b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821191131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.2821191131
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.687893947
Short name T190
Test name
Test status
Simulation time 25556044 ps
CPU time 1.23 seconds
Started Mar 07 01:20:17 PM PST 24
Finished Mar 07 01:20:20 PM PST 24
Peak memory 198120 kb
Host smart-3dbd7566-557b-46a8-a6c9-f7ec75a0c477
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687893947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.687893947
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1532849758
Short name T684
Test name
Test status
Simulation time 55465232 ps
CPU time 1.17 seconds
Started Mar 07 01:20:12 PM PST 24
Finished Mar 07 01:20:14 PM PST 24
Peak memory 196332 kb
Host smart-cb46d1c0-b24b-45fd-b14a-8c5ff27ac38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532849758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1532849758
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.608997213
Short name T123
Test name
Test status
Simulation time 79427426 ps
CPU time 0.93 seconds
Started Mar 07 01:20:15 PM PST 24
Finished Mar 07 01:20:16 PM PST 24
Peak memory 196316 kb
Host smart-fcf8172e-e07a-4422-81a8-fbf663961b79
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608997213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.608997213
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.3918330933
Short name T594
Test name
Test status
Simulation time 19265106057 ps
CPU time 124.09 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:22:26 PM PST 24
Peak memory 197856 kb
Host smart-be171348-6d01-478b-97fc-ef276f09863d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918330933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.3918330933
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3791121232
Short name T500
Test name
Test status
Simulation time 23679275 ps
CPU time 0.57 seconds
Started Mar 07 01:20:19 PM PST 24
Finished Mar 07 01:20:20 PM PST 24
Peak memory 192824 kb
Host smart-4b2db374-ee5d-4f68-b7ad-9cbd040a09ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791121232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3791121232
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.129918995
Short name T270
Test name
Test status
Simulation time 26537973 ps
CPU time 0.89 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:23 PM PST 24
Peak memory 197268 kb
Host smart-095b8610-ec85-433c-b73b-c2c1461d9745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129918995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.129918995
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1583132286
Short name T385
Test name
Test status
Simulation time 1753522269 ps
CPU time 21.63 seconds
Started Mar 07 01:20:20 PM PST 24
Finished Mar 07 01:20:43 PM PST 24
Peak memory 197060 kb
Host smart-6e7a7f76-bcd3-487a-acb3-5a9fd1618f3b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583132286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1583132286
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.2579771690
Short name T186
Test name
Test status
Simulation time 26402887 ps
CPU time 0.67 seconds
Started Mar 07 01:20:20 PM PST 24
Finished Mar 07 01:20:22 PM PST 24
Peak memory 194596 kb
Host smart-baabcbec-3ed1-4f35-9a76-7d6af71762c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579771690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.2579771690
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1173858060
Short name T593
Test name
Test status
Simulation time 154050742 ps
CPU time 0.94 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:23 PM PST 24
Peak memory 197020 kb
Host smart-8228cd2b-0292-45db-b41f-e8ae82026e11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173858060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1173858060
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3399669674
Short name T545
Test name
Test status
Simulation time 66613804 ps
CPU time 2.65 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:24 PM PST 24
Peak memory 198244 kb
Host smart-d5f012c1-507b-43d9-b860-333c4092486a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399669674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3399669674
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2227696494
Short name T505
Test name
Test status
Simulation time 109102046 ps
CPU time 3.23 seconds
Started Mar 07 01:20:18 PM PST 24
Finished Mar 07 01:20:23 PM PST 24
Peak memory 198236 kb
Host smart-9b02f175-bdba-4a2b-86bf-f95ba823333d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227696494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2227696494
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.1160524167
Short name T570
Test name
Test status
Simulation time 57616950 ps
CPU time 1.15 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:23 PM PST 24
Peak memory 195796 kb
Host smart-39952681-5632-4f4c-b952-6ecbbf96742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160524167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.1160524167
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.133807627
Short name T116
Test name
Test status
Simulation time 128149128 ps
CPU time 0.92 seconds
Started Mar 07 01:20:17 PM PST 24
Finished Mar 07 01:20:19 PM PST 24
Peak memory 196064 kb
Host smart-ecb4bbea-3441-4340-bdc2-642f51807f59
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133807627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup_
pulldown.133807627
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1755625121
Short name T372
Test name
Test status
Simulation time 474209711 ps
CPU time 5.85 seconds
Started Mar 07 01:20:21 PM PST 24
Finished Mar 07 01:20:27 PM PST 24
Peak memory 198140 kb
Host smart-de4f70b1-7b2b-4b17-86a8-398b214315f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755625121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1755625121
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3597282627
Short name T403
Test name
Test status
Simulation time 170859031 ps
CPU time 1.42 seconds
Started Mar 07 01:20:17 PM PST 24
Finished Mar 07 01:20:20 PM PST 24
Peak memory 198120 kb
Host smart-7e7733d2-60ca-4e48-82f5-f31534620d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597282627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3597282627
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2766285235
Short name T207
Test name
Test status
Simulation time 54659529 ps
CPU time 0.96 seconds
Started Mar 07 01:20:12 PM PST 24
Finished Mar 07 01:20:13 PM PST 24
Peak memory 195960 kb
Host smart-205de735-e092-453d-8452-9ed3b5b50bd1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766285235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2766285235
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1486712472
Short name T616
Test name
Test status
Simulation time 24601769057 ps
CPU time 162.98 seconds
Started Mar 07 01:20:20 PM PST 24
Finished Mar 07 01:23:04 PM PST 24
Peak memory 198300 kb
Host smart-5f211ea4-2db4-48d1-ad85-87fb5d4e8ec3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486712472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1486712472
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2940815505
Short name T17
Test name
Test status
Simulation time 14025255 ps
CPU time 0.59 seconds
Started Mar 07 01:20:21 PM PST 24
Finished Mar 07 01:20:22 PM PST 24
Peak memory 194140 kb
Host smart-702c1e0a-4442-4309-a6c8-98e32094eaee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940815505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2940815505
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.54025695
Short name T421
Test name
Test status
Simulation time 78263129 ps
CPU time 0.75 seconds
Started Mar 07 01:20:19 PM PST 24
Finished Mar 07 01:20:21 PM PST 24
Peak memory 195340 kb
Host smart-5b988443-1873-467a-abe1-af39fc8e9bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54025695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.54025695
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2140783100
Short name T328
Test name
Test status
Simulation time 1348108879 ps
CPU time 11.62 seconds
Started Mar 07 01:20:27 PM PST 24
Finished Mar 07 01:20:39 PM PST 24
Peak memory 195672 kb
Host smart-54badbbc-d1b1-4ce2-8edd-a435cc00c654
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140783100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2140783100
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1998643143
Short name T460
Test name
Test status
Simulation time 108691709 ps
CPU time 0.75 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:23 PM PST 24
Peak memory 195492 kb
Host smart-27ad5ce5-d7a7-4a7b-b9ae-033a136e1564
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998643143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1998643143
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.1992184103
Short name T325
Test name
Test status
Simulation time 126417759 ps
CPU time 1.23 seconds
Started Mar 07 01:20:18 PM PST 24
Finished Mar 07 01:20:20 PM PST 24
Peak memory 196292 kb
Host smart-ae14e98f-5c11-4801-ae08-4d0691efd6da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992184103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.1992184103
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.4102864436
Short name T693
Test name
Test status
Simulation time 105392248 ps
CPU time 2.26 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:25 PM PST 24
Peak memory 196508 kb
Host smart-c385b5f3-8d38-45c2-a910-623ef45f31e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102864436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.4102864436
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3834809317
Short name T145
Test name
Test status
Simulation time 214017746 ps
CPU time 2.15 seconds
Started Mar 07 01:20:21 PM PST 24
Finished Mar 07 01:20:23 PM PST 24
Peak memory 195872 kb
Host smart-ec784c0d-d804-42ad-b007-6f128975414f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834809317 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3834809317
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.4041696011
Short name T548
Test name
Test status
Simulation time 66319902 ps
CPU time 1.21 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:24 PM PST 24
Peak memory 196732 kb
Host smart-7e16b585-fecd-4cf8-b836-4a3cd9de5096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041696011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.4041696011
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2461169209
Short name T603
Test name
Test status
Simulation time 85029901 ps
CPU time 0.75 seconds
Started Mar 07 01:20:21 PM PST 24
Finished Mar 07 01:20:22 PM PST 24
Peak memory 195500 kb
Host smart-530c5444-54dc-44ad-9777-9345302ab8ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461169209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2461169209
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_smoke.1621744576
Short name T720
Test name
Test status
Simulation time 597572519 ps
CPU time 1.09 seconds
Started Mar 07 01:20:18 PM PST 24
Finished Mar 07 01:20:20 PM PST 24
Peak memory 195724 kb
Host smart-8ca42006-e2dc-4fcf-85db-ad582a124e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621744576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.1621744576
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2581984426
Short name T475
Test name
Test status
Simulation time 42551460 ps
CPU time 0.8 seconds
Started Mar 07 01:20:18 PM PST 24
Finished Mar 07 01:20:19 PM PST 24
Peak memory 195404 kb
Host smart-b8a42bdd-0ce0-402a-b188-e3c791cd4103
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581984426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2581984426
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.108194928
Short name T198
Test name
Test status
Simulation time 8521350973 ps
CPU time 122.83 seconds
Started Mar 07 01:20:21 PM PST 24
Finished Mar 07 01:22:24 PM PST 24
Peak memory 198360 kb
Host smart-0aaf9be5-fa67-433e-8a2d-a063fd9951e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108194928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.108194928
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3751580716
Short name T558
Test name
Test status
Simulation time 186876100982 ps
CPU time 1638.56 seconds
Started Mar 07 01:20:20 PM PST 24
Finished Mar 07 01:47:40 PM PST 24
Peak memory 198468 kb
Host smart-0579269b-d3e1-4cf4-ad9b-3578a5dd62e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3751580716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3751580716
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3950899543
Short name T43
Test name
Test status
Simulation time 18913417 ps
CPU time 0.55 seconds
Started Mar 07 01:20:26 PM PST 24
Finished Mar 07 01:20:26 PM PST 24
Peak memory 194084 kb
Host smart-8de23a24-e9dc-4c70-bcdd-16698d0364d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950899543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3950899543
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1843477531
Short name T165
Test name
Test status
Simulation time 25800594 ps
CPU time 0.7 seconds
Started Mar 07 01:20:23 PM PST 24
Finished Mar 07 01:20:24 PM PST 24
Peak memory 193392 kb
Host smart-7e61454c-7eaa-4b8d-926d-c4733513a2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843477531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1843477531
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.4015791100
Short name T302
Test name
Test status
Simulation time 432858558 ps
CPU time 12.25 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:34 PM PST 24
Peak memory 197004 kb
Host smart-6f081e24-7d44-4fd9-b691-126aecd3936b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015791100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.4015791100
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.2121942279
Short name T402
Test name
Test status
Simulation time 104552810 ps
CPU time 1.12 seconds
Started Mar 07 01:20:23 PM PST 24
Finished Mar 07 01:20:25 PM PST 24
Peak memory 196772 kb
Host smart-1b9f0ab8-6ba7-4204-a59a-f6a1366120dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121942279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.2121942279
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1208540837
Short name T512
Test name
Test status
Simulation time 106777014 ps
CPU time 0.82 seconds
Started Mar 07 01:20:21 PM PST 24
Finished Mar 07 01:20:22 PM PST 24
Peak memory 196432 kb
Host smart-03ddf60e-3c01-4993-805e-15aa7853ab32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208540837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1208540837
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1362625157
Short name T257
Test name
Test status
Simulation time 313863010 ps
CPU time 3.95 seconds
Started Mar 07 01:20:25 PM PST 24
Finished Mar 07 01:20:29 PM PST 24
Peak memory 198176 kb
Host smart-92510bdd-c242-43a5-a9e7-0231ab29fa08
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362625157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1362625157
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3816137062
Short name T471
Test name
Test status
Simulation time 403420849 ps
CPU time 2.29 seconds
Started Mar 07 01:20:23 PM PST 24
Finished Mar 07 01:20:25 PM PST 24
Peak memory 197616 kb
Host smart-6e219076-8d3c-45fc-96ef-d0274b0a0a09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816137062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3816137062
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1765423985
Short name T272
Test name
Test status
Simulation time 281746092 ps
CPU time 1.39 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:23 PM PST 24
Peak memory 197176 kb
Host smart-8e09df29-c9e7-462e-b5d9-13ce0797b295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765423985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1765423985
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2023815493
Short name T166
Test name
Test status
Simulation time 161909282 ps
CPU time 0.96 seconds
Started Mar 07 01:20:23 PM PST 24
Finished Mar 07 01:20:25 PM PST 24
Peak memory 195032 kb
Host smart-5c670e2e-ba56-4aba-84f4-a1ed9a4dfd61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023815493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2023815493
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1482449855
Short name T464
Test name
Test status
Simulation time 1359660672 ps
CPU time 4.64 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:27 PM PST 24
Peak memory 198188 kb
Host smart-060b2744-9870-4067-b270-d033c5e250b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482449855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1482449855
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.4115637166
Short name T490
Test name
Test status
Simulation time 95366621 ps
CPU time 0.94 seconds
Started Mar 07 01:20:22 PM PST 24
Finished Mar 07 01:20:23 PM PST 24
Peak memory 196504 kb
Host smart-1ab1fc5a-2545-45ef-bdb0-639355de8e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115637166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4115637166
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3301487953
Short name T578
Test name
Test status
Simulation time 55867576 ps
CPU time 1.12 seconds
Started Mar 07 01:20:24 PM PST 24
Finished Mar 07 01:20:25 PM PST 24
Peak memory 195688 kb
Host smart-4c8ff4cd-f752-4955-8ac5-873a4b392897
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301487953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3301487953
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2422216667
Short name T501
Test name
Test status
Simulation time 24145978799 ps
CPU time 168.96 seconds
Started Mar 07 01:20:34 PM PST 24
Finished Mar 07 01:23:24 PM PST 24
Peak memory 192124 kb
Host smart-cce1034e-b16d-478a-9a31-c9ecb8b64294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422216667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2422216667
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.4189555282
Short name T63
Test name
Test status
Simulation time 23042365924 ps
CPU time 557.68 seconds
Started Mar 07 01:20:29 PM PST 24
Finished Mar 07 01:29:47 PM PST 24
Peak memory 198504 kb
Host smart-bb548a2f-0996-4cab-af7e-dcb578430ffc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4189555282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.4189555282
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.1489009681
Short name T869
Test name
Test status
Simulation time 33550790 ps
CPU time 1 seconds
Started Mar 07 12:56:52 PM PST 24
Finished Mar 07 12:56:53 PM PST 24
Peak memory 198124 kb
Host smart-f676839b-d16b-4d36-b7ba-b6db11ab6f24
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1489009681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.1489009681
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2594156465
Short name T907
Test name
Test status
Simulation time 92507617 ps
CPU time 0.93 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:43 PM PST 24
Peak memory 196788 kb
Host smart-0f424ce1-bc2f-451e-bc0b-6e721eda3bff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594156465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2594156465
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1525562005
Short name T896
Test name
Test status
Simulation time 49614336 ps
CPU time 1.37 seconds
Started Mar 07 12:56:40 PM PST 24
Finished Mar 07 12:56:42 PM PST 24
Peak memory 196964 kb
Host smart-577cc219-078c-4126-93b6-52475562058e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1525562005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1525562005
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.234887249
Short name T912
Test name
Test status
Simulation time 219291300 ps
CPU time 0.91 seconds
Started Mar 07 12:56:55 PM PST 24
Finished Mar 07 12:56:56 PM PST 24
Peak memory 197172 kb
Host smart-897b4911-a1ed-45a7-bad6-c286342b88d1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234887249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.234887249
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2035661273
Short name T881
Test name
Test status
Simulation time 71919374 ps
CPU time 1.23 seconds
Started Mar 07 12:57:03 PM PST 24
Finished Mar 07 12:57:05 PM PST 24
Peak memory 196692 kb
Host smart-d192d3ca-67c8-4d5c-a51f-e3e99c203433
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2035661273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2035661273
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1648561111
Short name T861
Test name
Test status
Simulation time 28611281 ps
CPU time 0.83 seconds
Started Mar 07 12:57:00 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 196244 kb
Host smart-85e9c26a-418a-47fb-8db6-0253ea3e5e23
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648561111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1648561111
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1661825288
Short name T888
Test name
Test status
Simulation time 83841898 ps
CPU time 1.07 seconds
Started Mar 07 12:56:41 PM PST 24
Finished Mar 07 12:56:42 PM PST 24
Peak memory 196712 kb
Host smart-1433b59f-8d6a-4b5e-91c8-c92a650fea89
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1661825288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1661825288
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3856978679
Short name T917
Test name
Test status
Simulation time 60786938 ps
CPU time 1.02 seconds
Started Mar 07 12:56:40 PM PST 24
Finished Mar 07 12:56:41 PM PST 24
Peak memory 198052 kb
Host smart-62c271c2-4e3c-41e5-bc8b-aa33db6be816
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856978679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3856978679
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.2639452953
Short name T901
Test name
Test status
Simulation time 75682635 ps
CPU time 1.25 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:00 PM PST 24
Peak memory 197024 kb
Host smart-a6de77fb-5787-479f-922a-4897854e4b71
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2639452953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.2639452953
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3832030103
Short name T889
Test name
Test status
Simulation time 49272784 ps
CPU time 1.05 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:43 PM PST 24
Peak memory 196608 kb
Host smart-5b34b656-31ea-4270-bb88-183206d47d61
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832030103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3832030103
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.319111395
Short name T934
Test name
Test status
Simulation time 140307683 ps
CPU time 1.02 seconds
Started Mar 07 12:56:58 PM PST 24
Finished Mar 07 12:56:59 PM PST 24
Peak memory 196516 kb
Host smart-217c4bd1-1f50-40c1-9ba1-34ae6bece188
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=319111395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.319111395
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2083720287
Short name T860
Test name
Test status
Simulation time 153255283 ps
CPU time 1.49 seconds
Started Mar 07 12:57:01 PM PST 24
Finished Mar 07 12:57:03 PM PST 24
Peak memory 198172 kb
Host smart-0bbb4dd7-60db-4850-81a0-6a3cc555bbb6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083720287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2083720287
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.916188127
Short name T899
Test name
Test status
Simulation time 53212106 ps
CPU time 1.42 seconds
Started Mar 07 12:56:45 PM PST 24
Finished Mar 07 12:56:47 PM PST 24
Peak memory 196940 kb
Host smart-4553d54b-3b45-4d30-8b14-e624d6ff9d84
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=916188127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.916188127
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2913513146
Short name T897
Test name
Test status
Simulation time 383231261 ps
CPU time 1.42 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 195816 kb
Host smart-c14a00d0-ac9e-4afe-8e7c-30ea7d123e77
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913513146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2913513146
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.510988734
Short name T859
Test name
Test status
Simulation time 56923584 ps
CPU time 1.13 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 196676 kb
Host smart-cdd844fc-ebb8-452f-af43-5d153abea208
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=510988734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.510988734
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.61226092
Short name T922
Test name
Test status
Simulation time 69108250 ps
CPU time 0.83 seconds
Started Mar 07 12:56:53 PM PST 24
Finished Mar 07 12:56:54 PM PST 24
Peak memory 196568 kb
Host smart-5f36fcad-8aad-4acd-98c1-a659847c82f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61226092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.61226092
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3399638430
Short name T930
Test name
Test status
Simulation time 243386725 ps
CPU time 1.33 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 196992 kb
Host smart-efbe1d5c-c002-4f79-8e06-42387cf91b2f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3399638430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3399638430
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4240210426
Short name T872
Test name
Test status
Simulation time 242047540 ps
CPU time 1.15 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 196908 kb
Host smart-5b942ee7-a452-415a-aa60-f745da32b4c8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240210426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4240210426
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.308652065
Short name T921
Test name
Test status
Simulation time 171738552 ps
CPU time 1.31 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 197028 kb
Host smart-a07f4880-a242-4e26-8d73-4af56c70bf81
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=308652065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.308652065
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1932030345
Short name T894
Test name
Test status
Simulation time 69373293 ps
CPU time 1.14 seconds
Started Mar 07 12:57:15 PM PST 24
Finished Mar 07 12:57:17 PM PST 24
Peak memory 196640 kb
Host smart-b41cbb1e-1747-43cf-936d-c7751848eab8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932030345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1932030345
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.412653875
Short name T852
Test name
Test status
Simulation time 78047368 ps
CPU time 0.88 seconds
Started Mar 07 12:56:52 PM PST 24
Finished Mar 07 12:56:58 PM PST 24
Peak memory 196432 kb
Host smart-7a2d589d-a388-423e-8f57-3260469cfe9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=412653875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.412653875
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.233175201
Short name T909
Test name
Test status
Simulation time 230890844 ps
CPU time 1.17 seconds
Started Mar 07 12:56:54 PM PST 24
Finished Mar 07 12:56:55 PM PST 24
Peak memory 196784 kb
Host smart-f7286bfb-b758-4aa8-afd5-b41cf9c5ccb2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233175201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.233175201
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3408100960
Short name T874
Test name
Test status
Simulation time 88964548 ps
CPU time 0.91 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:43 PM PST 24
Peak memory 195560 kb
Host smart-8a35a8e4-b09b-41c0-839d-e800202b6976
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3408100960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3408100960
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.997989399
Short name T871
Test name
Test status
Simulation time 175126336 ps
CPU time 0.96 seconds
Started Mar 07 12:57:02 PM PST 24
Finished Mar 07 12:57:03 PM PST 24
Peak memory 195388 kb
Host smart-e6dd26b4-2a21-41fd-b7c0-caecbcce90da
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997989399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.997989399
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3561624825
Short name T895
Test name
Test status
Simulation time 201730576 ps
CPU time 1.01 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:00 PM PST 24
Peak memory 196028 kb
Host smart-6f8f2529-f227-42f4-b48f-4eb4316ad29e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3561624825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3561624825
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2498188199
Short name T858
Test name
Test status
Simulation time 47533102 ps
CPU time 0.73 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 195492 kb
Host smart-816dfc62-ebd4-4c83-b06f-44ba0e40bcf3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498188199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2498188199
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.875350509
Short name T946
Test name
Test status
Simulation time 110380116 ps
CPU time 1.13 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:50 PM PST 24
Peak memory 198172 kb
Host smart-b5895905-41cf-428c-ae64-7fc07d27c208
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=875350509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.875350509
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1118512964
Short name T925
Test name
Test status
Simulation time 395035943 ps
CPU time 1.47 seconds
Started Mar 07 12:56:44 PM PST 24
Finished Mar 07 12:56:46 PM PST 24
Peak memory 196896 kb
Host smart-5ca624b0-ff97-494d-b753-76b5ad21d5b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118512964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1118512964
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2701731107
Short name T865
Test name
Test status
Simulation time 437254579 ps
CPU time 1.37 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 197036 kb
Host smart-bc22a0ef-8436-41d3-b5d9-984feefda24b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2701731107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2701731107
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3049205283
Short name T918
Test name
Test status
Simulation time 39882884 ps
CPU time 1.22 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 196760 kb
Host smart-d776336e-f8ce-4e4a-8a01-35c711aa014e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049205283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3049205283
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.151526536
Short name T945
Test name
Test status
Simulation time 102192656 ps
CPU time 0.98 seconds
Started Mar 07 12:56:38 PM PST 24
Finished Mar 07 12:56:40 PM PST 24
Peak memory 196628 kb
Host smart-040e657e-9cef-464f-be0e-1f0eca7ac1ef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=151526536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.151526536
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4057565196
Short name T863
Test name
Test status
Simulation time 223120274 ps
CPU time 1.17 seconds
Started Mar 07 12:57:14 PM PST 24
Finished Mar 07 12:57:16 PM PST 24
Peak memory 198012 kb
Host smart-1afde36e-586f-45a1-b48b-ccae84befa82
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057565196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4057565196
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1320314566
Short name T914
Test name
Test status
Simulation time 21826646 ps
CPU time 0.77 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 196184 kb
Host smart-025d1947-4aae-42a4-8d6c-b35c1e1fa868
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1320314566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1320314566
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2744766177
Short name T938
Test name
Test status
Simulation time 110217166 ps
CPU time 1.09 seconds
Started Mar 07 12:56:44 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 196076 kb
Host smart-46dfd333-45d4-43db-8520-ec3061d1796a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744766177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2744766177
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2876909313
Short name T883
Test name
Test status
Simulation time 224099695 ps
CPU time 1.12 seconds
Started Mar 07 12:56:47 PM PST 24
Finished Mar 07 12:56:48 PM PST 24
Peak memory 197284 kb
Host smart-92f7d833-7f80-4d90-b926-a0c7220165b3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2876909313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2876909313
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.818198190
Short name T935
Test name
Test status
Simulation time 103441842 ps
CPU time 1.19 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:09 PM PST 24
Peak memory 196752 kb
Host smart-c92a65ab-b6ee-49a1-a5b6-c7b913e750b3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818198190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.818198190
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1099332185
Short name T853
Test name
Test status
Simulation time 31003367 ps
CPU time 0.93 seconds
Started Mar 07 12:56:39 PM PST 24
Finished Mar 07 12:56:40 PM PST 24
Peak memory 196140 kb
Host smart-08f127a6-806d-4504-a9aa-7cbcd164ad22
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1099332185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1099332185
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2983244753
Short name T915
Test name
Test status
Simulation time 39088159 ps
CPU time 0.87 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:00 PM PST 24
Peak memory 196208 kb
Host smart-98e23746-56d2-4b6e-b45c-75ee4cf14403
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983244753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2983244753
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.477631782
Short name T898
Test name
Test status
Simulation time 125105843 ps
CPU time 1.22 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 198144 kb
Host smart-7ed6ee85-3d26-4151-b1c5-6dd1cf075b45
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=477631782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.477631782
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2988276830
Short name T939
Test name
Test status
Simulation time 29509178 ps
CPU time 0.79 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:00 PM PST 24
Peak memory 195544 kb
Host smart-a566bb1c-740b-4946-a4bb-18285eb0cc7d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988276830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2988276830
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.2037156121
Short name T932
Test name
Test status
Simulation time 93328596 ps
CPU time 0.81 seconds
Started Mar 07 12:56:44 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 195448 kb
Host smart-f685ab05-572c-4fd2-85e6-c7dcae5fa843
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2037156121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.2037156121
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.93855331
Short name T908
Test name
Test status
Simulation time 179928379 ps
CPU time 1.31 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 196508 kb
Host smart-37b48b75-5e35-4a13-b932-e54384ce0c68
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93855331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.93855331
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3895864457
Short name T913
Test name
Test status
Simulation time 57856142 ps
CPU time 1.03 seconds
Started Mar 07 12:56:49 PM PST 24
Finished Mar 07 12:56:51 PM PST 24
Peak memory 197464 kb
Host smart-c3d128a9-ca7d-4989-8ba9-66eb00628e14
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3895864457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3895864457
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2379698763
Short name T879
Test name
Test status
Simulation time 921022633 ps
CPU time 0.97 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 196608 kb
Host smart-799fefd1-e99e-49b7-ac8f-078f81489a12
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379698763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2379698763
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.293663412
Short name T905
Test name
Test status
Simulation time 56772395 ps
CPU time 1.16 seconds
Started Mar 07 12:56:40 PM PST 24
Finished Mar 07 12:56:41 PM PST 24
Peak memory 195972 kb
Host smart-9a920343-9a71-4934-a7bb-19e15591420f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=293663412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.293663412
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2040121181
Short name T880
Test name
Test status
Simulation time 154504564 ps
CPU time 1.25 seconds
Started Mar 07 12:56:53 PM PST 24
Finished Mar 07 12:56:55 PM PST 24
Peak memory 198060 kb
Host smart-54446ea5-1622-48d7-9a8c-149aef0902d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040121181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2040121181
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2164579054
Short name T919
Test name
Test status
Simulation time 129080311 ps
CPU time 1.36 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 196528 kb
Host smart-ee9c5d9b-0fee-460a-9982-05aec797b76e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2164579054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2164579054
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3713333639
Short name T867
Test name
Test status
Simulation time 36324335 ps
CPU time 1.15 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:11 PM PST 24
Peak memory 196760 kb
Host smart-27c6a894-f25b-4f12-a151-d6aa5d59e280
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713333639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3713333639
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3997507081
Short name T876
Test name
Test status
Simulation time 55667489 ps
CPU time 1.08 seconds
Started Mar 07 12:57:07 PM PST 24
Finished Mar 07 12:57:10 PM PST 24
Peak memory 196824 kb
Host smart-a7192346-c449-4c03-a6c2-758c96b286b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3997507081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3997507081
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3080267250
Short name T893
Test name
Test status
Simulation time 127238612 ps
CPU time 1 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 196636 kb
Host smart-4b5a11a9-ae95-4b59-8dbf-fa1e42c2eaee
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080267250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3080267250
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.2367905299
Short name T857
Test name
Test status
Simulation time 493407753 ps
CPU time 1.15 seconds
Started Mar 07 12:56:56 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 196796 kb
Host smart-c387737b-e4c4-49d8-ba2f-cbe0f4813362
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2367905299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.2367905299
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2075656543
Short name T848
Test name
Test status
Simulation time 90862808 ps
CPU time 0.95 seconds
Started Mar 07 12:57:13 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 196656 kb
Host smart-523e55af-80a5-45fb-93bd-bfe967bc8610
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075656543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2075656543
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4215374082
Short name T944
Test name
Test status
Simulation time 178912123 ps
CPU time 1.38 seconds
Started Mar 07 12:57:13 PM PST 24
Finished Mar 07 12:57:16 PM PST 24
Peak memory 198156 kb
Host smart-382dcd43-0203-43cf-bc3a-fdf440a4f07d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4215374082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.4215374082
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3062281932
Short name T931
Test name
Test status
Simulation time 52897579 ps
CPU time 1.42 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 196708 kb
Host smart-97d65992-88fd-4e49-ab60-ce2241d7bd4d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062281932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3062281932
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1968726806
Short name T891
Test name
Test status
Simulation time 119777726 ps
CPU time 0.97 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 195940 kb
Host smart-09931dd6-6077-4cfe-81fd-39832b4bd35f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1968726806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1968726806
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.31412138
Short name T862
Test name
Test status
Simulation time 348666777 ps
CPU time 1.49 seconds
Started Mar 07 12:57:00 PM PST 24
Finished Mar 07 12:57:02 PM PST 24
Peak memory 198152 kb
Host smart-43295c13-13c3-4fe3-bb34-319d745cd9b0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31412138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.31412138
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3163549615
Short name T923
Test name
Test status
Simulation time 160733794 ps
CPU time 1.28 seconds
Started Mar 07 12:56:47 PM PST 24
Finished Mar 07 12:56:49 PM PST 24
Peak memory 196960 kb
Host smart-026bf504-bb94-4c2d-b03b-38649ec165bd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3163549615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3163549615
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1720109385
Short name T940
Test name
Test status
Simulation time 33811532 ps
CPU time 0.98 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:00 PM PST 24
Peak memory 196056 kb
Host smart-4c5c32bc-c5f5-4af1-ac6f-e7286f373ce2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720109385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1720109385
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3158250068
Short name T890
Test name
Test status
Simulation time 107778326 ps
CPU time 1.42 seconds
Started Mar 07 12:57:13 PM PST 24
Finished Mar 07 12:57:15 PM PST 24
Peak memory 196724 kb
Host smart-af5f0163-09d9-4fb4-8cef-d2a7e384af90
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3158250068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3158250068
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.31773416
Short name T851
Test name
Test status
Simulation time 42158468 ps
CPU time 0.93 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 196620 kb
Host smart-7a3cf51a-0b53-4a4d-be39-7562538ded7f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31773416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.31773416
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.906691883
Short name T866
Test name
Test status
Simulation time 381971932 ps
CPU time 1.27 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:00 PM PST 24
Peak memory 198156 kb
Host smart-f8647354-a980-4899-91f9-33eb5e6151dd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=906691883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.906691883
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2845836806
Short name T937
Test name
Test status
Simulation time 327988729 ps
CPU time 1.25 seconds
Started Mar 07 12:57:05 PM PST 24
Finished Mar 07 12:57:08 PM PST 24
Peak memory 196700 kb
Host smart-0c92b1a4-04ba-401f-8be9-7f7b4f032c75
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845836806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2845836806
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.789399079
Short name T854
Test name
Test status
Simulation time 128987021 ps
CPU time 0.84 seconds
Started Mar 07 12:57:05 PM PST 24
Finished Mar 07 12:57:08 PM PST 24
Peak memory 195612 kb
Host smart-8e75030f-7a63-44b0-b53e-ccfc74877278
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=789399079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.789399079
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3527338557
Short name T903
Test name
Test status
Simulation time 295917343 ps
CPU time 1.35 seconds
Started Mar 07 12:56:53 PM PST 24
Finished Mar 07 12:56:55 PM PST 24
Peak memory 198200 kb
Host smart-d1321712-4a08-445b-897c-c318832f027f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527338557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3527338557
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2532957638
Short name T911
Test name
Test status
Simulation time 78865158 ps
CPU time 1.32 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:44 PM PST 24
Peak memory 197036 kb
Host smart-c49c7860-56a6-4701-956f-f0b85772e380
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2532957638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2532957638
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3918674986
Short name T878
Test name
Test status
Simulation time 167402038 ps
CPU time 1.22 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:00 PM PST 24
Peak memory 196724 kb
Host smart-bc787621-60f8-4c40-9814-8572907dab36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918674986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3918674986
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.2792206342
Short name T926
Test name
Test status
Simulation time 306062180 ps
CPU time 1.37 seconds
Started Mar 07 12:56:44 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 198128 kb
Host smart-85725853-3acb-492e-8c04-01fe40ac0d5c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2792206342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.2792206342
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.777134853
Short name T902
Test name
Test status
Simulation time 32119121 ps
CPU time 1.04 seconds
Started Mar 07 12:57:00 PM PST 24
Finished Mar 07 12:57:01 PM PST 24
Peak memory 196672 kb
Host smart-aa455fe2-04a8-4096-8ec6-dc005fb54321
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777134853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.777134853
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.751981323
Short name T875
Test name
Test status
Simulation time 131630929 ps
CPU time 0.87 seconds
Started Mar 07 12:56:39 PM PST 24
Finished Mar 07 12:56:40 PM PST 24
Peak memory 195464 kb
Host smart-01222a17-f5d3-4009-9f3d-0ec18ac41bfe
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=751981323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.751981323
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3758040138
Short name T850
Test name
Test status
Simulation time 153528768 ps
CPU time 1.43 seconds
Started Mar 07 12:56:58 PM PST 24
Finished Mar 07 12:56:59 PM PST 24
Peak memory 196952 kb
Host smart-964eba9f-fb74-4e82-8fb7-0dd445bcfcbf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758040138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3758040138
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.905201829
Short name T916
Test name
Test status
Simulation time 115888110 ps
CPU time 0.93 seconds
Started Mar 07 12:56:47 PM PST 24
Finished Mar 07 12:56:48 PM PST 24
Peak memory 197160 kb
Host smart-d6fbf5c2-8147-4b8e-bc87-83cf7a380dfc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=905201829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.905201829
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3891714638
Short name T904
Test name
Test status
Simulation time 289560298 ps
CPU time 1.18 seconds
Started Mar 07 12:57:05 PM PST 24
Finished Mar 07 12:57:07 PM PST 24
Peak memory 196636 kb
Host smart-320fcec3-236c-4f51-be3f-b001b37b06ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891714638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3891714638
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.388951204
Short name T943
Test name
Test status
Simulation time 345722475 ps
CPU time 1.49 seconds
Started Mar 07 12:57:00 PM PST 24
Finished Mar 07 12:57:02 PM PST 24
Peak memory 197136 kb
Host smart-12d2550b-0398-41da-b193-2734c853a904
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=388951204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.388951204
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2466901795
Short name T885
Test name
Test status
Simulation time 959093480 ps
CPU time 1.27 seconds
Started Mar 07 12:56:53 PM PST 24
Finished Mar 07 12:56:55 PM PST 24
Peak memory 198176 kb
Host smart-5b4b42a0-3b8e-497f-8490-c0aa2880ff84
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466901795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2466901795
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.3819925204
Short name T924
Test name
Test status
Simulation time 254870147 ps
CPU time 1.12 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 195980 kb
Host smart-5c4998d9-7124-4e5c-b7e0-88e884e871ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3819925204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.3819925204
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.490865953
Short name T941
Test name
Test status
Simulation time 390562583 ps
CPU time 1.34 seconds
Started Mar 07 12:56:44 PM PST 24
Finished Mar 07 12:56:46 PM PST 24
Peak memory 198176 kb
Host smart-6e752ba0-504e-44e5-bdd3-6fc58c2fac3e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490865953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.490865953
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3067163647
Short name T920
Test name
Test status
Simulation time 304488202 ps
CPU time 1.46 seconds
Started Mar 07 12:57:01 PM PST 24
Finished Mar 07 12:57:03 PM PST 24
Peak memory 196516 kb
Host smart-0e12f934-499a-44df-b014-9e84de54f992
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3067163647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3067163647
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1616241757
Short name T868
Test name
Test status
Simulation time 166543178 ps
CPU time 0.95 seconds
Started Mar 07 12:56:47 PM PST 24
Finished Mar 07 12:56:48 PM PST 24
Peak memory 197200 kb
Host smart-1937c28c-e46a-4ecd-843a-71abdeb2d96a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616241757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1616241757
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3210427179
Short name T849
Test name
Test status
Simulation time 307820067 ps
CPU time 1.33 seconds
Started Mar 07 12:57:05 PM PST 24
Finished Mar 07 12:57:08 PM PST 24
Peak memory 198156 kb
Host smart-d0327b1f-5b3c-4773-8aa7-c73bba3849ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3210427179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3210427179
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.657682638
Short name T847
Test name
Test status
Simulation time 110227336 ps
CPU time 0.95 seconds
Started Mar 07 12:56:55 PM PST 24
Finished Mar 07 12:56:56 PM PST 24
Peak memory 196656 kb
Host smart-16512d50-809a-47bd-8fde-f18b90c8d241
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657682638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.657682638
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1898421643
Short name T886
Test name
Test status
Simulation time 57126910 ps
CPU time 1 seconds
Started Mar 07 12:57:12 PM PST 24
Finished Mar 07 12:57:14 PM PST 24
Peak memory 196572 kb
Host smart-ea564f59-f052-44b5-ae5c-130b2ea8748e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1898421643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1898421643
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.196582941
Short name T870
Test name
Test status
Simulation time 233882762 ps
CPU time 1.13 seconds
Started Mar 07 12:57:09 PM PST 24
Finished Mar 07 12:57:11 PM PST 24
Peak memory 196080 kb
Host smart-4d0a2f2d-8d4e-45a1-b919-bd2654a8b597
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196582941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.196582941
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.616029906
Short name T877
Test name
Test status
Simulation time 176982689 ps
CPU time 1.36 seconds
Started Mar 07 12:57:03 PM PST 24
Finished Mar 07 12:57:05 PM PST 24
Peak memory 197116 kb
Host smart-bf79dd53-ebeb-49d3-9fbe-586e322ad117
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=616029906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.616029906
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.147383005
Short name T864
Test name
Test status
Simulation time 43629727 ps
CPU time 0.97 seconds
Started Mar 07 12:56:51 PM PST 24
Finished Mar 07 12:56:52 PM PST 24
Peak memory 196676 kb
Host smart-4ac4125d-71ec-4aef-a339-cc3c2433e993
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147383005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.147383005
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3212331545
Short name T927
Test name
Test status
Simulation time 51228329 ps
CPU time 1.06 seconds
Started Mar 07 12:57:01 PM PST 24
Finished Mar 07 12:57:02 PM PST 24
Peak memory 198180 kb
Host smart-8b305c5b-db1b-4aa0-a482-c19aca8b0328
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3212331545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3212331545
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.492783631
Short name T884
Test name
Test status
Simulation time 170292230 ps
CPU time 1.01 seconds
Started Mar 07 12:57:06 PM PST 24
Finished Mar 07 12:57:09 PM PST 24
Peak memory 196636 kb
Host smart-6c60bb43-1dd6-4782-bdaf-c18332c34a7f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492783631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.492783631
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4226471030
Short name T856
Test name
Test status
Simulation time 95428554 ps
CPU time 0.81 seconds
Started Mar 07 12:56:59 PM PST 24
Finished Mar 07 12:57:00 PM PST 24
Peak memory 195356 kb
Host smart-0d844a3e-5c17-4cef-9f48-fbf6b1efd0cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4226471030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.4226471030
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4289825791
Short name T906
Test name
Test status
Simulation time 73154093 ps
CPU time 1.37 seconds
Started Mar 07 12:56:55 PM PST 24
Finished Mar 07 12:56:57 PM PST 24
Peak memory 198252 kb
Host smart-1e65b6d1-187b-418c-b8d0-271cc692b705
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289825791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4289825791
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.192360502
Short name T892
Test name
Test status
Simulation time 20158909 ps
CPU time 0.71 seconds
Started Mar 07 12:56:55 PM PST 24
Finished Mar 07 12:56:56 PM PST 24
Peak memory 195388 kb
Host smart-070ba0d2-77ef-4f9c-ab22-0a45f4c85bf5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=192360502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.192360502
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1684862925
Short name T900
Test name
Test status
Simulation time 125364838 ps
CPU time 0.81 seconds
Started Mar 07 12:56:49 PM PST 24
Finished Mar 07 12:56:50 PM PST 24
Peak memory 195444 kb
Host smart-6f4b8979-aaf7-427f-bd94-4f0cda9e44ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684862925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1684862925
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1875764982
Short name T942
Test name
Test status
Simulation time 40002095 ps
CPU time 0.9 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:43 PM PST 24
Peak memory 196324 kb
Host smart-0e478245-7e47-4d7c-b9fa-2d3e3f58e6fb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1875764982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1875764982
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.374528054
Short name T936
Test name
Test status
Simulation time 120250688 ps
CPU time 1.4 seconds
Started Mar 07 12:56:40 PM PST 24
Finished Mar 07 12:56:42 PM PST 24
Peak memory 198172 kb
Host smart-c2a8761a-57ec-4060-92d3-9a7b5d254570
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374528054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.374528054
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1068014091
Short name T933
Test name
Test status
Simulation time 116693025 ps
CPU time 1.2 seconds
Started Mar 07 12:56:39 PM PST 24
Finished Mar 07 12:56:41 PM PST 24
Peak memory 197320 kb
Host smart-20531c72-7ea5-4062-876b-e6a8e4ea9fc5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1068014091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1068014091
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3890195161
Short name T887
Test name
Test status
Simulation time 279806835 ps
CPU time 1.37 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:45 PM PST 24
Peak memory 198056 kb
Host smart-8f14be51-e13d-4d25-9b00-d7e3945b76dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890195161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3890195161
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.386940045
Short name T929
Test name
Test status
Simulation time 76408173 ps
CPU time 1.2 seconds
Started Mar 07 12:56:39 PM PST 24
Finished Mar 07 12:56:41 PM PST 24
Peak memory 196772 kb
Host smart-fe1849e8-0eb9-471c-a53e-359d4a01c7cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=386940045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.386940045
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2750899
Short name T855
Test name
Test status
Simulation time 54814616 ps
CPU time 0.71 seconds
Started Mar 07 12:56:43 PM PST 24
Finished Mar 07 12:56:55 PM PST 24
Peak memory 194364 kb
Host smart-e56086a7-e45f-4e73-a401-a874548329b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_en_
cdc_prim.2750899
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1063077898
Short name T928
Test name
Test status
Simulation time 255062121 ps
CPU time 1.15 seconds
Started Mar 07 12:56:53 PM PST 24
Finished Mar 07 12:56:54 PM PST 24
Peak memory 196752 kb
Host smart-671eefcb-7ff5-4743-b76c-474c341e6775
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1063077898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1063077898
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3512855371
Short name T910
Test name
Test status
Simulation time 111197822 ps
CPU time 1.15 seconds
Started Mar 07 12:56:42 PM PST 24
Finished Mar 07 12:56:43 PM PST 24
Peak memory 196568 kb
Host smart-af7d0dff-3f37-44bd-8314-86414198591e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512855371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3512855371
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1682630256
Short name T882
Test name
Test status
Simulation time 59307154 ps
CPU time 1.07 seconds
Started Mar 07 12:56:41 PM PST 24
Finished Mar 07 12:56:42 PM PST 24
Peak memory 197004 kb
Host smart-61846532-9449-4a0c-9b99-3cba675052a3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1682630256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1682630256
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3459576786
Short name T873
Test name
Test status
Simulation time 92014390 ps
CPU time 1.07 seconds
Started Mar 07 12:57:00 PM PST 24
Finished Mar 07 12:57:02 PM PST 24
Peak memory 196028 kb
Host smart-c55a172e-08f7-4e28-a1a0-b784fa7eb2b1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459576786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3459576786
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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