Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4918003	1			T22	61		T1	691		T11	1
all_pins[1]	4918003	1			T22	61		T1	691		T11	1
all_pins[2]	4918003	1			T22	61		T1	691		T11	1
all_pins[3]	4918003	1			T22	61		T1	691		T11	1
all_pins[4]	4918003	1			T22	61		T1	691		T11	1
all_pins[5]	4918003	1			T22	61		T1	691		T11	1
all_pins[6]	4918003	1			T22	61		T1	691		T11	1
all_pins[7]	4918003	1			T22	61		T1	691		T11	1
all_pins[8]	4918003	1			T22	61		T1	691		T11	1
all_pins[9]	4918003	1			T22	61		T1	691		T11	1
all_pins[10]	4918003	1			T22	61		T1	691		T11	1
all_pins[11]	4918003	1			T22	61		T1	691		T11	1
all_pins[12]	4918003	1			T22	61		T1	691		T11	1
all_pins[13]	4918003	1			T22	61		T1	691		T11	1
all_pins[14]	4918003	1			T22	61		T1	691		T11	1
all_pins[15]	4918003	1			T22	61		T1	691		T11	1
all_pins[16]	4918003	1			T22	61		T1	691		T11	1
all_pins[17]	4918003	1			T22	61		T1	691		T11	1
all_pins[18]	4918003	1			T22	61		T1	691		T11	1
all_pins[19]	4918003	1			T22	61		T1	691		T11	1
all_pins[20]	4918003	1			T22	61		T1	691		T11	1
all_pins[21]	4918003	1			T22	61		T1	691		T11	1
all_pins[22]	4918003	1			T22	61		T1	691		T11	1
all_pins[23]	4918003	1			T22	61		T1	691		T11	1
all_pins[24]	4918003	1			T22	61		T1	691		T11	1
all_pins[25]	4918003	1			T22	61		T1	691		T11	1
all_pins[26]	4918003	1			T22	61		T1	691		T11	1
all_pins[27]	4918003	1			T22	61		T1	691		T11	1
all_pins[28]	4918003	1			T22	61		T1	691		T11	1
all_pins[29]	4918003	1			T22	61		T1	691		T11	1
all_pins[30]	4918003	1			T22	61		T1	691		T11	1
all_pins[31]	4918003	1			T22	61		T1	691		T11	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	97770251	1			T22	1058		T1	14401		T11	32
values[0x1]	59605845	1			T22	894		T1	7711		T12	108775
transitions[0x0=>0x1]	35738787	1			T22	444		T1	4799		T12	655686
transitions[0x1=>0x0]	35738646	1			T22	444		T1	4799		T12	655686

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3061439	1			T22	31		T1	504		T11	1
all_pins[0]	values[0x1]	1856564	1			T22	30		T1	187		T12	33791
all_pins[0]	transitions[0x0=>0x1]	1148208	1			T22	17		T1	116		T12	20843
all_pins[0]	transitions[0x1=>0x0]	1156607	1			T22	15		T1	209		T12	21154
all_pins[1]	values[0x0]	3057521	1			T22	26		T1	437		T11	1
all_pins[1]	values[0x1]	1860482	1			T22	35		T1	254		T12	33611
all_pins[1]	transitions[0x0=>0x1]	1117526	1			T22	15		T1	195		T12	20340
all_pins[1]	transitions[0x1=>0x0]	1113608	1			T22	10		T1	128		T12	20520
all_pins[2]	values[0x0]	3051382	1			T22	33		T1	408		T11	1
all_pins[2]	values[0x1]	1866621	1			T22	28		T1	283		T12	33860
all_pins[2]	transitions[0x0=>0x1]	1120562	1			T22	13		T1	170		T12	20013
all_pins[2]	transitions[0x1=>0x0]	1114423	1			T22	20		T1	141		T12	19764
all_pins[3]	values[0x0]	3049610	1			T22	34		T1	468		T11	1
all_pins[3]	values[0x1]	1868393	1			T22	27		T1	223		T12	34451
all_pins[3]	transitions[0x0=>0x1]	1116783	1			T22	14		T1	121		T12	20679
all_pins[3]	transitions[0x1=>0x0]	1115011	1			T22	15		T1	181		T12	20088
all_pins[4]	values[0x0]	3050280	1			T22	28		T1	439		T11	1
all_pins[4]	values[0x1]	1867723	1			T22	33		T1	252		T12	34122
all_pins[4]	transitions[0x0=>0x1]	1116638	1			T22	15		T1	161		T12	20767
all_pins[4]	transitions[0x1=>0x0]	1117308	1			T22	9		T1	132		T12	21096
all_pins[5]	values[0x0]	3056317	1			T22	28		T1	460		T11	1
all_pins[5]	values[0x1]	1861686	1			T22	33		T1	231		T12	33399
all_pins[5]	transitions[0x0=>0x1]	1111993	1			T22	13		T1	138		T12	20236
all_pins[5]	transitions[0x1=>0x0]	1118030	1			T22	13		T1	159		T12	20959
all_pins[6]	values[0x0]	3056832	1			T22	40		T1	441		T11	1
all_pins[6]	values[0x1]	1861171	1			T22	21		T1	250		T12	33065
all_pins[6]	transitions[0x0=>0x1]	1116732	1			T22	8		T1	142		T12	20351
all_pins[6]	transitions[0x1=>0x0]	1117247	1			T22	20		T1	123		T12	20685
all_pins[7]	values[0x0]	3057059	1			T22	34		T1	448		T11	1
all_pins[7]	values[0x1]	1860944	1			T22	27		T1	243		T12	34892
all_pins[7]	transitions[0x0=>0x1]	1116357	1			T22	17		T1	155		T12	21418
all_pins[7]	transitions[0x1=>0x0]	1116584	1			T22	11		T1	162		T12	19591
all_pins[8]	values[0x0]	3056022	1			T22	35		T1	430		T11	1
all_pins[8]	values[0x1]	1861981	1			T22	26		T1	261		T12	34351
all_pins[8]	transitions[0x0=>0x1]	1115218	1			T22	11		T1	176		T12	20412
all_pins[8]	transitions[0x1=>0x0]	1114181	1			T22	12		T1	158		T12	20953
all_pins[9]	values[0x0]	3056702	1			T22	33		T1	398		T11	1
all_pins[9]	values[0x1]	1861301	1			T22	28		T1	293		T12	34466
all_pins[9]	transitions[0x0=>0x1]	1115563	1			T22	11		T1	152		T12	20996
all_pins[9]	transitions[0x1=>0x0]	1116243	1			T22	9		T1	120		T12	20881
all_pins[10]	values[0x0]	3057626	1			T22	34		T1	519		T11	1
all_pins[10]	values[0x1]	1860377	1			T22	27		T1	172		T12	34647
all_pins[10]	transitions[0x0=>0x1]	1116980	1			T22	12		T1	86		T12	20773
all_pins[10]	transitions[0x1=>0x0]	1117904	1			T22	13		T1	207		T12	20592
all_pins[11]	values[0x0]	3057268	1			T22	46		T1	452		T11	1
all_pins[11]	values[0x1]	1860735	1			T22	15		T1	239		T12	34583
all_pins[11]	transitions[0x0=>0x1]	1115541	1			T22	8		T1	181		T12	20475
all_pins[11]	transitions[0x1=>0x0]	1115183	1			T22	20		T1	114		T12	20539
all_pins[12]	values[0x0]	3056218	1			T22	40		T1	490		T11	1
all_pins[12]	values[0x1]	1861785	1			T22	21		T1	201		T12	34171
all_pins[12]	transitions[0x0=>0x1]	1113662	1			T22	14		T1	121		T12	20059
all_pins[12]	transitions[0x1=>0x0]	1112612	1			T22	8		T1	159		T12	20471
all_pins[13]	values[0x0]	3056749	1			T22	33		T1	433		T11	1
all_pins[13]	values[0x1]	1861254	1			T22	28		T1	258		T12	33872
all_pins[13]	transitions[0x0=>0x1]	1112647	1			T22	17		T1	142		T12	20429
all_pins[13]	transitions[0x1=>0x0]	1113178	1			T22	10		T1	85		T12	20728
all_pins[14]	values[0x0]	3051186	1			T22	29		T1	442		T11	1
all_pins[14]	values[0x1]	1866817	1			T22	32		T1	249		T12	33635
all_pins[14]	transitions[0x0=>0x1]	1118109	1			T22	16		T1	145		T12	20265
all_pins[14]	transitions[0x1=>0x0]	1112546	1			T22	12		T1	154		T12	20502
all_pins[15]	values[0x0]	3060404	1			T22	35		T1	484		T11	1
all_pins[15]	values[0x1]	1857599	1			T22	26		T1	207		T12	33883
all_pins[15]	transitions[0x0=>0x1]	1112414	1			T22	11		T1	140		T12	20668
all_pins[15]	transitions[0x1=>0x0]	1121632	1			T22	17		T1	182		T12	20420
all_pins[16]	values[0x0]	3052832	1			T22	34		T1	471		T11	1
all_pins[16]	values[0x1]	1865171	1			T22	27		T1	220		T12	33641
all_pins[16]	transitions[0x0=>0x1]	1117873	1			T22	14		T1	154		T12	19837
all_pins[16]	transitions[0x1=>0x0]	1110301	1			T22	13		T1	141		T12	20079
all_pins[17]	values[0x0]	3051784	1			T22	39		T1	423		T11	1
all_pins[17]	values[0x1]	1866219	1			T22	22		T1	268		T12	34156
all_pins[17]	transitions[0x0=>0x1]	1115749	1			T22	13		T1	176		T12	20418
all_pins[17]	transitions[0x1=>0x0]	1114701	1			T22	18		T1	128		T12	19903
all_pins[18]	values[0x0]	3056967	1			T22	31		T1	487		T11	1
all_pins[18]	values[0x1]	1861036	1			T22	30		T1	204		T12	33906
all_pins[18]	transitions[0x0=>0x1]	1113823	1			T22	16		T1	115		T12	20558
all_pins[18]	transitions[0x1=>0x0]	1119006	1			T22	8		T1	179		T12	20808
all_pins[19]	values[0x0]	3056745	1			T22	31		T1	463		T11	1
all_pins[19]	values[0x1]	1861258	1			T22	30		T1	228		T12	34009
all_pins[19]	transitions[0x0=>0x1]	1116538	1			T22	18		T1	177		T12	20368
all_pins[19]	transitions[0x1=>0x0]	1116316	1			T22	18		T1	153		T12	20265
all_pins[20]	values[0x0]	3057962	1			T22	31		T1	382		T11	1
all_pins[20]	values[0x1]	1860041	1			T22	30		T1	309		T12	34434
all_pins[20]	transitions[0x0=>0x1]	1115321	1			T22	17		T1	199		T12	20737
all_pins[20]	transitions[0x1=>0x0]	1116538	1			T22	17		T1	118		T12	20312
all_pins[21]	values[0x0]	3062080	1			T22	40		T1	409		T11	1
all_pins[21]	values[0x1]	1855923	1			T22	21		T1	282		T12	34173
all_pins[21]	transitions[0x0=>0x1]	1111566	1			T22	9		T1	137		T12	20542
all_pins[21]	transitions[0x1=>0x0]	1115684	1			T22	18		T1	164		T12	20803
all_pins[22]	values[0x0]	3050996	1			T22	24		T1	479		T11	1
all_pins[22]	values[0x1]	1867007	1			T22	37		T1	212		T12	33709
all_pins[22]	transitions[0x0=>0x1]	1119424	1			T22	25		T1	123		T12	20045
all_pins[22]	transitions[0x1=>0x0]	1108340	1			T22	9		T1	193		T12	20509
all_pins[23]	values[0x0]	3047360	1			T22	33		T1	470		T11	1
all_pins[23]	values[0x1]	1870643	1			T22	28		T1	221		T12	34705
all_pins[23]	transitions[0x0=>0x1]	1118718	1			T22	13		T1	156		T12	21072
all_pins[23]	transitions[0x1=>0x0]	1115082	1			T22	22		T1	147		T12	20076
all_pins[24]	values[0x0]	3057319	1			T22	35		T1	455		T11	1
all_pins[24]	values[0x1]	1860684	1			T22	26		T1	236		T12	33094
all_pins[24]	transitions[0x0=>0x1]	1112457	1			T22	9		T1	148		T12	19614
all_pins[24]	transitions[0x1=>0x0]	1122416	1			T22	11		T1	133		T12	21225
all_pins[25]	values[0x0]	3055376	1			T22	31		T1	437		T11	1
all_pins[25]	values[0x1]	1862627	1			T22	30		T1	254		T12	34485
all_pins[25]	transitions[0x0=>0x1]	1117306	1			T22	16		T1	168		T12	20971
all_pins[25]	transitions[0x1=>0x0]	1115363	1			T22	12		T1	150		T12	19580
all_pins[26]	values[0x0]	3055402	1			T22	30		T1	499		T11	1
all_pins[26]	values[0x1]	1862601	1			T22	31		T1	192		T12	34102
all_pins[26]	transitions[0x0=>0x1]	1115736	1			T22	13		T1	135		T12	20523
all_pins[26]	transitions[0x1=>0x0]	1115762	1			T22	12		T1	197		T12	20906
all_pins[27]	values[0x0]	3053309	1			T22	32		T1	489		T11	1
all_pins[27]	values[0x1]	1864694	1			T22	29		T1	202		T12	33287
all_pins[27]	transitions[0x0=>0x1]	1117260	1			T22	12		T1	152		T12	20366
all_pins[27]	transitions[0x1=>0x0]	1115167	1			T22	14		T1	142		T12	21181
all_pins[28]	values[0x0]	3055800	1			T22	30		T1	392		T11	1
all_pins[28]	values[0x1]	1862203	1			T22	31		T1	299		T12	33804
all_pins[28]	transitions[0x0=>0x1]	1115167	1			T22	17		T1	183		T12	20576
all_pins[28]	transitions[0x1=>0x0]	1117658	1			T22	15		T1	86		T12	20059
all_pins[29]	values[0x0]	3052069	1			T22	37		T1	383		T11	1
all_pins[29]	values[0x1]	1865934	1			T22	24		T1	308		T12	34214
all_pins[29]	transitions[0x0=>0x1]	1117412	1			T22	10		T1	144		T12	20591
all_pins[29]	transitions[0x1=>0x0]	1113681	1			T22	17		T1	135		T12	20181
all_pins[30]	values[0x0]	3058736	1			T22	28		T1	498		T11	1
all_pins[30]	values[0x1]	1859267	1			T22	33		T1	193		T12	33132
all_pins[30]	transitions[0x0=>0x1]	1110323	1			T22	17		T1	96		T12	19793
all_pins[30]	transitions[0x1=>0x0]	1116990	1			T22	8		T1	211		T12	20875
all_pins[31]	values[0x0]	3052899	1			T22	33		T1	411		T11	1
all_pins[31]	values[0x1]	1865104	1			T22	28		T1	280		T12	34102
all_pins[31]	transitions[0x0=>0x1]	1119181	1			T22	13		T1	195		T12	20951
all_pins[31]	transitions[0x1=>0x0]	1113344	1			T22	18		T1	108		T12	19981