Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[1]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[2]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[3]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[4]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[5]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[6]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[7]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[8]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[9]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[10]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[11]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[12]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[13]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[14]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[15]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[16]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[17]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[18]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[19]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[20]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[21]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[22]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[23]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[24]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[25]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[26]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[27]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[28]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[29]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[30]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[31]	15866288	1			T22	957		T1	1571		T11	714

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305423127

1

T22

15095

T1

11886

T11

17410

auto[1]

202298089

1

T22

15529

T1

38386

T11

5438

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

407036029

1

T22

30624

T1

28655

T11

16070

auto[1]

100685187

1

T1

21617

T11

6778

T12

170305

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

377789020

1

T22

30624

T1

25234

T11

11051

auto[1]

129932196

1

T1

25038

T11

11797

T12

229268

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5912722	1			T22	499		T1	6		T11	236
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4307832	1			T22	458		T1	395		T11	28
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1582197	1			T1	308		T11	112		T12	26800
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2036428	1			T1	31		T11	201		T12	40932
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	456024	1			T1	463		T11	32		T12	3226
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1571085	1			T1	368		T11	105		T12	26887
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5931950	1			T22	496		T1	12		T11	179
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4296345	1			T22	461		T1	505		T11	15
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1585143	1			T1	322		T11	133		T12	26798
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2030538	1			T1	7		T11	224		T12	41460
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	455678	1			T1	396		T11	37		T12	3303
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1566634	1			T1	329		T11	126		T12	26343
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5929741	1			T22	413		T1	9		T11	136
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4286331	1			T22	544		T1	499		T11	18
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1582241	1			T1	278		T11	139		T12	26777
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2038157	1			T1	27		T11	232		T12	41783
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	459357	1			T1	440		T11	35		T12	3392
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1570461	1			T1	318		T11	154		T12	25634
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5919593	1			T22	442		T1	24		T11	201
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4303673	1			T22	515		T1	390		T11	30
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1582345	1			T1	371		T11	62		T12	26230
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2035579	1			T1	16		T11	295		T12	41998
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	458128	1			T1	398		T11	27		T12	3484
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1566970	1			T1	372		T11	99		T12	26676
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5925628	1			T22	405		T1	7		T11	194
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4294281	1			T22	552		T1	355		T11	23
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1579951	1			T1	366		T11	86		T12	27352
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2040048	1			T1	25		T11	230		T12	41259
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	458097	1			T1	429		T11	39		T12	3388
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1568283	1			T1	389		T11	142		T12	26410
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5915597	1			T22	490		T1	16		T11	151
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4311198	1			T22	467		T1	390		T11	13
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1582461	1			T1	330		T11	89		T12	26312
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2035054	1			T1	17		T11	265		T12	42553
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	455184	1			T1	453		T11	51		T12	3536
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1566794	1			T1	365		T11	145		T12	27056
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5911365	1			T22	435		T1	17		T11	225
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4306152	1			T22	522		T1	537		T11	37
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1588902	1			T1	303		T11	86		T12	26560
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2030361	1			T1	10		T11	209		T12	40933
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	456636	1			T1	413		T11	20		T12	3390
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1572872	1			T1	291		T11	137		T12	27206
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5929058	1			T22	478		T1	20		T11	176
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4295107	1			T22	479		T1	367		T11	17
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1585883	1			T1	221		T11	98		T12	27161
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2034478	1			T1	20		T11	260		T12	41235
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	455003	1			T1	459		T11	24		T12	3362
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1566759	1			T1	484		T11	139		T12	26433
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5917986	1			T22	521		T1	15		T11	346
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4301935	1			T22	436		T1	379		T11	46
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1582227	1			T1	335		T11	86		T12	27639
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2036544	1			T1	18		T11	165		T12	41325
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	455409	1			T1	515		T11	16		T12	3522
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1572187	1			T1	309		T11	55		T12	25932
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5919258	1			T22	529		T1	17		T11	227
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4302566	1			T22	428		T1	505		T11	45
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1584897	1			T1	277		T11	126		T12	26229
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2031220	1			T1	22		T11	198		T12	41749
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	458507	1			T1	434		T11	23		T12	3220
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1569840	1			T1	316		T11	95		T12	26477
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5922488	1			T22	472		T1	7		T11	171
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4303461	1			T22	485		T1	331		T11	41
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1580503	1			T1	365		T11	110		T12	26851
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2034459	1			T1	31		T11	244		T12	41018
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	457750	1			T1	465		T11	32		T12	3348
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1567627	1			T1	372		T11	116		T12	27011
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5919309	1			T22	464		T1	12		T11	263
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4297289	1			T22	493		T1	420		T11	26
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1580260	1			T1	278		T11	78		T12	26854
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2040271	1			T1	12		T11	230		T12	41323
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	456933	1			T1	554		T11	18		T12	3442
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1572226	1			T1	295		T11	99		T12	26667
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5928879	1			T22	494		T1	18		T11	210
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4297479	1			T22	463		T1	491		T11	20
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1588345	1			T1	369		T11	123		T12	26465
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2027126	1			T1	10		T11	208		T12	42032
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	454108	1			T1	413		T11	26		T12	3537
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1570351	1			T1	270		T11	127		T12	26438
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5922159	1			T22	414		T1	22		T11	219
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4301123	1			T22	543		T1	511		T11	27
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1582939	1			T1	342		T11	67		T12	26712
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2034834	1			T1	4		T11	287		T12	41598
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	457491	1			T1	401		T11	30		T12	3430
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1567742	1			T1	291		T11	84		T12	26303
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5918827	1			T22	465		T1	31		T11	222
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4303905	1			T22	492		T1	426		T11	38
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1589268	1			T1	337		T11	150		T12	26985
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2022202	1			T1	12		T11	174		T12	41560
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	459845	1			T1	394		T11	26		T12	3454
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1572241	1			T1	371		T11	104		T12	25706
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5932507	1			T22	510		T1	23		T11	123
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4290692	1			T22	447		T1	519		T11	20
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1588715	1			T1	365		T11	87		T12	26601
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2028071	1			T1	15		T11	291		T12	41799
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	458491	1			T1	375		T11	35		T12	3398
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1567812	1			T1	274		T11	158		T12	26822
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5945864	1			T22	490		T1	20		T11	204
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4289988	1			T22	467		T1	453		T11	31
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1576884	1			T1	332		T11	112		T12	27049
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2035690	1			T1	11		T11	236		T12	41401
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	457485	1			T1	451		T11	22		T12	3416
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1560377	1			T1	304		T11	109		T12	26091
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5918919	1			T22	460		T1	20		T11	239
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4306935	1			T22	497		T1	369		T11	35
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1572935	1			T1	455		T11	136		T12	26779
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2042245	1			T1	17		T11	221		T12	42022
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	458514	1			T1	312		T11	23		T12	3346
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1566740	1			T1	398		T11	60		T12	26813
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5918151	1			T22	486		T1	26		T11	231
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4303415	1			T22	471		T1	435		T11	26
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1579405	1			T1	378		T11	86		T12	26310
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2041758	1			T1	15		T11	227		T12	42303
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	458793	1			T1	371		T11	28		T12	3489
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1564766	1			T1	346		T11	116		T12	26630
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5924553	1			T22	465		T1	27		T11	248
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4299694	1			T22	492		T1	428		T11	29
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1577045	1			T1	355		T11	120		T12	26954
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2043909	1			T1	10		T11	200		T12	41635
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	457717	1			T1	369		T11	31		T12	3318
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1563370	1			T1	382		T11	86		T12	26787
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5931092	1			T22	484		T1	16		T11	301
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4297793	1			T22	473		T1	517		T11	26
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1575724	1			T1	232		T11	125		T12	27255
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2038398	1			T1	17		T11	157		T12	40647
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	458702	1			T1	435		T11	23		T12	3368
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1564579	1			T1	354		T11	82		T12	26311
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5939716	1			T22	509		T1	21		T11	226
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4285963	1			T22	448		T1	360		T11	38
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1577058	1			T1	427		T11	120		T12	27054
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2040782	1			T1	17		T11	204		T12	42344
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	457003	1			T1	401		T11	38		T12	3537
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1565766	1			T1	345		T11	88		T12	26875
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5930034	1			T22	470		T1	17		T11	261
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4296899	1			T22	487		T1	394		T11	32
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1574408	1			T1	277		T11	57		T12	26632
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2040900	1			T1	20		T11	237		T12	41927
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	457940	1			T1	482		T11	31		T12	3316
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1566107	1			T1	381		T11	96		T12	26467
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5931385	1			T22	477		T1	8		T11	231
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4297963	1			T22	480		T1	345		T11	44
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1575682	1			T1	431		T11	97		T12	26114
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2040274	1			T1	23		T11	193		T12	42761
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	456522	1			T1	364		T11	16		T12	3468
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1564462	1			T1	400		T11	133		T12	26345
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5945226	1			T22	527		T1	20		T11	186
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4290329	1			T22	430		T1	422		T11	37
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1573820	1			T1	331		T11	135		T12	26012
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2044430	1			T1	11		T11	230		T12	42809
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	460127	1			T1	480		T11	23		T12	3428
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1552356	1			T1	307		T11	103		T12	26130
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5915149	1			T22	459		T1	14		T11	244
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4311079	1			T22	498		T1	474		T11	36
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1578010	1			T1	321		T11	97		T12	26660
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2038715	1			T1	16		T11	229		T12	41524
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	459316	1			T1	431		T11	18		T12	3269
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1564019	1			T1	315		T11	90		T12	25978
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5931562	1			T22	447		T1	20		T11	221
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4296382	1			T22	510		T1	423		T11	38
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1578288	1			T1	378		T11	73		T12	26721
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2040773	1			T1	16		T11	247		T12	42110
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	458750	1			T1	415		T11	29		T12	3417
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1560533	1			T1	319		T11	106		T12	26556
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5946317	1			T22	432		T1	11		T11	208
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4284249	1			T22	525		T1	538		T11	40
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1579177	1			T1	314		T11	117		T12	26831
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2043146	1			T1	20		T11	241		T12	41870
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	459498	1			T1	417		T11	25		T12	3514
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1553901	1			T1	271		T11	83		T12	26905
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5931472	1			T22	470		T1	22		T11	223
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4300215	1			T22	487		T1	365		T11	48
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1582583	1			T1	495		T11	107		T12	26938
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2032555	1			T1	18		T11	184		T12	41794
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	457380	1			T1	338		T11	17		T12	3617
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1562083	1			T1	333		T11	135		T12	26587
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5936569	1			T22	440		T1	11		T11	222
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4287037	1			T22	517		T1	443		T11	29
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1575463	1			T1	309		T11	88		T12	26833
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2046941	1			T1	21		T11	214		T12	42364
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	460324	1			T1	513		T11	33		T12	3337
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1559954	1			T1	274		T11	128		T12	26353
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5939631	1			T22	509		T1	19		T11	182
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4293696	1			T22	448		T1	453		T11	26
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1577561	1			T1	278		T11	81		T12	25921
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2033834	1			T1	14		T11	275		T12	42330
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	458200	1			T1	496		T11	38		T12	3326
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1563366	1			T1	311		T11	112		T12	26698
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5920217	1			T22	443		T1	11		T11	147
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4305380	1			T22	514		T1	447		T11	19
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1579390	1			T1	329		T11	37		T12	26823
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2040773	1			T1	15		T11	329		T12	41532
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	457314	1			T1	415		T11	36		T12	3315
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1563214	1			T1	354		T11	146		T12	26316

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal