Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[1]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[2]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[3]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[4]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[5]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[6]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[7]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[8]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[9]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[10]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[11]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[12]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[13]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[14]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[15]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[16]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[17]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[18]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[19]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[20]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[21]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[22]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[23]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[24]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[25]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[26]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[27]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[28]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[29]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[30]	15866288	1			T22	957		T1	1571		T11	714
bins_for_gpio_bits[31]	15866288	1			T22	957		T1	1571		T11	714

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305423127

1

T22

15095

T1

11886

T11

17410

auto[1]

202298089

1

T22

15529

T1

38386

T11

5438

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305415620

1

T22

15095

T1

11897

T11

17410

auto[1]

202305596

1

T22

15529

T1

38375

T11

5438

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	9249085	1			T22	499		T1	300		T11	531
bins_for_gpio_bits[0]	auto[0]	auto[1]	282035	1			T1	45		T11	18		T12	4771
bins_for_gpio_bits[0]	auto[1]	auto[0]	282262	1			T1	45		T11	18		T12	4772
bins_for_gpio_bits[0]	auto[1]	auto[1]	6052906	1			T22	458		T1	1181		T11	147
bins_for_gpio_bits[1]	auto[0]	auto[0]	9265667	1			T22	496		T1	291		T11	514
bins_for_gpio_bits[1]	auto[0]	auto[1]	281696	1			T1	51		T11	22		T12	4668
bins_for_gpio_bits[1]	auto[1]	auto[0]	281964	1			T1	50		T11	22		T12	4669
bins_for_gpio_bits[1]	auto[1]	auto[1]	6036961	1			T22	461		T1	1179		T11	156
bins_for_gpio_bits[2]	auto[0]	auto[0]	9267928	1			T22	413		T1	270		T11	486
bins_for_gpio_bits[2]	auto[0]	auto[1]	281996	1			T1	44		T11	21		T12	4699
bins_for_gpio_bits[2]	auto[1]	auto[0]	282211	1			T1	44		T11	21		T12	4700
bins_for_gpio_bits[2]	auto[1]	auto[1]	6034153	1			T22	544		T1	1213		T11	186
bins_for_gpio_bits[3]	auto[0]	auto[0]	9255679	1			T22	442		T1	361		T11	539
bins_for_gpio_bits[3]	auto[0]	auto[1]	281561	1			T1	50		T11	19		T12	4783
bins_for_gpio_bits[3]	auto[1]	auto[0]	281838	1			T1	50		T11	19		T12	4784
bins_for_gpio_bits[3]	auto[1]	auto[1]	6047210	1			T22	515		T1	1110		T11	137
bins_for_gpio_bits[4]	auto[0]	auto[0]	9263226	1			T22	405		T1	355		T11	491
bins_for_gpio_bits[4]	auto[0]	auto[1]	282152	1			T1	43		T11	19		T12	4767
bins_for_gpio_bits[4]	auto[1]	auto[0]	282401	1			T1	43		T11	19		T12	4767
bins_for_gpio_bits[4]	auto[1]	auto[1]	6038509	1			T22	552		T1	1130		T11	185
bins_for_gpio_bits[5]	auto[0]	auto[0]	9251353	1			T22	490		T1	310		T11	482
bins_for_gpio_bits[5]	auto[0]	auto[1]	281531	1			T1	53		T11	23		T12	4784
bins_for_gpio_bits[5]	auto[1]	auto[0]	281759	1			T1	53		T11	23		T12	4784
bins_for_gpio_bits[5]	auto[1]	auto[1]	6051645	1			T22	467		T1	1155		T11	186
bins_for_gpio_bits[6]	auto[0]	auto[0]	9248413	1			T22	435		T1	285		T11	500
bins_for_gpio_bits[6]	auto[0]	auto[1]	281990	1			T1	45		T11	20		T12	4791
bins_for_gpio_bits[6]	auto[1]	auto[0]	282215	1			T1	45		T11	20		T12	4791
bins_for_gpio_bits[6]	auto[1]	auto[1]	6053670	1			T22	522		T1	1196		T11	174
bins_for_gpio_bits[7]	auto[0]	auto[0]	9267786	1			T22	478		T1	226		T11	517
bins_for_gpio_bits[7]	auto[0]	auto[1]	281398	1			T1	35		T11	17		T12	4731
bins_for_gpio_bits[7]	auto[1]	auto[0]	281633	1			T1	35		T11	17		T12	4731
bins_for_gpio_bits[7]	auto[1]	auto[1]	6035471	1			T22	479		T1	1275		T11	163
bins_for_gpio_bits[8]	auto[0]	auto[0]	9254316	1			T22	521		T1	333		T11	588
bins_for_gpio_bits[8]	auto[0]	auto[1]	282207	1			T1	36		T11	9		T12	4777
bins_for_gpio_bits[8]	auto[1]	auto[0]	282441	1			T1	35		T11	9		T12	4777
bins_for_gpio_bits[8]	auto[1]	auto[1]	6047324	1			T22	436		T1	1167		T11	108
bins_for_gpio_bits[9]	auto[0]	auto[0]	9253428	1			T22	529		T1	263		T11	533
bins_for_gpio_bits[9]	auto[0]	auto[1]	281726	1			T1	54		T11	18		T12	4778
bins_for_gpio_bits[9]	auto[1]	auto[0]	281947	1			T1	53		T11	18		T12	4779
bins_for_gpio_bits[9]	auto[1]	auto[1]	6049187	1			T22	428		T1	1201		T11	145
bins_for_gpio_bits[10]	auto[0]	auto[0]	9255584	1			T22	472		T1	352		T11	504
bins_for_gpio_bits[10]	auto[0]	auto[1]	281629	1			T1	51		T11	21		T12	4767
bins_for_gpio_bits[10]	auto[1]	auto[0]	281866	1			T1	51		T11	21		T12	4768
bins_for_gpio_bits[10]	auto[1]	auto[1]	6047209	1			T22	485		T1	1117		T11	168
bins_for_gpio_bits[11]	auto[0]	auto[0]	9257127	1			T22	464		T1	261		T11	552
bins_for_gpio_bits[11]	auto[0]	auto[1]	282490	1			T1	41		T11	19		T12	4768
bins_for_gpio_bits[11]	auto[1]	auto[0]	282713	1			T1	41		T11	19		T12	4769
bins_for_gpio_bits[11]	auto[1]	auto[1]	6043958	1			T22	493		T1	1228		T11	124
bins_for_gpio_bits[12]	auto[0]	auto[0]	9262012	1			T22	494		T1	350		T11	521
bins_for_gpio_bits[12]	auto[0]	auto[1]	282107	1			T1	47		T11	20		T12	4724
bins_for_gpio_bits[12]	auto[1]	auto[0]	282338	1			T1	47		T11	20		T12	4724
bins_for_gpio_bits[12]	auto[1]	auto[1]	6039831	1			T22	463		T1	1127		T11	153
bins_for_gpio_bits[13]	auto[0]	auto[0]	9257986	1			T22	414		T1	318		T11	558
bins_for_gpio_bits[13]	auto[0]	auto[1]	281711	1			T1	50		T11	15		T12	4721
bins_for_gpio_bits[13]	auto[1]	auto[0]	281946	1			T1	50		T11	15		T12	4722
bins_for_gpio_bits[13]	auto[1]	auto[1]	6044645	1			T22	543		T1	1153		T11	126
bins_for_gpio_bits[14]	auto[0]	auto[0]	9248668	1			T22	465		T1	337		T11	530
bins_for_gpio_bits[14]	auto[0]	auto[1]	281373	1			T1	43		T11	16		T12	4694
bins_for_gpio_bits[14]	auto[1]	auto[0]	281629	1			T1	43		T11	16		T12	4695
bins_for_gpio_bits[14]	auto[1]	auto[1]	6054618	1			T22	492		T1	1148		T11	152
bins_for_gpio_bits[15]	auto[0]	auto[0]	9266613	1			T22	510		T1	347		T11	477
bins_for_gpio_bits[15]	auto[0]	auto[1]	282438	1			T1	56		T11	24		T12	4775
bins_for_gpio_bits[15]	auto[1]	auto[0]	282680	1			T1	56		T11	24		T12	4775
bins_for_gpio_bits[15]	auto[1]	auto[1]	6034557	1			T22	447		T1	1112		T11	189
bins_for_gpio_bits[16]	auto[0]	auto[0]	9277187	1			T22	490		T1	320		T11	534
bins_for_gpio_bits[16]	auto[0]	auto[1]	281013	1			T1	43		T11	18		T12	4708
bins_for_gpio_bits[16]	auto[1]	auto[0]	281251	1			T1	43		T11	18		T12	4708
bins_for_gpio_bits[16]	auto[1]	auto[1]	6026837	1			T22	467		T1	1165		T11	144
bins_for_gpio_bits[17]	auto[0]	auto[0]	9251461	1			T22	460		T1	441		T11	587
bins_for_gpio_bits[17]	auto[0]	auto[1]	282414	1			T1	51		T11	9		T12	4835
bins_for_gpio_bits[17]	auto[1]	auto[0]	282638	1			T1	51		T11	9		T12	4835
bins_for_gpio_bits[17]	auto[1]	auto[1]	6049775	1			T22	497		T1	1028		T11	109
bins_for_gpio_bits[18]	auto[0]	auto[0]	9256653	1			T22	486		T1	370		T11	524
bins_for_gpio_bits[18]	auto[0]	auto[1]	282429	1			T1	50		T11	20		T12	4849
bins_for_gpio_bits[18]	auto[1]	auto[0]	282661	1			T1	49		T11	20		T12	4850
bins_for_gpio_bits[18]	auto[1]	auto[1]	6044545	1			T22	471		T1	1102		T11	150
bins_for_gpio_bits[19]	auto[0]	auto[0]	9263472	1			T22	465		T1	338		T11	552
bins_for_gpio_bits[19]	auto[0]	auto[1]	281802	1			T1	55		T11	16		T12	4793
bins_for_gpio_bits[19]	auto[1]	auto[0]	282035	1			T1	54		T11	16		T12	4795
bins_for_gpio_bits[19]	auto[1]	auto[1]	6038979	1			T22	492		T1	1124		T11	130
bins_for_gpio_bits[20]	auto[0]	auto[0]	9263274	1			T22	484		T1	224		T11	568
bins_for_gpio_bits[20]	auto[0]	auto[1]	281750	1			T1	42		T11	15		T12	4862
bins_for_gpio_bits[20]	auto[1]	auto[0]	281940	1			T1	41		T11	15		T12	4863
bins_for_gpio_bits[20]	auto[1]	auto[1]	6039324	1			T22	473		T1	1264		T11	116
bins_for_gpio_bits[21]	auto[0]	auto[0]	9274992	1			T22	509		T1	411		T11	531
bins_for_gpio_bits[21]	auto[0]	auto[1]	282367	1			T1	54		T11	19		T12	4833
bins_for_gpio_bits[21]	auto[1]	auto[0]	282564	1			T1	54		T11	19		T12	4833
bins_for_gpio_bits[21]	auto[1]	auto[1]	6026365	1			T22	448		T1	1052		T11	145
bins_for_gpio_bits[22]	auto[0]	auto[0]	9263213	1			T22	470		T1	270		T11	538
bins_for_gpio_bits[22]	auto[0]	auto[1]	281908	1			T1	45		T11	17		T12	4788
bins_for_gpio_bits[22]	auto[1]	auto[0]	282129	1			T1	44		T11	17		T12	4788
bins_for_gpio_bits[22]	auto[1]	auto[1]	6039038	1			T22	487		T1	1212		T11	142
bins_for_gpio_bits[23]	auto[0]	auto[0]	9265417	1			T22	477		T1	410		T11	500
bins_for_gpio_bits[23]	auto[0]	auto[1]	281688	1			T1	52		T11	21		T12	4711
bins_for_gpio_bits[23]	auto[1]	auto[0]	281924	1			T1	52		T11	21		T12	4711
bins_for_gpio_bits[23]	auto[1]	auto[1]	6037259	1			T22	480		T1	1057		T11	172
bins_for_gpio_bits[24]	auto[0]	auto[0]	9282173	1			T22	527		T1	313		T11	529
bins_for_gpio_bits[24]	auto[0]	auto[1]	281092	1			T1	49		T11	22		T12	4693
bins_for_gpio_bits[24]	auto[1]	auto[0]	281303	1			T1	49		T11	22		T12	4693
bins_for_gpio_bits[24]	auto[1]	auto[1]	6021720	1			T22	430		T1	1160		T11	141
bins_for_gpio_bits[25]	auto[0]	auto[0]	9249663	1			T22	459		T1	302		T11	552
bins_for_gpio_bits[25]	auto[0]	auto[1]	281996	1			T1	49		T11	18		T12	4697
bins_for_gpio_bits[25]	auto[1]	auto[0]	282211	1			T1	49		T11	18		T12	4697
bins_for_gpio_bits[25]	auto[1]	auto[1]	6052418	1			T22	498		T1	1171		T11	126
bins_for_gpio_bits[26]	auto[0]	auto[0]	9268714	1			T22	447		T1	354		T11	521
bins_for_gpio_bits[26]	auto[0]	auto[1]	281631	1			T1	61		T11	20		T12	4792
bins_for_gpio_bits[26]	auto[1]	auto[0]	281909	1			T1	60		T11	20		T12	4792
bins_for_gpio_bits[26]	auto[1]	auto[1]	6034034	1			T22	510		T1	1096		T11	153
bins_for_gpio_bits[27]	auto[0]	auto[0]	9286582	1			T22	432		T1	300		T11	550
bins_for_gpio_bits[27]	auto[0]	auto[1]	281824	1			T1	45		T11	16		T12	4821
bins_for_gpio_bits[27]	auto[1]	auto[0]	282058	1			T1	45		T11	16		T12	4821
bins_for_gpio_bits[27]	auto[1]	auto[1]	6015824	1			T22	525		T1	1181		T11	132
bins_for_gpio_bits[28]	auto[0]	auto[0]	9264363	1			T22	470		T1	478		T11	493
bins_for_gpio_bits[28]	auto[0]	auto[1]	281981	1			T1	58		T11	21		T12	4782
bins_for_gpio_bits[28]	auto[1]	auto[0]	282247	1			T1	57		T11	21		T12	4783
bins_for_gpio_bits[28]	auto[1]	auto[1]	6037697	1			T22	487		T1	978		T11	179
bins_for_gpio_bits[29]	auto[0]	auto[0]	9276956	1			T22	440		T1	290		T11	506
bins_for_gpio_bits[29]	auto[0]	auto[1]	281754	1			T1	51		T11	18		T12	4716
bins_for_gpio_bits[29]	auto[1]	auto[0]	282017	1			T1	51		T11	18		T12	4716
bins_for_gpio_bits[29]	auto[1]	auto[1]	6025561	1			T22	517		T1	1179		T11	172
bins_for_gpio_bits[30]	auto[0]	auto[0]	9269224	1			T22	509		T1	267		T11	516
bins_for_gpio_bits[30]	auto[0]	auto[1]	281542	1			T1	45		T11	22		T12	4734
bins_for_gpio_bits[30]	auto[1]	auto[0]	281802	1			T1	44		T11	22		T12	4735
bins_for_gpio_bits[30]	auto[1]	auto[1]	6033720	1			T22	448		T1	1215		T11	154
bins_for_gpio_bits[31]	auto[0]	auto[0]	9258225	1			T22	443		T1	310		T11	488
bins_for_gpio_bits[31]	auto[0]	auto[1]	281949	1			T1	46		T11	25		T12	4793
bins_for_gpio_bits[31]	auto[1]	auto[0]	282155	1			T1	45		T11	25		T12	4793
bins_for_gpio_bits[31]	auto[1]	auto[1]	6043959	1			T22	514		T1	1170		T11	176