Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9190210 |
1 |
|
|
T22 |
957 |
|
T1 |
1010 |
|
T11 |
363 |
| auto[1] |
6966270 |
1 |
|
|
T1 |
659 |
|
T12 |
126555 |
|
T14 |
953 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15254802 |
1 |
|
|
T22 |
957 |
|
T1 |
1634 |
|
T11 |
363 |
| auto[1] |
901678 |
1 |
|
|
T1 |
35 |
|
T12 |
17570 |
|
T14 |
197 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9181186 |
1 |
|
|
T22 |
957 |
|
T1 |
742 |
|
T11 |
363 |
| auto[1] |
6975294 |
1 |
|
|
T1 |
927 |
|
T12 |
130027 |
|
T14 |
1143 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3030785 |
1 |
|
|
T1 |
533 |
|
T12 |
59723 |
|
T14 |
565 |
| auto[1] |
auto[0] |
auto[1] |
449085 |
1 |
|
|
T1 |
19 |
|
T12 |
9435 |
|
T14 |
113 |
| auto[1] |
auto[1] |
auto[0] |
3042831 |
1 |
|
|
T1 |
359 |
|
T12 |
52734 |
|
T14 |
381 |
| auto[1] |
auto[1] |
auto[1] |
452593 |
1 |
|
|
T1 |
16 |
|
T12 |
8135 |
|
T14 |
84 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9202537 |
1 |
|
|
T22 |
957 |
|
T1 |
861 |
|
T11 |
363 |
| auto[1] |
6953943 |
1 |
|
|
T1 |
808 |
|
T12 |
130590 |
|
T14 |
1158 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15256521 |
1 |
|
|
T22 |
957 |
|
T1 |
1631 |
|
T11 |
363 |
| auto[1] |
899959 |
1 |
|
|
T1 |
38 |
|
T12 |
17864 |
|
T14 |
218 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9181047 |
1 |
|
|
T22 |
957 |
|
T1 |
713 |
|
T11 |
363 |
| auto[1] |
6975433 |
1 |
|
|
T1 |
956 |
|
T12 |
131770 |
|
T14 |
1249 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3052629 |
1 |
|
|
T1 |
451 |
|
T12 |
59028 |
|
T14 |
534 |
| auto[1] |
auto[0] |
auto[1] |
453171 |
1 |
|
|
T1 |
21 |
|
T12 |
9122 |
|
T14 |
119 |
| auto[1] |
auto[1] |
auto[0] |
3022845 |
1 |
|
|
T1 |
467 |
|
T12 |
54878 |
|
T14 |
497 |
| auto[1] |
auto[1] |
auto[1] |
446788 |
1 |
|
|
T1 |
17 |
|
T12 |
8742 |
|
T14 |
99 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9207743 |
1 |
|
|
T22 |
957 |
|
T1 |
1087 |
|
T11 |
363 |
| auto[1] |
6948737 |
1 |
|
|
T1 |
582 |
|
T12 |
127882 |
|
T14 |
1204 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15259750 |
1 |
|
|
T22 |
957 |
|
T1 |
1633 |
|
T11 |
363 |
| auto[1] |
896730 |
1 |
|
|
T1 |
36 |
|
T12 |
17792 |
|
T14 |
236 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9198310 |
1 |
|
|
T22 |
957 |
|
T1 |
913 |
|
T11 |
363 |
| auto[1] |
6958170 |
1 |
|
|
T1 |
756 |
|
T12 |
130736 |
|
T14 |
1268 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3060775 |
1 |
|
|
T1 |
451 |
|
T12 |
60552 |
|
T14 |
455 |
| auto[1] |
auto[0] |
auto[1] |
453936 |
1 |
|
|
T1 |
26 |
|
T12 |
9781 |
|
T14 |
104 |
| auto[1] |
auto[1] |
auto[0] |
3000665 |
1 |
|
|
T1 |
269 |
|
T12 |
52392 |
|
T14 |
577 |
| auto[1] |
auto[1] |
auto[1] |
442794 |
1 |
|
|
T1 |
10 |
|
T12 |
8011 |
|
T14 |
132 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9193959 |
1 |
|
|
T22 |
957 |
|
T1 |
882 |
|
T11 |
363 |
| auto[1] |
6962521 |
1 |
|
|
T1 |
787 |
|
T12 |
132143 |
|
T14 |
1203 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15265611 |
1 |
|
|
T22 |
957 |
|
T1 |
1642 |
|
T11 |
363 |
| auto[1] |
890869 |
1 |
|
|
T1 |
27 |
|
T12 |
17549 |
|
T14 |
248 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9235955 |
1 |
|
|
T22 |
957 |
|
T1 |
783 |
|
T11 |
363 |
| auto[1] |
6920525 |
1 |
|
|
T1 |
886 |
|
T12 |
131172 |
|
T14 |
1396 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3016702 |
1 |
|
|
T1 |
512 |
|
T12 |
57579 |
|
T14 |
502 |
| auto[1] |
auto[0] |
auto[1] |
445630 |
1 |
|
|
T1 |
18 |
|
T12 |
8973 |
|
T14 |
113 |
| auto[1] |
auto[1] |
auto[0] |
3012954 |
1 |
|
|
T1 |
347 |
|
T12 |
56044 |
|
T14 |
646 |
| auto[1] |
auto[1] |
auto[1] |
445239 |
1 |
|
|
T1 |
9 |
|
T12 |
8576 |
|
T14 |
135 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9203179 |
1 |
|
|
T22 |
957 |
|
T1 |
918 |
|
T11 |
363 |
| auto[1] |
6953301 |
1 |
|
|
T1 |
751 |
|
T12 |
134490 |
|
T14 |
1379 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15252550 |
1 |
|
|
T22 |
957 |
|
T1 |
1640 |
|
T11 |
363 |
| auto[1] |
903930 |
1 |
|
|
T1 |
29 |
|
T12 |
16845 |
|
T14 |
226 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9158825 |
1 |
|
|
T22 |
957 |
|
T1 |
893 |
|
T11 |
363 |
| auto[1] |
6997655 |
1 |
|
|
T1 |
776 |
|
T12 |
125179 |
|
T14 |
1213 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3058221 |
1 |
|
|
T1 |
396 |
|
T12 |
53336 |
|
T14 |
385 |
| auto[1] |
auto[0] |
auto[1] |
453602 |
1 |
|
|
T1 |
16 |
|
T12 |
8257 |
|
T14 |
90 |
| auto[1] |
auto[1] |
auto[0] |
3035504 |
1 |
|
|
T1 |
351 |
|
T12 |
54998 |
|
T14 |
602 |
| auto[1] |
auto[1] |
auto[1] |
450328 |
1 |
|
|
T1 |
13 |
|
T12 |
8588 |
|
T14 |
136 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9204467 |
1 |
|
|
T22 |
957 |
|
T1 |
790 |
|
T11 |
363 |
| auto[1] |
6952013 |
1 |
|
|
T1 |
879 |
|
T12 |
124790 |
|
T14 |
1241 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15259616 |
1 |
|
|
T22 |
957 |
|
T1 |
1632 |
|
T11 |
363 |
| auto[1] |
896864 |
1 |
|
|
T1 |
37 |
|
T12 |
17411 |
|
T14 |
138 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9204617 |
1 |
|
|
T22 |
957 |
|
T1 |
724 |
|
T11 |
363 |
| auto[1] |
6951863 |
1 |
|
|
T1 |
945 |
|
T12 |
129161 |
|
T14 |
714 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3041367 |
1 |
|
|
T1 |
479 |
|
T12 |
59925 |
|
T14 |
289 |
| auto[1] |
auto[0] |
auto[1] |
451660 |
1 |
|
|
T1 |
22 |
|
T12 |
9500 |
|
T14 |
62 |
| auto[1] |
auto[1] |
auto[0] |
3013632 |
1 |
|
|
T1 |
429 |
|
T12 |
51825 |
|
T14 |
287 |
| auto[1] |
auto[1] |
auto[1] |
445204 |
1 |
|
|
T1 |
15 |
|
T12 |
7911 |
|
T14 |
76 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9174776 |
1 |
|
|
T22 |
957 |
|
T1 |
864 |
|
T11 |
363 |
| auto[1] |
6981704 |
1 |
|
|
T1 |
805 |
|
T12 |
125427 |
|
T14 |
1216 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15257299 |
1 |
|
|
T22 |
957 |
|
T1 |
1646 |
|
T11 |
363 |
| auto[1] |
899181 |
1 |
|
|
T1 |
23 |
|
T12 |
18455 |
|
T14 |
256 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9180688 |
1 |
|
|
T22 |
957 |
|
T1 |
889 |
|
T11 |
363 |
| auto[1] |
6975792 |
1 |
|
|
T1 |
780 |
|
T12 |
135227 |
|
T14 |
1292 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3033273 |
1 |
|
|
T1 |
371 |
|
T12 |
58083 |
|
T14 |
524 |
| auto[1] |
auto[0] |
auto[1] |
448619 |
1 |
|
|
T1 |
8 |
|
T12 |
9117 |
|
T14 |
132 |
| auto[1] |
auto[1] |
auto[0] |
3043338 |
1 |
|
|
T1 |
386 |
|
T12 |
58689 |
|
T14 |
512 |
| auto[1] |
auto[1] |
auto[1] |
450562 |
1 |
|
|
T1 |
15 |
|
T12 |
9338 |
|
T14 |
124 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9218291 |
1 |
|
|
T22 |
957 |
|
T1 |
974 |
|
T11 |
363 |
| auto[1] |
6938189 |
1 |
|
|
T1 |
695 |
|
T12 |
128428 |
|
T14 |
1294 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15260091 |
1 |
|
|
T22 |
957 |
|
T1 |
1633 |
|
T11 |
363 |
| auto[1] |
896389 |
1 |
|
|
T1 |
36 |
|
T12 |
17122 |
|
T14 |
203 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9200815 |
1 |
|
|
T22 |
957 |
|
T1 |
813 |
|
T11 |
363 |
| auto[1] |
6955665 |
1 |
|
|
T1 |
856 |
|
T12 |
127989 |
|
T14 |
1115 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3052017 |
1 |
|
|
T1 |
485 |
|
T12 |
55842 |
|
T14 |
427 |
| auto[1] |
auto[0] |
auto[1] |
452485 |
1 |
|
|
T1 |
22 |
|
T12 |
8627 |
|
T14 |
89 |
| auto[1] |
auto[1] |
auto[0] |
3007259 |
1 |
|
|
T1 |
335 |
|
T12 |
55025 |
|
T14 |
485 |
| auto[1] |
auto[1] |
auto[1] |
443904 |
1 |
|
|
T1 |
14 |
|
T12 |
8495 |
|
T14 |
114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9195946 |
1 |
|
|
T22 |
957 |
|
T1 |
921 |
|
T11 |
363 |
| auto[1] |
6960534 |
1 |
|
|
T1 |
748 |
|
T12 |
128343 |
|
T14 |
1547 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15253506 |
1 |
|
|
T22 |
957 |
|
T1 |
1640 |
|
T11 |
363 |
| auto[1] |
902974 |
1 |
|
|
T1 |
29 |
|
T12 |
16834 |
|
T14 |
184 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9163873 |
1 |
|
|
T22 |
957 |
|
T1 |
773 |
|
T11 |
363 |
| auto[1] |
6992607 |
1 |
|
|
T1 |
896 |
|
T12 |
126808 |
|
T14 |
1034 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3043398 |
1 |
|
|
T1 |
477 |
|
T12 |
54006 |
|
T14 |
297 |
| auto[1] |
auto[0] |
auto[1] |
451667 |
1 |
|
|
T1 |
19 |
|
T12 |
8304 |
|
T14 |
65 |
| auto[1] |
auto[1] |
auto[0] |
3046235 |
1 |
|
|
T1 |
390 |
|
T12 |
55968 |
|
T14 |
553 |
| auto[1] |
auto[1] |
auto[1] |
451307 |
1 |
|
|
T1 |
10 |
|
T12 |
8530 |
|
T14 |
119 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9183111 |
1 |
|
|
T22 |
957 |
|
T1 |
809 |
|
T11 |
363 |
| auto[1] |
6973369 |
1 |
|
|
T1 |
860 |
|
T12 |
131062 |
|
T14 |
1157 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15253717 |
1 |
|
|
T22 |
957 |
|
T1 |
1642 |
|
T11 |
363 |
| auto[1] |
902763 |
1 |
|
|
T1 |
27 |
|
T12 |
18267 |
|
T14 |
195 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9163655 |
1 |
|
|
T22 |
957 |
|
T1 |
910 |
|
T11 |
363 |
| auto[1] |
6992825 |
1 |
|
|
T1 |
759 |
|
T12 |
134423 |
|
T14 |
1092 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3051066 |
1 |
|
|
T1 |
311 |
|
T12 |
59068 |
|
T14 |
545 |
| auto[1] |
auto[0] |
auto[1] |
450973 |
1 |
|
|
T1 |
14 |
|
T12 |
9322 |
|
T14 |
120 |
| auto[1] |
auto[1] |
auto[0] |
3038996 |
1 |
|
|
T1 |
421 |
|
T12 |
57088 |
|
T14 |
352 |
| auto[1] |
auto[1] |
auto[1] |
451790 |
1 |
|
|
T1 |
13 |
|
T12 |
8945 |
|
T14 |
75 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9183167 |
1 |
|
|
T22 |
957 |
|
T1 |
873 |
|
T11 |
363 |
| auto[1] |
6973313 |
1 |
|
|
T1 |
796 |
|
T12 |
129202 |
|
T14 |
1266 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15262213 |
1 |
|
|
T22 |
957 |
|
T1 |
1629 |
|
T11 |
363 |
| auto[1] |
894267 |
1 |
|
|
T1 |
40 |
|
T12 |
18154 |
|
T14 |
248 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9220437 |
1 |
|
|
T22 |
957 |
|
T1 |
534 |
|
T11 |
363 |
| auto[1] |
6936043 |
1 |
|
|
T1 |
1135 |
|
T12 |
134227 |
|
T14 |
1287 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3025471 |
1 |
|
|
T1 |
548 |
|
T12 |
58440 |
|
T14 |
503 |
| auto[1] |
auto[0] |
auto[1] |
447102 |
1 |
|
|
T1 |
21 |
|
T12 |
9107 |
|
T14 |
116 |
| auto[1] |
auto[1] |
auto[0] |
3016305 |
1 |
|
|
T1 |
547 |
|
T12 |
57633 |
|
T14 |
536 |
| auto[1] |
auto[1] |
auto[1] |
447165 |
1 |
|
|
T1 |
19 |
|
T12 |
9047 |
|
T14 |
132 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9235688 |
1 |
|
|
T22 |
957 |
|
T1 |
872 |
|
T11 |
363 |
| auto[1] |
6920792 |
1 |
|
|
T1 |
797 |
|
T12 |
130665 |
|
T14 |
1237 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15260324 |
1 |
|
|
T22 |
957 |
|
T1 |
1636 |
|
T11 |
363 |
| auto[1] |
896156 |
1 |
|
|
T1 |
33 |
|
T12 |
18360 |
|
T14 |
254 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9193154 |
1 |
|
|
T22 |
957 |
|
T1 |
667 |
|
T11 |
363 |
| auto[1] |
6963326 |
1 |
|
|
T1 |
1002 |
|
T12 |
135325 |
|
T14 |
1313 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3061869 |
1 |
|
|
T1 |
508 |
|
T12 |
58258 |
|
T14 |
461 |
| auto[1] |
auto[0] |
auto[1] |
452904 |
1 |
|
|
T1 |
13 |
|
T12 |
9217 |
|
T14 |
116 |
| auto[1] |
auto[1] |
auto[0] |
3005301 |
1 |
|
|
T1 |
461 |
|
T12 |
58707 |
|
T14 |
598 |
| auto[1] |
auto[1] |
auto[1] |
443252 |
1 |
|
|
T1 |
20 |
|
T12 |
9143 |
|
T14 |
138 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9172208 |
1 |
|
|
T22 |
957 |
|
T1 |
829 |
|
T11 |
363 |
| auto[1] |
6984272 |
1 |
|
|
T1 |
840 |
|
T12 |
126384 |
|
T14 |
1099 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15264389 |
1 |
|
|
T22 |
957 |
|
T1 |
1633 |
|
T11 |
363 |
| auto[1] |
892091 |
1 |
|
|
T1 |
36 |
|
T12 |
16801 |
|
T14 |
229 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9226439 |
1 |
|
|
T22 |
957 |
|
T1 |
761 |
|
T11 |
363 |
| auto[1] |
6930041 |
1 |
|
|
T1 |
908 |
|
T12 |
127105 |
|
T14 |
1234 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3007976 |
1 |
|
|
T1 |
495 |
|
T12 |
55731 |
|
T14 |
655 |
| auto[1] |
auto[0] |
auto[1] |
444478 |
1 |
|
|
T1 |
28 |
|
T12 |
8581 |
|
T14 |
160 |
| auto[1] |
auto[1] |
auto[0] |
3029974 |
1 |
|
|
T1 |
377 |
|
T12 |
54573 |
|
T14 |
350 |
| auto[1] |
auto[1] |
auto[1] |
447613 |
1 |
|
|
T1 |
8 |
|
T12 |
8220 |
|
T14 |
69 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9165090 |
1 |
|
|
T22 |
957 |
|
T1 |
745 |
|
T11 |
363 |
| auto[1] |
6991390 |
1 |
|
|
T1 |
924 |
|
T12 |
127191 |
|
T14 |
1211 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15263802 |
1 |
|
|
T22 |
957 |
|
T1 |
1647 |
|
T11 |
363 |
| auto[1] |
892678 |
1 |
|
|
T1 |
22 |
|
T12 |
16743 |
|
T14 |
259 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9218312 |
1 |
|
|
T22 |
957 |
|
T1 |
892 |
|
T11 |
363 |
| auto[1] |
6938168 |
1 |
|
|
T1 |
777 |
|
T12 |
125680 |
|
T14 |
1373 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3030828 |
1 |
|
|
T1 |
351 |
|
T12 |
56557 |
|
T14 |
509 |
| auto[1] |
auto[0] |
auto[1] |
447300 |
1 |
|
|
T1 |
11 |
|
T12 |
8747 |
|
T14 |
123 |
| auto[1] |
auto[1] |
auto[0] |
3014662 |
1 |
|
|
T1 |
404 |
|
T12 |
52380 |
|
T14 |
605 |
| auto[1] |
auto[1] |
auto[1] |
445378 |
1 |
|
|
T1 |
11 |
|
T12 |
7996 |
|
T14 |
136 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9238305 |
1 |
|
|
T22 |
957 |
|
T1 |
824 |
|
T11 |
363 |
| auto[1] |
6918175 |
1 |
|
|
T1 |
845 |
|
T12 |
131524 |
|
T14 |
1048 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15258825 |
1 |
|
|
T22 |
957 |
|
T1 |
1637 |
|
T11 |
363 |
| auto[1] |
897655 |
1 |
|
|
T1 |
32 |
|
T12 |
17120 |
|
T14 |
320 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9190799 |
1 |
|
|
T22 |
957 |
|
T1 |
845 |
|
T11 |
363 |
| auto[1] |
6965681 |
1 |
|
|
T1 |
824 |
|
T12 |
126461 |
|
T14 |
1659 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3065363 |
1 |
|
|
T1 |
373 |
|
T12 |
53608 |
|
T14 |
836 |
| auto[1] |
auto[0] |
auto[1] |
453832 |
1 |
|
|
T1 |
17 |
|
T12 |
8255 |
|
T14 |
202 |
| auto[1] |
auto[1] |
auto[0] |
3002663 |
1 |
|
|
T1 |
419 |
|
T12 |
55733 |
|
T14 |
503 |
| auto[1] |
auto[1] |
auto[1] |
443823 |
1 |
|
|
T1 |
15 |
|
T12 |
8865 |
|
T14 |
118 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9182181 |
1 |
|
|
T22 |
957 |
|
T1 |
916 |
|
T11 |
363 |
| auto[1] |
6974299 |
1 |
|
|
T1 |
753 |
|
T12 |
128715 |
|
T14 |
1548 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15257168 |
1 |
|
|
T22 |
957 |
|
T1 |
1623 |
|
T11 |
363 |
| auto[1] |
899312 |
1 |
|
|
T1 |
46 |
|
T12 |
17670 |
|
T14 |
245 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9183262 |
1 |
|
|
T22 |
957 |
|
T1 |
883 |
|
T11 |
363 |
| auto[1] |
6973218 |
1 |
|
|
T1 |
786 |
|
T12 |
131187 |
|
T14 |
1348 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3029010 |
1 |
|
|
T1 |
370 |
|
T12 |
56103 |
|
T14 |
417 |
| auto[1] |
auto[0] |
auto[1] |
447917 |
1 |
|
|
T1 |
18 |
|
T12 |
8876 |
|
T14 |
97 |
| auto[1] |
auto[1] |
auto[0] |
3044896 |
1 |
|
|
T1 |
370 |
|
T12 |
57414 |
|
T14 |
686 |
| auto[1] |
auto[1] |
auto[1] |
451395 |
1 |
|
|
T1 |
28 |
|
T12 |
8794 |
|
T14 |
148 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9166203 |
1 |
|
|
T22 |
957 |
|
T1 |
843 |
|
T11 |
363 |
| auto[1] |
6990277 |
1 |
|
|
T1 |
826 |
|
T12 |
125805 |
|
T14 |
1322 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15257918 |
1 |
|
|
T22 |
957 |
|
T1 |
1637 |
|
T11 |
363 |
| auto[1] |
898562 |
1 |
|
|
T1 |
32 |
|
T12 |
17451 |
|
T14 |
269 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9191641 |
1 |
|
|
T22 |
957 |
|
T1 |
899 |
|
T11 |
363 |
| auto[1] |
6964839 |
1 |
|
|
T1 |
770 |
|
T12 |
128815 |
|
T14 |
1428 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3030538 |
1 |
|
|
T1 |
373 |
|
T12 |
55996 |
|
T14 |
472 |
| auto[1] |
auto[0] |
auto[1] |
447767 |
1 |
|
|
T1 |
16 |
|
T12 |
8875 |
|
T14 |
105 |
| auto[1] |
auto[1] |
auto[0] |
3035739 |
1 |
|
|
T1 |
365 |
|
T12 |
55368 |
|
T14 |
687 |
| auto[1] |
auto[1] |
auto[1] |
450795 |
1 |
|
|
T1 |
16 |
|
T12 |
8576 |
|
T14 |
164 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9216277 |
1 |
|
|
T22 |
957 |
|
T1 |
983 |
|
T11 |
363 |
| auto[1] |
6940203 |
1 |
|
|
T1 |
686 |
|
T12 |
126896 |
|
T14 |
1302 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15258336 |
1 |
|
|
T22 |
957 |
|
T1 |
1642 |
|
T11 |
363 |
| auto[1] |
898144 |
1 |
|
|
T1 |
27 |
|
T12 |
17697 |
|
T14 |
296 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9200911 |
1 |
|
|
T22 |
957 |
|
T1 |
949 |
|
T11 |
363 |
| auto[1] |
6955569 |
1 |
|
|
T1 |
720 |
|
T12 |
131920 |
|
T14 |
1540 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3029597 |
1 |
|
|
T1 |
421 |
|
T12 |
56070 |
|
T14 |
552 |
| auto[1] |
auto[0] |
auto[1] |
450053 |
1 |
|
|
T1 |
16 |
|
T12 |
8543 |
|
T14 |
131 |
| auto[1] |
auto[1] |
auto[0] |
3027828 |
1 |
|
|
T1 |
272 |
|
T12 |
58153 |
|
T14 |
692 |
| auto[1] |
auto[1] |
auto[1] |
448091 |
1 |
|
|
T1 |
11 |
|
T12 |
9154 |
|
T14 |
165 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9169489 |
1 |
|
|
T22 |
957 |
|
T1 |
916 |
|
T11 |
363 |
| auto[1] |
6986991 |
1 |
|
|
T1 |
753 |
|
T12 |
133031 |
|
T14 |
1294 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15259409 |
1 |
|
|
T22 |
957 |
|
T1 |
1642 |
|
T11 |
363 |
| auto[1] |
897071 |
1 |
|
|
T1 |
27 |
|
T12 |
17239 |
|
T14 |
225 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9200967 |
1 |
|
|
T22 |
957 |
|
T1 |
1019 |
|
T11 |
363 |
| auto[1] |
6955513 |
1 |
|
|
T1 |
650 |
|
T12 |
128747 |
|
T14 |
1149 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3039804 |
1 |
|
|
T1 |
362 |
|
T12 |
56358 |
|
T14 |
523 |
| auto[1] |
auto[0] |
auto[1] |
450557 |
1 |
|
|
T1 |
16 |
|
T12 |
8735 |
|
T14 |
127 |
| auto[1] |
auto[1] |
auto[0] |
3018638 |
1 |
|
|
T1 |
261 |
|
T12 |
55150 |
|
T14 |
401 |
| auto[1] |
auto[1] |
auto[1] |
446514 |
1 |
|
|
T1 |
11 |
|
T12 |
8504 |
|
T14 |
98 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |