Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9208459 |
1 |
|
|
T22 |
957 |
|
T1 |
949 |
|
T11 |
363 |
| auto[1] |
6948021 |
1 |
|
|
T1 |
720 |
|
T12 |
128771 |
|
T14 |
1212 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15261770 |
1 |
|
|
T22 |
957 |
|
T1 |
1635 |
|
T11 |
363 |
| auto[1] |
894710 |
1 |
|
|
T1 |
34 |
|
T12 |
17430 |
|
T14 |
243 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9215928 |
1 |
|
|
T22 |
957 |
|
T1 |
952 |
|
T11 |
363 |
| auto[1] |
6940552 |
1 |
|
|
T1 |
717 |
|
T12 |
130144 |
|
T14 |
1356 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3038873 |
1 |
|
|
T1 |
366 |
|
T12 |
56805 |
|
T14 |
592 |
| auto[1] |
auto[0] |
auto[1] |
450685 |
1 |
|
|
T1 |
21 |
|
T12 |
8777 |
|
T14 |
134 |
| auto[1] |
auto[1] |
auto[0] |
3006969 |
1 |
|
|
T1 |
317 |
|
T12 |
55909 |
|
T14 |
521 |
| auto[1] |
auto[1] |
auto[1] |
444025 |
1 |
|
|
T1 |
13 |
|
T12 |
8653 |
|
T14 |
109 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |