Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9218500 |
1 |
|
|
T22 |
957 |
|
T1 |
758 |
|
T11 |
363 |
| auto[1] |
6937980 |
1 |
|
|
T1 |
911 |
|
T12 |
118248 |
|
T14 |
1200 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15261998 |
1 |
|
|
T22 |
957 |
|
T1 |
1634 |
|
T11 |
363 |
| auto[1] |
894482 |
1 |
|
|
T1 |
35 |
|
T12 |
18584 |
|
T14 |
244 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9224391 |
1 |
|
|
T22 |
957 |
|
T1 |
859 |
|
T11 |
363 |
| auto[1] |
6932089 |
1 |
|
|
T1 |
810 |
|
T12 |
135812 |
|
T14 |
1180 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3040174 |
1 |
|
|
T1 |
375 |
|
T12 |
66829 |
|
T14 |
485 |
| auto[1] |
auto[0] |
auto[1] |
451140 |
1 |
|
|
T1 |
20 |
|
T12 |
11011 |
|
T14 |
128 |
| auto[1] |
auto[1] |
auto[0] |
2997433 |
1 |
|
|
T1 |
400 |
|
T12 |
50399 |
|
T14 |
451 |
| auto[1] |
auto[1] |
auto[1] |
443342 |
1 |
|
|
T1 |
15 |
|
T12 |
7573 |
|
T14 |
116 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |