Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9184630 |
1 |
|
|
T22 |
957 |
|
T1 |
789 |
|
T11 |
363 |
| auto[1] |
6971850 |
1 |
|
|
T1 |
880 |
|
T12 |
130986 |
|
T14 |
1278 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15257785 |
1 |
|
|
T22 |
957 |
|
T1 |
1650 |
|
T11 |
363 |
| auto[1] |
898695 |
1 |
|
|
T1 |
19 |
|
T12 |
17456 |
|
T14 |
182 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9198313 |
1 |
|
|
T22 |
957 |
|
T1 |
1047 |
|
T11 |
363 |
| auto[1] |
6958167 |
1 |
|
|
T1 |
622 |
|
T12 |
128667 |
|
T14 |
1006 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3027990 |
1 |
|
|
T1 |
294 |
|
T12 |
57008 |
|
T14 |
294 |
| auto[1] |
auto[0] |
auto[1] |
449176 |
1 |
|
|
T1 |
9 |
|
T12 |
8980 |
|
T14 |
63 |
| auto[1] |
auto[1] |
auto[0] |
3031482 |
1 |
|
|
T1 |
309 |
|
T12 |
54203 |
|
T14 |
530 |
| auto[1] |
auto[1] |
auto[1] |
449519 |
1 |
|
|
T1 |
10 |
|
T12 |
8476 |
|
T14 |
119 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |