Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9220733 |
1 |
|
|
T22 |
957 |
|
T1 |
728 |
|
T11 |
363 |
| auto[1] |
6935747 |
1 |
|
|
T1 |
941 |
|
T12 |
130748 |
|
T14 |
1222 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15260168 |
1 |
|
|
T22 |
957 |
|
T1 |
1637 |
|
T11 |
363 |
| auto[1] |
896312 |
1 |
|
|
T1 |
32 |
|
T12 |
17589 |
|
T14 |
239 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9193121 |
1 |
|
|
T22 |
957 |
|
T1 |
842 |
|
T11 |
363 |
| auto[1] |
6963359 |
1 |
|
|
T1 |
827 |
|
T12 |
128573 |
|
T14 |
1274 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3040528 |
1 |
|
|
T1 |
319 |
|
T12 |
55763 |
|
T14 |
518 |
| auto[1] |
auto[0] |
auto[1] |
449397 |
1 |
|
|
T1 |
19 |
|
T12 |
8875 |
|
T14 |
120 |
| auto[1] |
auto[1] |
auto[0] |
3026519 |
1 |
|
|
T1 |
476 |
|
T12 |
55221 |
|
T14 |
517 |
| auto[1] |
auto[1] |
auto[1] |
446915 |
1 |
|
|
T1 |
13 |
|
T12 |
8714 |
|
T14 |
119 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |