Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9203179 |
1 |
|
|
T22 |
957 |
|
T1 |
918 |
|
T11 |
363 |
| auto[1] |
6953301 |
1 |
|
|
T1 |
751 |
|
T12 |
134490 |
|
T14 |
1379 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13317058 |
1 |
|
|
T22 |
957 |
|
T1 |
1193 |
|
T11 |
363 |
| auto[1] |
2839422 |
1 |
|
|
T1 |
476 |
|
T12 |
48184 |
|
T14 |
606 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9205352 |
1 |
|
|
T22 |
957 |
|
T1 |
1023 |
|
T11 |
363 |
| auto[1] |
6951128 |
1 |
|
|
T1 |
646 |
|
T12 |
123428 |
|
T14 |
1164 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2072088 |
1 |
|
|
T1 |
81 |
|
T12 |
37505 |
|
T14 |
214 |
| auto[1] |
auto[0] |
auto[1] |
1429549 |
1 |
|
|
T1 |
250 |
|
T12 |
24557 |
|
T14 |
191 |
| auto[1] |
auto[1] |
auto[0] |
2039618 |
1 |
|
|
T1 |
89 |
|
T12 |
37739 |
|
T14 |
344 |
| auto[1] |
auto[1] |
auto[1] |
1409873 |
1 |
|
|
T1 |
226 |
|
T12 |
23627 |
|
T14 |
415 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |