Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9199910 |
1 |
|
|
T22 |
957 |
|
T1 |
954 |
|
T11 |
363 |
| auto[1] |
6956570 |
1 |
|
|
T1 |
715 |
|
T12 |
131496 |
|
T14 |
1112 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15256391 |
1 |
|
|
T22 |
957 |
|
T1 |
1625 |
|
T11 |
363 |
| auto[1] |
900089 |
1 |
|
|
T1 |
44 |
|
T12 |
18879 |
|
T14 |
236 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9182365 |
1 |
|
|
T22 |
957 |
|
T1 |
773 |
|
T11 |
363 |
| auto[1] |
6974115 |
1 |
|
|
T1 |
896 |
|
T12 |
138306 |
|
T14 |
1229 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3048065 |
1 |
|
|
T1 |
490 |
|
T12 |
60663 |
|
T14 |
605 |
| auto[1] |
auto[0] |
auto[1] |
452000 |
1 |
|
|
T1 |
28 |
|
T12 |
9568 |
|
T14 |
146 |
| auto[1] |
auto[1] |
auto[0] |
3025961 |
1 |
|
|
T1 |
362 |
|
T12 |
58764 |
|
T14 |
388 |
| auto[1] |
auto[1] |
auto[1] |
448089 |
1 |
|
|
T1 |
16 |
|
T12 |
9311 |
|
T14 |
90 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |