Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9204467 |
1 |
|
|
T22 |
957 |
|
T1 |
790 |
|
T11 |
363 |
| auto[1] |
6952013 |
1 |
|
|
T1 |
879 |
|
T12 |
124790 |
|
T14 |
1241 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13310746 |
1 |
|
|
T22 |
957 |
|
T1 |
1039 |
|
T11 |
363 |
| auto[1] |
2845734 |
1 |
|
|
T1 |
630 |
|
T12 |
49508 |
|
T14 |
761 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9198175 |
1 |
|
|
T22 |
957 |
|
T1 |
865 |
|
T11 |
363 |
| auto[1] |
6958305 |
1 |
|
|
T1 |
804 |
|
T12 |
130305 |
|
T14 |
1517 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2052267 |
1 |
|
|
T1 |
78 |
|
T12 |
40845 |
|
T14 |
382 |
| auto[1] |
auto[0] |
auto[1] |
1425977 |
1 |
|
|
T1 |
287 |
|
T12 |
25146 |
|
T14 |
375 |
| auto[1] |
auto[1] |
auto[0] |
2060304 |
1 |
|
|
T1 |
96 |
|
T12 |
39952 |
|
T14 |
374 |
| auto[1] |
auto[1] |
auto[1] |
1419757 |
1 |
|
|
T1 |
343 |
|
T12 |
24362 |
|
T14 |
386 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |