Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9174776 |
1 |
|
|
T22 |
957 |
|
T1 |
864 |
|
T11 |
363 |
| auto[1] |
6981704 |
1 |
|
|
T1 |
805 |
|
T12 |
125427 |
|
T14 |
1216 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13306117 |
1 |
|
|
T22 |
957 |
|
T1 |
957 |
|
T11 |
363 |
| auto[1] |
2850363 |
1 |
|
|
T1 |
712 |
|
T12 |
48708 |
|
T14 |
681 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9190405 |
1 |
|
|
T22 |
957 |
|
T1 |
799 |
|
T11 |
363 |
| auto[1] |
6966075 |
1 |
|
|
T1 |
870 |
|
T12 |
126614 |
|
T14 |
1343 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2059468 |
1 |
|
|
T1 |
47 |
|
T12 |
39659 |
|
T14 |
377 |
| auto[1] |
auto[0] |
auto[1] |
1425296 |
1 |
|
|
T1 |
388 |
|
T12 |
24791 |
|
T14 |
386 |
| auto[1] |
auto[1] |
auto[0] |
2056244 |
1 |
|
|
T1 |
111 |
|
T12 |
38247 |
|
T14 |
285 |
| auto[1] |
auto[1] |
auto[1] |
1425067 |
1 |
|
|
T1 |
324 |
|
T12 |
23917 |
|
T14 |
295 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |