Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9195946 |
1 |
|
|
T22 |
957 |
|
T1 |
921 |
|
T11 |
363 |
| auto[1] |
6960534 |
1 |
|
|
T1 |
748 |
|
T12 |
128343 |
|
T14 |
1547 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13312723 |
1 |
|
|
T22 |
957 |
|
T1 |
1070 |
|
T11 |
363 |
| auto[1] |
2843757 |
1 |
|
|
T1 |
599 |
|
T12 |
50227 |
|
T14 |
505 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9193461 |
1 |
|
|
T22 |
957 |
|
T1 |
906 |
|
T11 |
363 |
| auto[1] |
6963019 |
1 |
|
|
T1 |
763 |
|
T12 |
130675 |
|
T14 |
1026 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2073234 |
1 |
|
|
T1 |
83 |
|
T12 |
41742 |
|
T14 |
182 |
| auto[1] |
auto[0] |
auto[1] |
1425019 |
1 |
|
|
T1 |
296 |
|
T12 |
25792 |
|
T14 |
167 |
| auto[1] |
auto[1] |
auto[0] |
2046028 |
1 |
|
|
T1 |
81 |
|
T12 |
38706 |
|
T14 |
339 |
| auto[1] |
auto[1] |
auto[1] |
1418738 |
1 |
|
|
T1 |
303 |
|
T12 |
24435 |
|
T14 |
338 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |