Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9183111 |
1 |
|
|
T22 |
957 |
|
T1 |
809 |
|
T11 |
363 |
| auto[1] |
6973369 |
1 |
|
|
T1 |
860 |
|
T12 |
131062 |
|
T14 |
1157 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13305637 |
1 |
|
|
T22 |
957 |
|
T1 |
1174 |
|
T11 |
363 |
| auto[1] |
2850843 |
1 |
|
|
T1 |
495 |
|
T12 |
50869 |
|
T14 |
732 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9204437 |
1 |
|
|
T22 |
957 |
|
T1 |
963 |
|
T11 |
363 |
| auto[1] |
6952043 |
1 |
|
|
T1 |
706 |
|
T12 |
129475 |
|
T14 |
1436 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2058429 |
1 |
|
|
T1 |
108 |
|
T12 |
39030 |
|
T14 |
317 |
| auto[1] |
auto[0] |
auto[1] |
1432242 |
1 |
|
|
T1 |
226 |
|
T12 |
25050 |
|
T14 |
338 |
| auto[1] |
auto[1] |
auto[0] |
2042771 |
1 |
|
|
T1 |
103 |
|
T12 |
39576 |
|
T14 |
387 |
| auto[1] |
auto[1] |
auto[1] |
1418601 |
1 |
|
|
T1 |
269 |
|
T12 |
25819 |
|
T14 |
394 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |