Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9183167 |
1 |
|
|
T22 |
957 |
|
T1 |
873 |
|
T11 |
363 |
| auto[1] |
6973313 |
1 |
|
|
T1 |
796 |
|
T12 |
129202 |
|
T14 |
1266 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13303626 |
1 |
|
|
T22 |
957 |
|
T1 |
1206 |
|
T11 |
363 |
| auto[1] |
2852854 |
1 |
|
|
T1 |
463 |
|
T12 |
50186 |
|
T14 |
734 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9170688 |
1 |
|
|
T22 |
957 |
|
T1 |
942 |
|
T11 |
363 |
| auto[1] |
6985792 |
1 |
|
|
T1 |
727 |
|
T12 |
129275 |
|
T14 |
1396 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2071331 |
1 |
|
|
T1 |
133 |
|
T12 |
38901 |
|
T14 |
337 |
| auto[1] |
auto[0] |
auto[1] |
1427971 |
1 |
|
|
T1 |
208 |
|
T12 |
25217 |
|
T14 |
361 |
| auto[1] |
auto[1] |
auto[0] |
2061607 |
1 |
|
|
T1 |
131 |
|
T12 |
40188 |
|
T14 |
325 |
| auto[1] |
auto[1] |
auto[1] |
1424883 |
1 |
|
|
T1 |
255 |
|
T12 |
24969 |
|
T14 |
373 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |