Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9235688 |
1 |
|
|
T22 |
957 |
|
T1 |
872 |
|
T11 |
363 |
| auto[1] |
6920792 |
1 |
|
|
T1 |
797 |
|
T12 |
130665 |
|
T14 |
1237 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13305474 |
1 |
|
|
T22 |
957 |
|
T1 |
1015 |
|
T11 |
363 |
| auto[1] |
2851006 |
1 |
|
|
T1 |
654 |
|
T12 |
50770 |
|
T14 |
677 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9188349 |
1 |
|
|
T22 |
957 |
|
T1 |
811 |
|
T11 |
363 |
| auto[1] |
6968131 |
1 |
|
|
T1 |
858 |
|
T12 |
130359 |
|
T14 |
1420 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2075651 |
1 |
|
|
T1 |
109 |
|
T12 |
40367 |
|
T14 |
378 |
| auto[1] |
auto[0] |
auto[1] |
1430924 |
1 |
|
|
T1 |
414 |
|
T12 |
25186 |
|
T14 |
344 |
| auto[1] |
auto[1] |
auto[0] |
2041474 |
1 |
|
|
T1 |
95 |
|
T12 |
39222 |
|
T14 |
365 |
| auto[1] |
auto[1] |
auto[1] |
1420082 |
1 |
|
|
T1 |
240 |
|
T12 |
25584 |
|
T14 |
333 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |