Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9172208 |
1 |
|
|
T22 |
957 |
|
T1 |
829 |
|
T11 |
363 |
| auto[1] |
6984272 |
1 |
|
|
T1 |
840 |
|
T12 |
126384 |
|
T14 |
1099 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13299424 |
1 |
|
|
T22 |
957 |
|
T1 |
838 |
|
T11 |
363 |
| auto[1] |
2857056 |
1 |
|
|
T1 |
831 |
|
T12 |
51853 |
|
T14 |
638 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9154306 |
1 |
|
|
T22 |
957 |
|
T1 |
668 |
|
T11 |
363 |
| auto[1] |
7002174 |
1 |
|
|
T1 |
1001 |
|
T12 |
135795 |
|
T14 |
1223 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2059298 |
1 |
|
|
T1 |
104 |
|
T12 |
45958 |
|
T14 |
288 |
| auto[1] |
auto[0] |
auto[1] |
1422570 |
1 |
|
|
T1 |
468 |
|
T12 |
27957 |
|
T14 |
341 |
| auto[1] |
auto[1] |
auto[0] |
2085820 |
1 |
|
|
T1 |
66 |
|
T12 |
37984 |
|
T14 |
297 |
| auto[1] |
auto[1] |
auto[1] |
1434486 |
1 |
|
|
T1 |
363 |
|
T12 |
23896 |
|
T14 |
297 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |