Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9238305 |
1 |
|
|
T22 |
957 |
|
T1 |
824 |
|
T11 |
363 |
| auto[1] |
6918175 |
1 |
|
|
T1 |
845 |
|
T12 |
131524 |
|
T14 |
1048 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13320065 |
1 |
|
|
T22 |
957 |
|
T1 |
1042 |
|
T11 |
363 |
| auto[1] |
2836415 |
1 |
|
|
T1 |
627 |
|
T12 |
50169 |
|
T14 |
726 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9206562 |
1 |
|
|
T22 |
957 |
|
T1 |
843 |
|
T11 |
363 |
| auto[1] |
6949918 |
1 |
|
|
T1 |
826 |
|
T12 |
130913 |
|
T14 |
1473 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2074501 |
1 |
|
|
T1 |
54 |
|
T12 |
40906 |
|
T14 |
415 |
| auto[1] |
auto[0] |
auto[1] |
1425398 |
1 |
|
|
T1 |
284 |
|
T12 |
25123 |
|
T14 |
419 |
| auto[1] |
auto[1] |
auto[0] |
2039002 |
1 |
|
|
T1 |
145 |
|
T12 |
39838 |
|
T14 |
332 |
| auto[1] |
auto[1] |
auto[1] |
1411017 |
1 |
|
|
T1 |
343 |
|
T12 |
25046 |
|
T14 |
307 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |