Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9185450 |
1 |
|
|
T22 |
957 |
|
T1 |
935 |
|
T11 |
363 |
| auto[1] |
6971030 |
1 |
|
|
T1 |
734 |
|
T12 |
126682 |
|
T14 |
1065 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15254065 |
1 |
|
|
T22 |
957 |
|
T1 |
1635 |
|
T11 |
363 |
| auto[1] |
902415 |
1 |
|
|
T1 |
34 |
|
T12 |
17011 |
|
T14 |
238 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9167061 |
1 |
|
|
T22 |
957 |
|
T1 |
809 |
|
T11 |
363 |
| auto[1] |
6989419 |
1 |
|
|
T1 |
860 |
|
T12 |
128171 |
|
T14 |
1283 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3039419 |
1 |
|
|
T1 |
491 |
|
T12 |
57551 |
|
T14 |
527 |
| auto[1] |
auto[0] |
auto[1] |
450681 |
1 |
|
|
T1 |
26 |
|
T12 |
8743 |
|
T14 |
116 |
| auto[1] |
auto[1] |
auto[0] |
3047585 |
1 |
|
|
T1 |
335 |
|
T12 |
53609 |
|
T14 |
518 |
| auto[1] |
auto[1] |
auto[1] |
451734 |
1 |
|
|
T1 |
8 |
|
T12 |
8268 |
|
T14 |
122 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |