Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9166203 |
1 |
|
|
T22 |
957 |
|
T1 |
843 |
|
T11 |
363 |
| auto[1] |
6990277 |
1 |
|
|
T1 |
826 |
|
T12 |
125805 |
|
T14 |
1322 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13306994 |
1 |
|
|
T22 |
957 |
|
T1 |
1258 |
|
T11 |
363 |
| auto[1] |
2849486 |
1 |
|
|
T1 |
411 |
|
T12 |
49513 |
|
T14 |
576 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9187832 |
1 |
|
|
T22 |
957 |
|
T1 |
1079 |
|
T11 |
363 |
| auto[1] |
6968648 |
1 |
|
|
T1 |
590 |
|
T12 |
127063 |
|
T14 |
1173 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2048176 |
1 |
|
|
T1 |
111 |
|
T12 |
40764 |
|
T14 |
275 |
| auto[1] |
auto[0] |
auto[1] |
1414299 |
1 |
|
|
T1 |
223 |
|
T12 |
25361 |
|
T14 |
280 |
| auto[1] |
auto[1] |
auto[0] |
2070986 |
1 |
|
|
T1 |
68 |
|
T12 |
36786 |
|
T14 |
322 |
| auto[1] |
auto[1] |
auto[1] |
1435187 |
1 |
|
|
T1 |
188 |
|
T12 |
24152 |
|
T14 |
296 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |