Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9216277 |
1 |
|
|
T22 |
957 |
|
T1 |
983 |
|
T11 |
363 |
| auto[1] |
6940203 |
1 |
|
|
T1 |
686 |
|
T12 |
126896 |
|
T14 |
1302 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13302457 |
1 |
|
|
T22 |
957 |
|
T1 |
957 |
|
T11 |
363 |
| auto[1] |
2854023 |
1 |
|
|
T1 |
712 |
|
T12 |
49531 |
|
T14 |
518 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9159850 |
1 |
|
|
T22 |
957 |
|
T1 |
765 |
|
T11 |
363 |
| auto[1] |
6996630 |
1 |
|
|
T1 |
904 |
|
T12 |
128692 |
|
T14 |
1058 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2087745 |
1 |
|
|
T1 |
119 |
|
T12 |
44336 |
|
T14 |
268 |
| auto[1] |
auto[0] |
auto[1] |
1434601 |
1 |
|
|
T1 |
399 |
|
T12 |
26466 |
|
T14 |
234 |
| auto[1] |
auto[1] |
auto[0] |
2054862 |
1 |
|
|
T1 |
73 |
|
T12 |
34825 |
|
T14 |
272 |
| auto[1] |
auto[1] |
auto[1] |
1419422 |
1 |
|
|
T1 |
313 |
|
T12 |
23065 |
|
T14 |
284 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |