Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9184610 |
1 |
|
|
T22 |
957 |
|
T1 |
666 |
|
T11 |
363 |
| auto[1] |
6971870 |
1 |
|
|
T1 |
1003 |
|
T12 |
131035 |
|
T14 |
1094 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15259406 |
1 |
|
|
T22 |
957 |
|
T1 |
1633 |
|
T11 |
363 |
| auto[1] |
897074 |
1 |
|
|
T1 |
36 |
|
T12 |
17169 |
|
T14 |
250 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9202252 |
1 |
|
|
T22 |
957 |
|
T1 |
948 |
|
T11 |
363 |
| auto[1] |
6954228 |
1 |
|
|
T1 |
721 |
|
T12 |
128390 |
|
T14 |
1308 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3031351 |
1 |
|
|
T1 |
247 |
|
T12 |
52802 |
|
T14 |
616 |
| auto[1] |
auto[0] |
auto[1] |
449297 |
1 |
|
|
T1 |
12 |
|
T12 |
8198 |
|
T14 |
142 |
| auto[1] |
auto[1] |
auto[0] |
3025803 |
1 |
|
|
T1 |
438 |
|
T12 |
58419 |
|
T14 |
442 |
| auto[1] |
auto[1] |
auto[1] |
447777 |
1 |
|
|
T1 |
24 |
|
T12 |
8971 |
|
T14 |
108 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |