Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9211063 |
1 |
|
|
T22 |
957 |
|
T1 |
683 |
|
T11 |
363 |
| auto[1] |
6945417 |
1 |
|
|
T1 |
986 |
|
T12 |
128336 |
|
T14 |
1216 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15255028 |
1 |
|
|
T22 |
957 |
|
T1 |
1638 |
|
T11 |
363 |
| auto[1] |
901452 |
1 |
|
|
T1 |
31 |
|
T12 |
17370 |
|
T14 |
260 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9172639 |
1 |
|
|
T22 |
957 |
|
T1 |
936 |
|
T11 |
363 |
| auto[1] |
6983841 |
1 |
|
|
T1 |
733 |
|
T12 |
128632 |
|
T14 |
1350 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3071439 |
1 |
|
|
T1 |
300 |
|
T12 |
55429 |
|
T14 |
569 |
| auto[1] |
auto[0] |
auto[1] |
457531 |
1 |
|
|
T1 |
13 |
|
T12 |
8669 |
|
T14 |
140 |
| auto[1] |
auto[1] |
auto[0] |
3010950 |
1 |
|
|
T1 |
402 |
|
T12 |
55833 |
|
T14 |
521 |
| auto[1] |
auto[1] |
auto[1] |
443921 |
1 |
|
|
T1 |
18 |
|
T12 |
8701 |
|
T14 |
120 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |