Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9220909 |
1 |
|
|
T22 |
957 |
|
T1 |
874 |
|
T11 |
363 |
| auto[1] |
6935571 |
1 |
|
|
T1 |
795 |
|
T12 |
127204 |
|
T14 |
1115 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15259906 |
1 |
|
|
T22 |
957 |
|
T1 |
1639 |
|
T11 |
363 |
| auto[1] |
896574 |
1 |
|
|
T1 |
30 |
|
T12 |
17563 |
|
T14 |
245 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9201378 |
1 |
|
|
T22 |
957 |
|
T1 |
856 |
|
T11 |
363 |
| auto[1] |
6955102 |
1 |
|
|
T1 |
813 |
|
T12 |
130067 |
|
T14 |
1266 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3041176 |
1 |
|
|
T1 |
434 |
|
T12 |
56939 |
|
T14 |
560 |
| auto[1] |
auto[0] |
auto[1] |
450181 |
1 |
|
|
T1 |
18 |
|
T12 |
8838 |
|
T14 |
134 |
| auto[1] |
auto[1] |
auto[0] |
3017352 |
1 |
|
|
T1 |
349 |
|
T12 |
55565 |
|
T14 |
461 |
| auto[1] |
auto[1] |
auto[1] |
446393 |
1 |
|
|
T1 |
12 |
|
T12 |
8725 |
|
T14 |
111 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |