Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9177425 |
1 |
|
|
T22 |
957 |
|
T1 |
985 |
|
T11 |
363 |
| auto[1] |
6979055 |
1 |
|
|
T1 |
684 |
|
T12 |
128586 |
|
T14 |
1317 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15259086 |
1 |
|
|
T22 |
957 |
|
T1 |
1644 |
|
T11 |
363 |
| auto[1] |
897394 |
1 |
|
|
T1 |
25 |
|
T12 |
17152 |
|
T14 |
235 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9198622 |
1 |
|
|
T22 |
957 |
|
T1 |
784 |
|
T11 |
363 |
| auto[1] |
6957858 |
1 |
|
|
T1 |
885 |
|
T12 |
127798 |
|
T14 |
1337 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3024884 |
1 |
|
|
T1 |
479 |
|
T12 |
54678 |
|
T14 |
447 |
| auto[1] |
auto[0] |
auto[1] |
447947 |
1 |
|
|
T1 |
17 |
|
T12 |
8397 |
|
T14 |
107 |
| auto[1] |
auto[1] |
auto[0] |
3035580 |
1 |
|
|
T1 |
381 |
|
T12 |
55968 |
|
T14 |
655 |
| auto[1] |
auto[1] |
auto[1] |
449447 |
1 |
|
|
T1 |
8 |
|
T12 |
8755 |
|
T14 |
128 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |