Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9176360 |
1 |
|
|
T22 |
957 |
|
T1 |
772 |
|
T11 |
363 |
| auto[1] |
6980120 |
1 |
|
|
T1 |
897 |
|
T12 |
133324 |
|
T14 |
1215 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15256612 |
1 |
|
|
T22 |
957 |
|
T1 |
1647 |
|
T11 |
363 |
| auto[1] |
899868 |
1 |
|
|
T1 |
22 |
|
T12 |
17964 |
|
T14 |
341 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9186126 |
1 |
|
|
T22 |
957 |
|
T1 |
906 |
|
T11 |
363 |
| auto[1] |
6970354 |
1 |
|
|
T1 |
763 |
|
T12 |
132945 |
|
T14 |
1762 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3025750 |
1 |
|
|
T1 |
285 |
|
T12 |
55409 |
|
T14 |
693 |
| auto[1] |
auto[0] |
auto[1] |
447230 |
1 |
|
|
T1 |
5 |
|
T12 |
8679 |
|
T14 |
166 |
| auto[1] |
auto[1] |
auto[0] |
3044736 |
1 |
|
|
T1 |
456 |
|
T12 |
59572 |
|
T14 |
728 |
| auto[1] |
auto[1] |
auto[1] |
452638 |
1 |
|
|
T1 |
17 |
|
T12 |
9285 |
|
T14 |
175 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |