Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9179044 |
1 |
|
|
T22 |
957 |
|
T1 |
724 |
|
T11 |
363 |
| auto[1] |
6977436 |
1 |
|
|
T1 |
945 |
|
T12 |
129725 |
|
T14 |
1332 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15260656 |
1 |
|
|
T22 |
957 |
|
T1 |
1646 |
|
T11 |
363 |
| auto[1] |
895824 |
1 |
|
|
T1 |
23 |
|
T12 |
17185 |
|
T14 |
201 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9208462 |
1 |
|
|
T22 |
957 |
|
T1 |
938 |
|
T11 |
363 |
| auto[1] |
6948018 |
1 |
|
|
T1 |
731 |
|
T12 |
128216 |
|
T14 |
1098 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3032438 |
1 |
|
|
T1 |
311 |
|
T12 |
58165 |
|
T14 |
422 |
| auto[1] |
auto[0] |
auto[1] |
448281 |
1 |
|
|
T1 |
13 |
|
T12 |
9026 |
|
T14 |
91 |
| auto[1] |
auto[1] |
auto[0] |
3019756 |
1 |
|
|
T1 |
397 |
|
T12 |
52866 |
|
T14 |
475 |
| auto[1] |
auto[1] |
auto[1] |
447543 |
1 |
|
|
T1 |
10 |
|
T12 |
8159 |
|
T14 |
110 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |