Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 947
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html
T95 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1297829434 Mar 10 01:06:42 PM PDT 24 Mar 10 01:06:45 PM PDT 24 69030512 ps
T40 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1741849835 Mar 10 01:06:47 PM PDT 24 Mar 10 01:06:49 PM PDT 24 89353228 ps
T84 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1855372562 Mar 10 01:06:23 PM PDT 24 Mar 10 01:06:24 PM PDT 24 91777077 ps
T762 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2821792316 Mar 10 01:06:47 PM PDT 24 Mar 10 01:06:48 PM PDT 24 162438949 ps
T763 /workspace/coverage/cover_reg_top/31.gpio_intr_test.4109053184 Mar 10 01:06:55 PM PDT 24 Mar 10 01:06:57 PM PDT 24 54516336 ps
T35 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1246862482 Mar 10 01:06:35 PM PDT 24 Mar 10 01:06:36 PM PDT 24 1965641201 ps
T36 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3101684257 Mar 10 01:06:35 PM PDT 24 Mar 10 01:06:36 PM PDT 24 167626936 ps
T96 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3153214510 Mar 10 01:06:32 PM PDT 24 Mar 10 01:06:35 PM PDT 24 52522792 ps
T764 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3652502555 Mar 10 01:06:43 PM PDT 24 Mar 10 01:06:45 PM PDT 24 44137674 ps
T765 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2832511688 Mar 10 01:06:22 PM PDT 24 Mar 10 01:06:23 PM PDT 24 17740469 ps
T766 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1995224736 Mar 10 01:06:43 PM PDT 24 Mar 10 01:06:46 PM PDT 24 211218711 ps
T85 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1991282026 Mar 10 01:06:26 PM PDT 24 Mar 10 01:06:27 PM PDT 24 36697806 ps
T102 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3542622852 Mar 10 01:06:35 PM PDT 24 Mar 10 01:06:38 PM PDT 24 171648460 ps
T767 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2584398910 Mar 10 01:06:21 PM PDT 24 Mar 10 01:06:24 PM PDT 24 484897834 ps
T768 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.676769931 Mar 10 01:06:25 PM PDT 24 Mar 10 01:06:26 PM PDT 24 20505991 ps
T769 /workspace/coverage/cover_reg_top/21.gpio_intr_test.125370393 Mar 10 01:06:46 PM PDT 24 Mar 10 01:06:47 PM PDT 24 19710952 ps
T770 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1361779829 Mar 10 01:06:35 PM PDT 24 Mar 10 01:06:37 PM PDT 24 1692155897 ps
T771 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3495189946 Mar 10 01:06:44 PM PDT 24 Mar 10 01:06:45 PM PDT 24 41651396 ps
T772 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2971110528 Mar 10 01:06:32 PM PDT 24 Mar 10 01:06:36 PM PDT 24 151550537 ps
T773 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1862842528 Mar 10 01:06:16 PM PDT 24 Mar 10 01:06:17 PM PDT 24 112368304 ps
T774 /workspace/coverage/cover_reg_top/4.gpio_intr_test.1531167819 Mar 10 01:06:24 PM PDT 24 Mar 10 01:06:25 PM PDT 24 26684414 ps
T775 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1878219167 Mar 10 01:06:36 PM PDT 24 Mar 10 01:06:38 PM PDT 24 33511993 ps
T776 /workspace/coverage/cover_reg_top/30.gpio_intr_test.386936429 Mar 10 01:06:52 PM PDT 24 Mar 10 01:06:53 PM PDT 24 26168125 ps
T777 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.122790003 Mar 10 01:06:38 PM PDT 24 Mar 10 01:06:39 PM PDT 24 21800033 ps
T778 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3161563831 Mar 10 01:06:46 PM PDT 24 Mar 10 01:06:47 PM PDT 24 20275794 ps
T779 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1910965542 Mar 10 01:06:47 PM PDT 24 Mar 10 01:06:48 PM PDT 24 70073427 ps
T780 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3666773452 Mar 10 01:06:21 PM PDT 24 Mar 10 01:06:25 PM PDT 24 4105842551 ps
T781 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3999006649 Mar 10 01:06:32 PM PDT 24 Mar 10 01:06:35 PM PDT 24 27553862 ps
T86 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2681427580 Mar 10 01:06:17 PM PDT 24 Mar 10 01:06:18 PM PDT 24 70352112 ps
T782 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3315220082 Mar 10 01:06:25 PM PDT 24 Mar 10 01:06:26 PM PDT 24 27734756 ps
T783 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1008295259 Mar 10 01:06:48 PM PDT 24 Mar 10 01:06:49 PM PDT 24 46526526 ps
T784 /workspace/coverage/cover_reg_top/27.gpio_intr_test.204586729 Mar 10 01:06:47 PM PDT 24 Mar 10 01:06:47 PM PDT 24 14177686 ps
T785 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3315356807 Mar 10 01:06:31 PM PDT 24 Mar 10 01:06:32 PM PDT 24 64369774 ps
T786 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4144326498 Mar 10 01:06:34 PM PDT 24 Mar 10 01:06:35 PM PDT 24 14898282 ps
T787 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2115878417 Mar 10 01:06:32 PM PDT 24 Mar 10 01:06:35 PM PDT 24 88731864 ps
T788 /workspace/coverage/cover_reg_top/5.gpio_intr_test.1987907314 Mar 10 01:06:36 PM PDT 24 Mar 10 01:06:38 PM PDT 24 40618189 ps
T789 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2998000736 Mar 10 01:06:33 PM PDT 24 Mar 10 01:06:35 PM PDT 24 80503722 ps
T790 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.258603428 Mar 10 01:06:27 PM PDT 24 Mar 10 01:06:28 PM PDT 24 92397347 ps
T791 /workspace/coverage/cover_reg_top/11.gpio_intr_test.2490368651 Mar 10 01:06:36 PM PDT 24 Mar 10 01:06:38 PM PDT 24 129425055 ps
T792 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1941621411 Mar 10 01:06:53 PM PDT 24 Mar 10 01:06:54 PM PDT 24 16350577 ps
T793 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1486211574 Mar 10 01:06:36 PM PDT 24 Mar 10 01:06:38 PM PDT 24 215135805 ps
T794 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2373864334 Mar 10 01:06:26 PM PDT 24 Mar 10 01:06:27 PM PDT 24 69021692 ps
T795 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1061611947 Mar 10 01:06:35 PM PDT 24 Mar 10 01:06:40 PM PDT 24 416219523 ps
T796 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2979924515 Mar 10 01:06:43 PM PDT 24 Mar 10 01:06:46 PM PDT 24 292499268 ps
T797 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2721775132 Mar 10 01:06:37 PM PDT 24 Mar 10 01:06:38 PM PDT 24 160588940 ps
T798 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1651544512 Mar 10 01:06:22 PM PDT 24 Mar 10 01:06:23 PM PDT 24 138199960 ps
T799 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.189522470 Mar 10 01:06:26 PM PDT 24 Mar 10 01:06:28 PM PDT 24 131405536 ps
T800 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1779360744 Mar 10 01:06:22 PM PDT 24 Mar 10 01:06:23 PM PDT 24 14665646 ps
T801 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2829668183 Mar 10 01:06:45 PM PDT 24 Mar 10 01:06:46 PM PDT 24 22974206 ps
T802 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.958749171 Mar 10 01:06:22 PM PDT 24 Mar 10 01:06:23 PM PDT 24 339062833 ps
T803 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4277639066 Mar 10 01:06:22 PM PDT 24 Mar 10 01:06:24 PM PDT 24 60981442 ps
T804 /workspace/coverage/cover_reg_top/39.gpio_intr_test.4161759579 Mar 10 01:06:55 PM PDT 24 Mar 10 01:06:57 PM PDT 24 22246761 ps
T805 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1361465831 Mar 10 01:06:39 PM PDT 24 Mar 10 01:06:40 PM PDT 24 262767501 ps
T806 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2066651500 Mar 10 01:06:43 PM PDT 24 Mar 10 01:06:45 PM PDT 24 191741940 ps
T807 /workspace/coverage/cover_reg_top/22.gpio_intr_test.1433195601 Mar 10 01:06:47 PM PDT 24 Mar 10 01:06:48 PM PDT 24 92466140 ps
T808 /workspace/coverage/cover_reg_top/2.gpio_intr_test.4145981350 Mar 10 01:06:22 PM PDT 24 Mar 10 01:06:23 PM PDT 24 124953716 ps
T809 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2188796862 Mar 10 01:06:33 PM PDT 24 Mar 10 01:06:36 PM PDT 24 1137624877 ps
T810 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.245666153 Mar 10 01:06:44 PM PDT 24 Mar 10 01:06:45 PM PDT 24 57721293 ps
T811 /workspace/coverage/cover_reg_top/15.gpio_intr_test.2528350031 Mar 10 01:06:42 PM PDT 24 Mar 10 01:06:45 PM PDT 24 42424459 ps
T812 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2496747267 Mar 10 01:06:36 PM PDT 24 Mar 10 01:06:38 PM PDT 24 43491137 ps
T813 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3734594104 Mar 10 01:06:29 PM PDT 24 Mar 10 01:06:30 PM PDT 24 81701936 ps
T814 /workspace/coverage/cover_reg_top/17.gpio_intr_test.3932713685 Mar 10 01:06:45 PM PDT 24 Mar 10 01:06:46 PM PDT 24 14283132 ps
T815 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4018456617 Mar 10 01:06:35 PM PDT 24 Mar 10 01:06:37 PM PDT 24 17210647 ps
T816 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3667408413 Mar 10 01:06:47 PM PDT 24 Mar 10 01:06:49 PM PDT 24 27069553 ps
T817 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3331329291 Mar 10 01:06:49 PM PDT 24 Mar 10 01:06:50 PM PDT 24 12054636 ps
T818 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3467454661 Mar 10 01:06:32 PM PDT 24 Mar 10 01:06:35 PM PDT 24 21298076 ps
T819 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2794603017 Mar 10 01:06:32 PM PDT 24 Mar 10 01:06:36 PM PDT 24 100868617 ps
T820 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3144214597 Mar 10 01:06:54 PM PDT 24 Mar 10 01:06:56 PM PDT 24 15553456 ps
T821 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3617159223 Mar 10 01:06:35 PM PDT 24 Mar 10 01:06:38 PM PDT 24 523723392 ps
T822 /workspace/coverage/cover_reg_top/42.gpio_intr_test.1720780288 Mar 10 01:06:58 PM PDT 24 Mar 10 01:06:59 PM PDT 24 17513825 ps
T823 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4060876337 Mar 10 01:06:32 PM PDT 24 Mar 10 01:06:36 PM PDT 24 73134824 ps
T824 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2866698029 Mar 10 01:06:54 PM PDT 24 Mar 10 01:06:56 PM PDT 24 12749744 ps
T825 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3452414412 Mar 10 01:06:47 PM PDT 24 Mar 10 01:06:50 PM PDT 24 53353281 ps
T826 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1004149995 Mar 10 01:07:04 PM PDT 24 Mar 10 01:07:05 PM PDT 24 38462939 ps
T827 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1757170293 Mar 10 01:06:44 PM PDT 24 Mar 10 01:06:46 PM PDT 24 404492825 ps
T828 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2224764722 Mar 10 01:06:36 PM PDT 24 Mar 10 01:06:38 PM PDT 24 44225835 ps
T829 /workspace/coverage/cover_reg_top/14.gpio_intr_test.4260956979 Mar 10 01:06:42 PM PDT 24 Mar 10 01:06:44 PM PDT 24 13936147 ps
T830 /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2691308510 Mar 10 01:06:32 PM PDT 24 Mar 10 01:06:35 PM PDT 24 13859762 ps
T831 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2447796918 Mar 10 01:06:58 PM PDT 24 Mar 10 01:06:59 PM PDT 24 13955539 ps
T832 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1870360696 Mar 10 01:06:36 PM PDT 24 Mar 10 01:06:38 PM PDT 24 239240867 ps
T833 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3533544402 Mar 10 01:06:35 PM PDT 24 Mar 10 01:06:37 PM PDT 24 96717358 ps
T89 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1519297575 Mar 10 01:06:31 PM PDT 24 Mar 10 01:06:32 PM PDT 24 16337619 ps
T834 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2934574154 Mar 10 01:06:37 PM PDT 24 Mar 10 01:06:39 PM PDT 24 34580248 ps
T835 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3488069616 Mar 10 01:06:27 PM PDT 24 Mar 10 01:06:28 PM PDT 24 20409500 ps
T836 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3849111902 Mar 10 01:06:21 PM PDT 24 Mar 10 01:06:22 PM PDT 24 56333845 ps
T837 /workspace/coverage/cover_reg_top/24.gpio_intr_test.334678637 Mar 10 01:06:46 PM PDT 24 Mar 10 01:06:47 PM PDT 24 48648363 ps
T838 /workspace/coverage/cover_reg_top/28.gpio_intr_test.1108005585 Mar 10 01:06:48 PM PDT 24 Mar 10 01:06:49 PM PDT 24 27194449 ps
T839 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1278000327 Mar 10 01:06:45 PM PDT 24 Mar 10 01:06:47 PM PDT 24 33483157 ps
T840 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.567745801 Mar 10 01:06:43 PM PDT 24 Mar 10 01:06:46 PM PDT 24 97071846 ps
T841 /workspace/coverage/cover_reg_top/19.gpio_intr_test.2144568580 Mar 10 01:06:48 PM PDT 24 Mar 10 01:06:49 PM PDT 24 44248456 ps
T842 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1446854884 Mar 10 01:06:36 PM PDT 24 Mar 10 01:06:40 PM PDT 24 165321982 ps
T843 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1910489094 Mar 10 01:06:36 PM PDT 24 Mar 10 01:06:38 PM PDT 24 52445848 ps
T844 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1178537796 Mar 10 01:06:33 PM PDT 24 Mar 10 01:06:35 PM PDT 24 83564633 ps
T87 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3358751472 Mar 10 01:06:26 PM PDT 24 Mar 10 01:06:27 PM PDT 24 58346455 ps
T845 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1993099183 Mar 10 01:06:33 PM PDT 24 Mar 10 01:06:36 PM PDT 24 211906385 ps
T846 /workspace/coverage/cover_reg_top/36.gpio_intr_test.483702074 Mar 10 01:06:54 PM PDT 24 Mar 10 01:06:55 PM PDT 24 36293233 ps
T847 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3232430144 Mar 10 01:06:47 PM PDT 24 Mar 10 01:06:49 PM PDT 24 118912780 ps
T848 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1994193029 Mar 10 01:16:42 PM PDT 24 Mar 10 01:16:43 PM PDT 24 1749032723 ps
T849 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2731926186 Mar 10 01:16:51 PM PDT 24 Mar 10 01:16:52 PM PDT 24 138666526 ps
T850 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2512056673 Mar 10 01:16:42 PM PDT 24 Mar 10 01:16:43 PM PDT 24 40884067 ps
T851 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2814863655 Mar 10 01:16:56 PM PDT 24 Mar 10 01:16:58 PM PDT 24 22996216 ps
T852 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.448554577 Mar 10 01:17:30 PM PDT 24 Mar 10 01:17:32 PM PDT 24 77248440 ps
T853 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1969523517 Mar 10 01:17:35 PM PDT 24 Mar 10 01:17:36 PM PDT 24 51453930 ps
T854 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2755838562 Mar 10 01:17:20 PM PDT 24 Mar 10 01:17:21 PM PDT 24 24499893 ps
T855 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.724251401 Mar 10 01:17:08 PM PDT 24 Mar 10 01:17:10 PM PDT 24 140766621 ps
T856 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3029904931 Mar 10 01:17:05 PM PDT 24 Mar 10 01:17:06 PM PDT 24 54886622 ps
T857 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.716346906 Mar 10 01:17:35 PM PDT 24 Mar 10 01:17:37 PM PDT 24 102958163 ps
T858 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4266820855 Mar 10 01:17:09 PM PDT 24 Mar 10 01:17:10 PM PDT 24 116366693 ps
T859 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3176554247 Mar 10 01:17:20 PM PDT 24 Mar 10 01:17:21 PM PDT 24 55808722 ps
T860 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1505832669 Mar 10 01:17:18 PM PDT 24 Mar 10 01:17:20 PM PDT 24 367851273 ps
T861 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1720915928 Mar 10 01:16:33 PM PDT 24 Mar 10 01:16:34 PM PDT 24 63284576 ps
T862 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3811434325 Mar 10 01:17:13 PM PDT 24 Mar 10 01:17:15 PM PDT 24 38246741 ps
T863 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4127647043 Mar 10 01:17:41 PM PDT 24 Mar 10 01:17:42 PM PDT 24 193845005 ps
T864 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.45793487 Mar 10 01:17:41 PM PDT 24 Mar 10 01:17:43 PM PDT 24 56955474 ps
T865 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.465463519 Mar 10 01:16:51 PM PDT 24 Mar 10 01:16:53 PM PDT 24 194861861 ps
T866 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3979779434 Mar 10 01:17:13 PM PDT 24 Mar 10 01:17:15 PM PDT 24 193822355 ps
T867 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2336590420 Mar 10 01:17:25 PM PDT 24 Mar 10 01:17:27 PM PDT 24 92775661 ps
T868 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3266286472 Mar 10 01:17:24 PM PDT 24 Mar 10 01:17:25 PM PDT 24 43636431 ps
T869 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.658085037 Mar 10 01:16:55 PM PDT 24 Mar 10 01:16:57 PM PDT 24 418912690 ps
T870 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4157517693 Mar 10 01:17:35 PM PDT 24 Mar 10 01:17:37 PM PDT 24 273418494 ps
T871 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1919205217 Mar 10 01:17:20 PM PDT 24 Mar 10 01:17:22 PM PDT 24 81830792 ps
T872 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3483808197 Mar 10 01:17:31 PM PDT 24 Mar 10 01:17:33 PM PDT 24 134736148 ps
T873 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2426877685 Mar 10 01:17:41 PM PDT 24 Mar 10 01:17:42 PM PDT 24 20919659 ps
T874 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3235224729 Mar 10 01:16:51 PM PDT 24 Mar 10 01:16:52 PM PDT 24 123750702 ps
T875 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3308632239 Mar 10 01:17:30 PM PDT 24 Mar 10 01:17:32 PM PDT 24 68931193 ps
T876 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4006371998 Mar 10 01:17:37 PM PDT 24 Mar 10 01:17:38 PM PDT 24 133069538 ps
T877 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3284812818 Mar 10 01:17:20 PM PDT 24 Mar 10 01:17:21 PM PDT 24 387159847 ps
T878 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2635918932 Mar 10 01:17:01 PM PDT 24 Mar 10 01:17:03 PM PDT 24 114139840 ps
T879 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4118440302 Mar 10 01:17:26 PM PDT 24 Mar 10 01:17:27 PM PDT 24 158003753 ps
T880 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.632369421 Mar 10 01:17:26 PM PDT 24 Mar 10 01:17:28 PM PDT 24 210646796 ps
T881 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.720709291 Mar 10 01:17:31 PM PDT 24 Mar 10 01:17:33 PM PDT 24 48339069 ps
T882 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1756482508 Mar 10 01:17:20 PM PDT 24 Mar 10 01:17:21 PM PDT 24 1422651885 ps
T883 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3623843861 Mar 10 01:16:46 PM PDT 24 Mar 10 01:16:47 PM PDT 24 229794628 ps
T884 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1031998701 Mar 10 01:17:35 PM PDT 24 Mar 10 01:17:37 PM PDT 24 150899126 ps
T885 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.59821970 Mar 10 01:16:49 PM PDT 24 Mar 10 01:16:50 PM PDT 24 494549419 ps
T886 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.350926006 Mar 10 01:17:31 PM PDT 24 Mar 10 01:17:33 PM PDT 24 211615525 ps
T887 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2238526736 Mar 10 01:17:25 PM PDT 24 Mar 10 01:17:26 PM PDT 24 212552912 ps
T888 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2433576787 Mar 10 01:16:56 PM PDT 24 Mar 10 01:16:58 PM PDT 24 158981441 ps
T889 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1179013012 Mar 10 01:16:38 PM PDT 24 Mar 10 01:16:39 PM PDT 24 154254385 ps
T890 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.11609804 Mar 10 01:17:39 PM PDT 24 Mar 10 01:17:40 PM PDT 24 497462631 ps
T891 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.770805713 Mar 10 01:17:36 PM PDT 24 Mar 10 01:17:37 PM PDT 24 73682011 ps
T892 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.325439482 Mar 10 01:17:41 PM PDT 24 Mar 10 01:17:42 PM PDT 24 333699097 ps
T893 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1055666460 Mar 10 01:17:11 PM PDT 24 Mar 10 01:17:13 PM PDT 24 169389266 ps
T894 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1643308649 Mar 10 01:17:19 PM PDT 24 Mar 10 01:17:21 PM PDT 24 133963332 ps
T895 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4181304499 Mar 10 01:17:35 PM PDT 24 Mar 10 01:17:36 PM PDT 24 24485102 ps
T896 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2214289286 Mar 10 01:17:14 PM PDT 24 Mar 10 01:17:15 PM PDT 24 39237169 ps
T897 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.55928177 Mar 10 01:17:36 PM PDT 24 Mar 10 01:17:37 PM PDT 24 37889555 ps
T898 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3377899036 Mar 10 01:17:24 PM PDT 24 Mar 10 01:17:25 PM PDT 24 289168399 ps
T899 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2121869021 Mar 10 01:17:35 PM PDT 24 Mar 10 01:17:37 PM PDT 24 39186893 ps
T900 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.805939309 Mar 10 01:17:25 PM PDT 24 Mar 10 01:17:26 PM PDT 24 50252206 ps
T901 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.707757867 Mar 10 01:16:40 PM PDT 24 Mar 10 01:16:41 PM PDT 24 37916992 ps
T902 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2694789446 Mar 10 01:17:13 PM PDT 24 Mar 10 01:17:16 PM PDT 24 940077129 ps
T903 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.376167141 Mar 10 01:17:18 PM PDT 24 Mar 10 01:17:19 PM PDT 24 46724601 ps
T904 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3424319305 Mar 10 01:17:26 PM PDT 24 Mar 10 01:17:28 PM PDT 24 83805203 ps
T905 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.26502410 Mar 10 01:17:09 PM PDT 24 Mar 10 01:17:10 PM PDT 24 720874060 ps
T906 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.441075407 Mar 10 01:17:21 PM PDT 24 Mar 10 01:17:23 PM PDT 24 63068403 ps
T907 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.215056604 Mar 10 01:17:20 PM PDT 24 Mar 10 01:17:22 PM PDT 24 87215286 ps
T908 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.37745904 Mar 10 01:17:40 PM PDT 24 Mar 10 01:17:41 PM PDT 24 51843737 ps
T909 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1952830164 Mar 10 01:17:14 PM PDT 24 Mar 10 01:17:16 PM PDT 24 753274992 ps
T910 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4212279814 Mar 10 01:17:34 PM PDT 24 Mar 10 01:17:35 PM PDT 24 32108122 ps
T911 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3203072674 Mar 10 01:17:10 PM PDT 24 Mar 10 01:17:12 PM PDT 24 173840684 ps
T912 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4067390703 Mar 10 01:17:26 PM PDT 24 Mar 10 01:17:28 PM PDT 24 368958049 ps
T913 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1844826033 Mar 10 01:17:06 PM PDT 24 Mar 10 01:17:07 PM PDT 24 151610090 ps
T914 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.105774849 Mar 10 01:17:30 PM PDT 24 Mar 10 01:17:32 PM PDT 24 133789935 ps
T915 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2185832858 Mar 10 01:16:42 PM PDT 24 Mar 10 01:16:43 PM PDT 24 71545153 ps
T916 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.131109755 Mar 10 01:17:14 PM PDT 24 Mar 10 01:17:15 PM PDT 24 88935119 ps
T917 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.512910286 Mar 10 01:17:25 PM PDT 24 Mar 10 01:17:26 PM PDT 24 105470824 ps
T918 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1908908658 Mar 10 01:16:46 PM PDT 24 Mar 10 01:16:47 PM PDT 24 106800308 ps
T919 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.827186465 Mar 10 01:17:14 PM PDT 24 Mar 10 01:17:16 PM PDT 24 144847774 ps
T920 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.665859504 Mar 10 01:17:39 PM PDT 24 Mar 10 01:17:40 PM PDT 24 36265215 ps
T921 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1968435227 Mar 10 01:17:15 PM PDT 24 Mar 10 01:17:17 PM PDT 24 645809701 ps
T922 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.287212733 Mar 10 01:17:08 PM PDT 24 Mar 10 01:17:09 PM PDT 24 61827530 ps
T923 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.894687053 Mar 10 01:17:21 PM PDT 24 Mar 10 01:17:22 PM PDT 24 51940821 ps
T924 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1627475957 Mar 10 01:16:42 PM PDT 24 Mar 10 01:16:43 PM PDT 24 57843294 ps
T925 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3057906478 Mar 10 01:17:25 PM PDT 24 Mar 10 01:17:26 PM PDT 24 53252822 ps
T926 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3865388254 Mar 10 01:17:25 PM PDT 24 Mar 10 01:17:27 PM PDT 24 225895782 ps
T927 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1815693021 Mar 10 01:17:34 PM PDT 24 Mar 10 01:17:36 PM PDT 24 55616806 ps
T928 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2938364017 Mar 10 01:17:20 PM PDT 24 Mar 10 01:17:21 PM PDT 24 195027785 ps
T929 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2086037693 Mar 10 01:16:33 PM PDT 24 Mar 10 01:16:34 PM PDT 24 157675820 ps
T930 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3876019492 Mar 10 01:16:40 PM PDT 24 Mar 10 01:16:42 PM PDT 24 131638530 ps
T931 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2717715699 Mar 10 01:16:37 PM PDT 24 Mar 10 01:16:38 PM PDT 24 27910611 ps
T932 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.305787760 Mar 10 01:17:20 PM PDT 24 Mar 10 01:17:22 PM PDT 24 34790943 ps
T933 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1445273075 Mar 10 01:16:46 PM PDT 24 Mar 10 01:16:48 PM PDT 24 40978181 ps
T934 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2016910990 Mar 10 01:17:08 PM PDT 24 Mar 10 01:17:09 PM PDT 24 240391890 ps
T935 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3826084473 Mar 10 01:17:26 PM PDT 24 Mar 10 01:17:28 PM PDT 24 66622804 ps
T936 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3701999832 Mar 10 01:17:25 PM PDT 24 Mar 10 01:17:26 PM PDT 24 151380085 ps
T937 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3577704391 Mar 10 01:17:34 PM PDT 24 Mar 10 01:17:36 PM PDT 24 112103522 ps
T938 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1323309413 Mar 10 01:17:36 PM PDT 24 Mar 10 01:17:38 PM PDT 24 65716186 ps
T939 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.4058360702 Mar 10 01:16:50 PM PDT 24 Mar 10 01:16:52 PM PDT 24 39336558 ps
T940 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2211274913 Mar 10 01:16:50 PM PDT 24 Mar 10 01:16:51 PM PDT 24 63212294 ps
T941 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2040906407 Mar 10 01:17:09 PM PDT 24 Mar 10 01:17:10 PM PDT 24 47067578 ps
T942 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3043658198 Mar 10 01:17:07 PM PDT 24 Mar 10 01:17:09 PM PDT 24 177400950 ps
T943 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4185065057 Mar 10 01:17:09 PM PDT 24 Mar 10 01:17:10 PM PDT 24 35734537 ps
T944 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3193248533 Mar 10 01:17:23 PM PDT 24 Mar 10 01:17:24 PM PDT 24 109386782 ps
T945 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3525325975 Mar 10 01:16:42 PM PDT 24 Mar 10 01:16:44 PM PDT 24 154351148 ps
T946 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4126651232 Mar 10 01:17:41 PM PDT 24 Mar 10 01:17:42 PM PDT 24 113079810 ps
T947 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2833159212 Mar 10 01:17:06 PM PDT 24 Mar 10 01:17:07 PM PDT 24 87098505 ps

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1200050711
Short name T1
Test name
Test status
Simulation time 1726051537 ps
CPU time 5.79 seconds
Started Mar 10 03:30:07 PM PDT 24
Finished Mar 10 03:30:13 PM PDT 24
Peak memory 198168 kb
Host smart-dc3abfd5-8b7d-4746-91eb-9be4f4902745
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200050711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1200050711
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3654661998
Short name T22
Test name
Test status
Simulation time 256775039 ps
CPU time 2.37 seconds
Started Mar 10 03:25:35 PM PDT 24
Finished Mar 10 03:25:38 PM PDT 24
Peak memory 198168 kb
Host smart-eef6bdab-0f4b-4b99-ae25-4d8ec5ef83d6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654661998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3654661998
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2006309703
Short name T12
Test name
Test status
Simulation time 95013830860 ps
CPU time 739.74 seconds
Started Mar 10 03:29:49 PM PDT 24
Finished Mar 10 03:42:09 PM PDT 24
Peak memory 198472 kb
Host smart-85414a3e-acc7-4cea-87c4-6725413a48ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2006309703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2006309703
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.713146500
Short name T29
Test name
Test status
Simulation time 175508274 ps
CPU time 1.04 seconds
Started Mar 10 03:25:20 PM PDT 24
Finished Mar 10 03:25:21 PM PDT 24
Peak memory 214936 kb
Host smart-7a14cad7-ca1e-4bbf-bd3a-465dc4a7958f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713146500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.713146500
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.997816762
Short name T75
Test name
Test status
Simulation time 30628323 ps
CPU time 0.77 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:23 PM PDT 24
Peak memory 196380 kb
Host smart-a0ef5ad5-f8d1-498e-ba26-5b67c9beb497
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997816762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.gpio_csr_aliasing.997816762
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.1246862482
Short name T35
Test name
Test status
Simulation time 1965641201 ps
CPU time 1.45 seconds
Started Mar 10 01:06:35 PM PDT 24
Finished Mar 10 01:06:36 PM PDT 24
Peak memory 198540 kb
Host smart-d4778152-6497-4ccb-a39f-af01146082e7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246862482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.1246862482
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/10.gpio_alert_test.3103448436
Short name T32
Test name
Test status
Simulation time 13253153 ps
CPU time 0.62 seconds
Started Mar 10 03:26:55 PM PDT 24
Finished Mar 10 03:26:56 PM PDT 24
Peak memory 194132 kb
Host smart-bbad74b5-516e-4a3a-986b-5253ada5674e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103448436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.3103448436
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.1496978154
Short name T90
Test name
Test status
Simulation time 19923529 ps
CPU time 0.83 seconds
Started Mar 10 01:06:26 PM PDT 24
Finished Mar 10 01:06:28 PM PDT 24
Peak memory 196856 kb
Host smart-2eda8344-a359-484e-8237-21d680668a6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496978154 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.1496978154
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1470746147
Short name T39
Test name
Test status
Simulation time 1320709266 ps
CPU time 1.72 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:24 PM PDT 24
Peak memory 198584 kb
Host smart-1d7e8868-ef5b-4a05-8f8a-c5de39efda6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470746147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1470746147
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3507995638
Short name T760
Test name
Test status
Simulation time 16624755 ps
CPU time 0.82 seconds
Started Mar 10 01:06:20 PM PDT 24
Finished Mar 10 01:06:21 PM PDT 24
Peak memory 197100 kb
Host smart-27dc547a-707a-4328-8548-a86ca62863b3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507995638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3507995638
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.189522470
Short name T799
Test name
Test status
Simulation time 131405536 ps
CPU time 1.39 seconds
Started Mar 10 01:06:26 PM PDT 24
Finished Mar 10 01:06:28 PM PDT 24
Peak memory 198404 kb
Host smart-1349b20c-14ba-4066-8e71-fcf8b624f855
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189522470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.189522470
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1343161550
Short name T79
Test name
Test status
Simulation time 16436766 ps
CPU time 0.71 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:23 PM PDT 24
Peak memory 195468 kb
Host smart-32080e4d-6ae7-4b08-98dc-3abffa228c3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343161550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1343161550
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2166343475
Short name T746
Test name
Test status
Simulation time 58142992 ps
CPU time 0.71 seconds
Started Mar 10 01:06:17 PM PDT 24
Finished Mar 10 01:06:18 PM PDT 24
Peak memory 198448 kb
Host smart-4a32aa93-4dd8-4c23-a45e-29aef29df005
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166343475 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2166343475
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2681427580
Short name T86
Test name
Test status
Simulation time 70352112 ps
CPU time 0.56 seconds
Started Mar 10 01:06:17 PM PDT 24
Finished Mar 10 01:06:18 PM PDT 24
Peak memory 193640 kb
Host smart-eb2e9202-a344-4739-84c6-5a35db0afa59
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681427580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2681427580
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1779360744
Short name T800
Test name
Test status
Simulation time 14665646 ps
CPU time 0.63 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:23 PM PDT 24
Peak memory 194256 kb
Host smart-b15ebed0-2e53-45ac-87ae-12a4a22a9fd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779360744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1779360744
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1862842528
Short name T773
Test name
Test status
Simulation time 112368304 ps
CPU time 0.81 seconds
Started Mar 10 01:06:16 PM PDT 24
Finished Mar 10 01:06:17 PM PDT 24
Peak memory 196912 kb
Host smart-6e15a3e6-a8d3-4f6a-91d7-679457f1b149
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862842528 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1862842528
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.1742045240
Short name T737
Test name
Test status
Simulation time 190397584 ps
CPU time 2.71 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:24 PM PDT 24
Peak memory 198548 kb
Host smart-1452104a-43a7-43e7-b861-b75060178822
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742045240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.1742045240
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2795180967
Short name T26
Test name
Test status
Simulation time 155011455 ps
CPU time 0.92 seconds
Started Mar 10 01:06:21 PM PDT 24
Finished Mar 10 01:06:22 PM PDT 24
Peak memory 198388 kb
Host smart-d2f6623a-30ba-460a-9cd7-186dd5375447
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795180967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2795180967
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1855372562
Short name T84
Test name
Test status
Simulation time 91777077 ps
CPU time 0.73 seconds
Started Mar 10 01:06:23 PM PDT 24
Finished Mar 10 01:06:24 PM PDT 24
Peak memory 194860 kb
Host smart-db2c0510-6c94-4fb5-985c-227ef8a1d2a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855372562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1855372562
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3666773452
Short name T780
Test name
Test status
Simulation time 4105842551 ps
CPU time 3.2 seconds
Started Mar 10 01:06:21 PM PDT 24
Finished Mar 10 01:06:25 PM PDT 24
Peak memory 197620 kb
Host smart-64260f6f-2f87-47db-ac6f-b76a90f51961
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666773452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3666773452
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2160658704
Short name T69
Test name
Test status
Simulation time 16966046 ps
CPU time 0.7 seconds
Started Mar 10 01:06:20 PM PDT 24
Finished Mar 10 01:06:21 PM PDT 24
Peak memory 195284 kb
Host smart-8f6c45e1-f474-4326-85e3-cf976008f9fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160658704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2160658704
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.2084948929
Short name T738
Test name
Test status
Simulation time 24946953 ps
CPU time 0.83 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:23 PM PDT 24
Peak memory 198380 kb
Host smart-2d421f42-ecf2-42a9-a4ef-f7029c04288f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084948929 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.2084948929
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1991427505
Short name T101
Test name
Test status
Simulation time 35122665 ps
CPU time 0.62 seconds
Started Mar 10 01:06:21 PM PDT 24
Finished Mar 10 01:06:21 PM PDT 24
Peak memory 194896 kb
Host smart-860921df-5507-45a0-9932-601e0b7b4e42
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991427505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1991427505
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2832511688
Short name T765
Test name
Test status
Simulation time 17740469 ps
CPU time 0.65 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:23 PM PDT 24
Peak memory 194920 kb
Host smart-e5bb1da9-eafb-403d-bc47-b049fe94d179
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832511688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2832511688
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3315220082
Short name T782
Test name
Test status
Simulation time 27734756 ps
CPU time 0.77 seconds
Started Mar 10 01:06:25 PM PDT 24
Finished Mar 10 01:06:26 PM PDT 24
Peak memory 196624 kb
Host smart-310a6d7c-e4c2-4eb8-b3d6-3eec49dca58b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315220082 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3315220082
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2584398910
Short name T767
Test name
Test status
Simulation time 484897834 ps
CPU time 2.7 seconds
Started Mar 10 01:06:21 PM PDT 24
Finished Mar 10 01:06:24 PM PDT 24
Peak memory 198532 kb
Host smart-cac2c658-1bdf-4db2-8896-1cab0269472a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584398910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2584398910
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2115878417
Short name T787
Test name
Test status
Simulation time 88731864 ps
CPU time 0.76 seconds
Started Mar 10 01:06:32 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 198452 kb
Host smart-7bc850e7-68dc-4adf-aef7-a2edf54ddfe6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115878417 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2115878417
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1616031823
Short name T74
Test name
Test status
Simulation time 107392854 ps
CPU time 0.67 seconds
Started Mar 10 01:06:35 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 195504 kb
Host smart-2d43083b-60ca-4f1c-9f6a-3c09a7df7965
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616031823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1616031823
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.122265209
Short name T761
Test name
Test status
Simulation time 14920006 ps
CPU time 0.57 seconds
Started Mar 10 01:06:34 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 194520 kb
Host smart-c1aac38d-b3e6-4dbe-814c-ccfc72735809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122265209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.122265209
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1993099183
Short name T845
Test name
Test status
Simulation time 211906385 ps
CPU time 1.1 seconds
Started Mar 10 01:06:33 PM PDT 24
Finished Mar 10 01:06:36 PM PDT 24
Peak memory 197192 kb
Host smart-8dc2650c-7589-4a37-a8e1-28d1e52288eb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993099183 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1993099183
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1737367817
Short name T730
Test name
Test status
Simulation time 946428999 ps
CPU time 2.22 seconds
Started Mar 10 01:06:35 PM PDT 24
Finished Mar 10 01:06:37 PM PDT 24
Peak memory 198488 kb
Host smart-9001436e-b992-434d-9423-794c2ab53a79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737367817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1737367817
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.218225548
Short name T744
Test name
Test status
Simulation time 26821636 ps
CPU time 0.82 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 198428 kb
Host smart-e3cb0eed-98ae-4ea3-bed8-072e241586cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218225548 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.218225548
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1466446739
Short name T76
Test name
Test status
Simulation time 13501321 ps
CPU time 0.64 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 195496 kb
Host smart-7ffce2b1-3e89-4f8c-b6ad-2b84a1c6acf5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466446739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1466446739
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.2490368651
Short name T791
Test name
Test status
Simulation time 129425055 ps
CPU time 0.6 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 194168 kb
Host smart-57d2451c-511c-410e-bd2f-65e5bd9bf374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490368651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.2490368651
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2721775132
Short name T797
Test name
Test status
Simulation time 160588940 ps
CPU time 0.93 seconds
Started Mar 10 01:06:37 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 197932 kb
Host smart-6d8b3e5e-7cb5-4d19-84f1-066a75be8df4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721775132 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2721775132
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2934574154
Short name T834
Test name
Test status
Simulation time 34580248 ps
CPU time 1.76 seconds
Started Mar 10 01:06:37 PM PDT 24
Finished Mar 10 01:06:39 PM PDT 24
Peak memory 198552 kb
Host smart-f92584ab-5b60-4c51-8786-811dcab8f0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934574154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2934574154
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3542622852
Short name T102
Test name
Test status
Simulation time 171648460 ps
CPU time 0.91 seconds
Started Mar 10 01:06:35 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 197832 kb
Host smart-54c740e5-1cba-431d-ac27-42266f8f2366
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542622852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3542622852
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2496747267
Short name T812
Test name
Test status
Simulation time 43491137 ps
CPU time 1.24 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 198628 kb
Host smart-bc5956d2-522e-49c7-9632-81bbb5b4f00a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496747267 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2496747267
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.4237368279
Short name T80
Test name
Test status
Simulation time 125403176 ps
CPU time 0.64 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 195100 kb
Host smart-9eaa4fff-70e9-4edb-937f-b367aeadd102
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237368279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.4237368279
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.3901339330
Short name T729
Test name
Test status
Simulation time 78757931 ps
CPU time 0.59 seconds
Started Mar 10 01:06:35 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 194852 kb
Host smart-fc4662eb-4dec-431b-b69d-313595385fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901339330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.3901339330
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.3801165494
Short name T94
Test name
Test status
Simulation time 19135707 ps
CPU time 0.8 seconds
Started Mar 10 01:06:38 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 196508 kb
Host smart-80d9ae8c-897a-4102-9dc5-cf74b32555ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801165494 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.3801165494
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1061611947
Short name T795
Test name
Test status
Simulation time 416219523 ps
CPU time 2.67 seconds
Started Mar 10 01:06:35 PM PDT 24
Finished Mar 10 01:06:40 PM PDT 24
Peak memory 198648 kb
Host smart-456173f2-9b9e-4227-8b31-e0978888040d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061611947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1061611947
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3589464499
Short name T27
Test name
Test status
Simulation time 153967167 ps
CPU time 0.94 seconds
Started Mar 10 01:06:37 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 197632 kb
Host smart-9006123f-b1f9-4358-b948-115b30202de3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589464499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3589464499
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.3533544402
Short name T833
Test name
Test status
Simulation time 96717358 ps
CPU time 1.36 seconds
Started Mar 10 01:06:35 PM PDT 24
Finished Mar 10 01:06:37 PM PDT 24
Peak memory 198656 kb
Host smart-44db4750-3e50-44f3-9936-0345863cc237
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533544402 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.3533544402
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.4018456617
Short name T815
Test name
Test status
Simulation time 17210647 ps
CPU time 0.66 seconds
Started Mar 10 01:06:35 PM PDT 24
Finished Mar 10 01:06:37 PM PDT 24
Peak memory 195360 kb
Host smart-7691568d-042f-4734-accb-b560ab8c76e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018456617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.4018456617
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2224764722
Short name T828
Test name
Test status
Simulation time 44225835 ps
CPU time 0.65 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 194196 kb
Host smart-7c33eaf4-387d-467b-9c96-3d89a42d4bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224764722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2224764722
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.122790003
Short name T777
Test name
Test status
Simulation time 21800033 ps
CPU time 0.92 seconds
Started Mar 10 01:06:38 PM PDT 24
Finished Mar 10 01:06:39 PM PDT 24
Peak memory 198372 kb
Host smart-8897c7dc-3cfc-43b0-9dff-6ab5179302a7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122790003 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.122790003
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1361779829
Short name T770
Test name
Test status
Simulation time 1692155897 ps
CPU time 1.94 seconds
Started Mar 10 01:06:35 PM PDT 24
Finished Mar 10 01:06:37 PM PDT 24
Peak memory 198548 kb
Host smart-d5173250-2f43-4d83-95b0-f2ba0a46f12c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361779829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1361779829
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.3242332034
Short name T34
Test name
Test status
Simulation time 235536101 ps
CPU time 1.56 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:39 PM PDT 24
Peak memory 198372 kb
Host smart-fd7af44d-164f-4545-9658-ba4584d2a2e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242332034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.3242332034
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.226994256
Short name T736
Test name
Test status
Simulation time 47482086 ps
CPU time 1.78 seconds
Started Mar 10 01:06:42 PM PDT 24
Finished Mar 10 01:06:46 PM PDT 24
Peak memory 198684 kb
Host smart-d6abbba3-8aa3-4b5b-9cf2-862ea3ef3aa9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226994256 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.226994256
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.1878219167
Short name T775
Test name
Test status
Simulation time 33511993 ps
CPU time 0.62 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 195688 kb
Host smart-1c8de83d-2364-43cd-8f6c-b3d5284ded9e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878219167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.1878219167
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.4260956979
Short name T829
Test name
Test status
Simulation time 13936147 ps
CPU time 0.64 seconds
Started Mar 10 01:06:42 PM PDT 24
Finished Mar 10 01:06:44 PM PDT 24
Peak memory 194280 kb
Host smart-1a4586bc-dc90-4c7c-9f4d-4b2de9e4af06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260956979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.4260956979
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.549401877
Short name T71
Test name
Test status
Simulation time 21305687 ps
CPU time 0.72 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:47 PM PDT 24
Peak memory 195212 kb
Host smart-7307e29c-3637-4c2e-855a-439682522bdb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549401877 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 14.gpio_same_csr_outstanding.549401877
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1206452079
Short name T753
Test name
Test status
Simulation time 78835083 ps
CPU time 1.37 seconds
Started Mar 10 01:06:45 PM PDT 24
Finished Mar 10 01:06:46 PM PDT 24
Peak memory 198532 kb
Host smart-239d7aad-fd47-4787-b41b-2def1e284d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206452079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1206452079
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.2979924515
Short name T796
Test name
Test status
Simulation time 292499268 ps
CPU time 1.47 seconds
Started Mar 10 01:06:43 PM PDT 24
Finished Mar 10 01:06:46 PM PDT 24
Peak memory 198544 kb
Host smart-983bbe5a-0d2e-4c60-9e5a-8010fd862a8b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979924515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.2979924515
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.567745801
Short name T840
Test name
Test status
Simulation time 97071846 ps
CPU time 1.39 seconds
Started Mar 10 01:06:43 PM PDT 24
Finished Mar 10 01:06:46 PM PDT 24
Peak memory 198736 kb
Host smart-dc912f16-e986-4bef-b959-bcabe189bb84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567745801 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.567745801
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.2559955929
Short name T752
Test name
Test status
Simulation time 15653345 ps
CPU time 0.66 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:48 PM PDT 24
Peak memory 194440 kb
Host smart-de8735ae-ee9a-4f82-84c8-bae7d158e133
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559955929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.2559955929
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2528350031
Short name T811
Test name
Test status
Simulation time 42424459 ps
CPU time 0.67 seconds
Started Mar 10 01:06:42 PM PDT 24
Finished Mar 10 01:06:45 PM PDT 24
Peak memory 194952 kb
Host smart-5b93b807-916d-4bab-b685-88d02c1e7f3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528350031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2528350031
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3652502555
Short name T764
Test name
Test status
Simulation time 44137674 ps
CPU time 0.8 seconds
Started Mar 10 01:06:43 PM PDT 24
Finished Mar 10 01:06:45 PM PDT 24
Peak memory 196592 kb
Host smart-2bd1c431-49dd-4b71-8fa0-9cf672837ac3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652502555 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3652502555
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1830145026
Short name T740
Test name
Test status
Simulation time 206244718 ps
CPU time 1.29 seconds
Started Mar 10 01:06:43 PM PDT 24
Finished Mar 10 01:06:46 PM PDT 24
Peak memory 198568 kb
Host smart-30be2ac7-05ea-4a3b-9c3c-c0a853250b06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830145026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1830145026
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1995224736
Short name T766
Test name
Test status
Simulation time 211218711 ps
CPU time 1.52 seconds
Started Mar 10 01:06:43 PM PDT 24
Finished Mar 10 01:06:46 PM PDT 24
Peak memory 198488 kb
Host smart-fc237f2f-0250-41d3-87ff-7f13717a4bec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995224736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1995224736
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1278000327
Short name T839
Test name
Test status
Simulation time 33483157 ps
CPU time 1.41 seconds
Started Mar 10 01:06:45 PM PDT 24
Finished Mar 10 01:06:47 PM PDT 24
Peak memory 198656 kb
Host smart-4b5c9ef6-5009-4966-88fa-7bba4de3e25c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278000327 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1278000327
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2829668183
Short name T801
Test name
Test status
Simulation time 22974206 ps
CPU time 0.59 seconds
Started Mar 10 01:06:45 PM PDT 24
Finished Mar 10 01:06:46 PM PDT 24
Peak memory 193796 kb
Host smart-bb02ad25-57ac-4ca3-bdc1-2e8811bd8e30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829668183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2829668183
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.655713178
Short name T751
Test name
Test status
Simulation time 104980904 ps
CPU time 0.65 seconds
Started Mar 10 01:06:45 PM PDT 24
Finished Mar 10 01:06:46 PM PDT 24
Peak memory 194324 kb
Host smart-68702898-4dd3-41d1-97e3-f22cf908b3e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655713178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.655713178
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.519381428
Short name T73
Test name
Test status
Simulation time 20953814 ps
CPU time 0.92 seconds
Started Mar 10 01:06:45 PM PDT 24
Finished Mar 10 01:06:46 PM PDT 24
Peak memory 197552 kb
Host smart-afede6bf-980d-4417-83ec-9ac47f94d65d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519381428 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 16.gpio_same_csr_outstanding.519381428
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.1757170293
Short name T827
Test name
Test status
Simulation time 404492825 ps
CPU time 2.03 seconds
Started Mar 10 01:06:44 PM PDT 24
Finished Mar 10 01:06:46 PM PDT 24
Peak memory 198596 kb
Host smart-05358564-a7d7-43a8-962a-a7151af37cc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757170293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.1757170293
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2877997073
Short name T28
Test name
Test status
Simulation time 45129492 ps
CPU time 0.88 seconds
Started Mar 10 01:06:42 PM PDT 24
Finished Mar 10 01:06:45 PM PDT 24
Peak memory 198408 kb
Host smart-6b55845d-cb06-4bc0-9df3-c36560c26c37
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877997073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2877997073
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2912135435
Short name T745
Test name
Test status
Simulation time 19775942 ps
CPU time 0.77 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:48 PM PDT 24
Peak memory 197940 kb
Host smart-557d764b-7786-4d40-ba1a-b0cde87c1641
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912135435 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2912135435
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3746188641
Short name T78
Test name
Test status
Simulation time 53933901 ps
CPU time 0.68 seconds
Started Mar 10 01:06:43 PM PDT 24
Finished Mar 10 01:06:45 PM PDT 24
Peak memory 196088 kb
Host smart-cb91d49e-1669-4723-a3fa-149f9f089de4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746188641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3746188641
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.3932713685
Short name T814
Test name
Test status
Simulation time 14283132 ps
CPU time 0.6 seconds
Started Mar 10 01:06:45 PM PDT 24
Finished Mar 10 01:06:46 PM PDT 24
Peak memory 193488 kb
Host smart-bce5d4d5-516a-47c3-9a61-c85f7dbaf85d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932713685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.3932713685
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3643767228
Short name T93
Test name
Test status
Simulation time 609569387 ps
CPU time 0.91 seconds
Started Mar 10 01:06:41 PM PDT 24
Finished Mar 10 01:06:44 PM PDT 24
Peak memory 197828 kb
Host smart-c6a33fd6-cdf0-43f1-9e3f-daa069a2c6d8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643767228 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3643767228
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3571273701
Short name T734
Test name
Test status
Simulation time 78588188 ps
CPU time 1.56 seconds
Started Mar 10 01:06:42 PM PDT 24
Finished Mar 10 01:06:45 PM PDT 24
Peak memory 198636 kb
Host smart-554b4e95-19cb-4013-8574-3a59a6d592dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571273701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3571273701
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2066651500
Short name T806
Test name
Test status
Simulation time 191741940 ps
CPU time 0.89 seconds
Started Mar 10 01:06:43 PM PDT 24
Finished Mar 10 01:06:45 PM PDT 24
Peak memory 198280 kb
Host smart-9b36eacc-6ad1-49f0-b54f-b8fa9c72eeed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066651500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2066651500
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3495189946
Short name T771
Test name
Test status
Simulation time 41651396 ps
CPU time 0.74 seconds
Started Mar 10 01:06:44 PM PDT 24
Finished Mar 10 01:06:45 PM PDT 24
Peak memory 198316 kb
Host smart-f1abe53d-e632-4cf4-8193-26a58d7cc811
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495189946 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3495189946
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.245666153
Short name T810
Test name
Test status
Simulation time 57721293 ps
CPU time 0.62 seconds
Started Mar 10 01:06:44 PM PDT 24
Finished Mar 10 01:06:45 PM PDT 24
Peak memory 195280 kb
Host smart-f9286091-5792-4f2a-9a26-e15ee3aec968
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245666153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio
_csr_rw.245666153
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3667408413
Short name T816
Test name
Test status
Simulation time 27069553 ps
CPU time 0.58 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:49 PM PDT 24
Peak memory 194192 kb
Host smart-1515376e-2e3c-4e62-974a-b7882315c798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667408413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3667408413
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.1297829434
Short name T95
Test name
Test status
Simulation time 69030512 ps
CPU time 0.81 seconds
Started Mar 10 01:06:42 PM PDT 24
Finished Mar 10 01:06:45 PM PDT 24
Peak memory 197092 kb
Host smart-dd14688e-5a96-41e1-bea3-60efe74e1d83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297829434 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.1297829434
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1910965542
Short name T779
Test name
Test status
Simulation time 70073427 ps
CPU time 1.52 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:48 PM PDT 24
Peak memory 198576 kb
Host smart-a1652f45-923d-488b-9a15-0d817694aa89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910965542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1910965542
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1741849835
Short name T40
Test name
Test status
Simulation time 89353228 ps
CPU time 0.93 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:49 PM PDT 24
Peak memory 198312 kb
Host smart-b0f3fce4-e4e6-4ce1-b8ef-471c400be918
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741849835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1741849835
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3232430144
Short name T847
Test name
Test status
Simulation time 118912780 ps
CPU time 1 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:49 PM PDT 24
Peak memory 198448 kb
Host smart-34baf6f0-21b7-4cf2-b5aa-431ae6dcca0a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232430144 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3232430144
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3161563831
Short name T778
Test name
Test status
Simulation time 20275794 ps
CPU time 0.6 seconds
Started Mar 10 01:06:46 PM PDT 24
Finished Mar 10 01:06:47 PM PDT 24
Peak memory 195568 kb
Host smart-3719950e-1780-44f0-8d16-cb939b8f71ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161563831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3161563831
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2144568580
Short name T841
Test name
Test status
Simulation time 44248456 ps
CPU time 0.6 seconds
Started Mar 10 01:06:48 PM PDT 24
Finished Mar 10 01:06:49 PM PDT 24
Peak memory 194088 kb
Host smart-98eac27b-1123-4e3b-9d60-fb551a903a02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144568580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2144568580
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1008295259
Short name T783
Test name
Test status
Simulation time 46526526 ps
CPU time 0.69 seconds
Started Mar 10 01:06:48 PM PDT 24
Finished Mar 10 01:06:49 PM PDT 24
Peak memory 195148 kb
Host smart-aca4d5a9-d30d-4666-bf7c-d1d44817d002
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008295259 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1008295259
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3452414412
Short name T825
Test name
Test status
Simulation time 53353281 ps
CPU time 2.59 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:50 PM PDT 24
Peak memory 198544 kb
Host smart-e44e1e19-8965-4039-9c3b-05a3a6819553
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452414412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3452414412
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2821792316
Short name T762
Test name
Test status
Simulation time 162438949 ps
CPU time 0.93 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:48 PM PDT 24
Peak memory 197728 kb
Host smart-50a0afd4-ec66-4d69-b97d-51355e7f7512
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821792316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2821792316
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3492118035
Short name T83
Test name
Test status
Simulation time 255574404 ps
CPU time 2.46 seconds
Started Mar 10 01:06:21 PM PDT 24
Finished Mar 10 01:06:24 PM PDT 24
Peak memory 197596 kb
Host smart-9986df31-e7cf-4626-b283-ca65372422dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492118035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3492118035
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.644859984
Short name T77
Test name
Test status
Simulation time 44936942 ps
CPU time 0.65 seconds
Started Mar 10 01:06:21 PM PDT 24
Finished Mar 10 01:06:22 PM PDT 24
Peak memory 195184 kb
Host smart-49dab1d8-5cf2-4b17-afa0-5e393c569b36
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644859984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.644859984
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.1651544512
Short name T798
Test name
Test status
Simulation time 138199960 ps
CPU time 1.01 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:23 PM PDT 24
Peak memory 198484 kb
Host smart-3c154703-7972-4599-b578-03c992857b8b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651544512 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.1651544512
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.2737372322
Short name T70
Test name
Test status
Simulation time 13268474 ps
CPU time 0.7 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:22 PM PDT 24
Peak memory 196156 kb
Host smart-b1464d95-4e5a-47da-8e4c-03974d1fb55c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737372322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.2737372322
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.4145981350
Short name T808
Test name
Test status
Simulation time 124953716 ps
CPU time 0.62 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:23 PM PDT 24
Peak memory 194224 kb
Host smart-5d394326-a594-4a98-97c8-cbd29cf5037e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145981350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.4145981350
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3849111902
Short name T836
Test name
Test status
Simulation time 56333845 ps
CPU time 0.78 seconds
Started Mar 10 01:06:21 PM PDT 24
Finished Mar 10 01:06:22 PM PDT 24
Peak memory 197284 kb
Host smart-99b8cf7d-42a5-4a60-a170-12f1246e371c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849111902 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3849111902
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.4277639066
Short name T803
Test name
Test status
Simulation time 60981442 ps
CPU time 1.71 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:24 PM PDT 24
Peak memory 198548 kb
Host smart-fa4ed32e-927a-4793-80d1-04afc0b42c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277639066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.4277639066
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.958749171
Short name T802
Test name
Test status
Simulation time 339062833 ps
CPU time 1.09 seconds
Started Mar 10 01:06:22 PM PDT 24
Finished Mar 10 01:06:23 PM PDT 24
Peak memory 198056 kb
Host smart-10605b4a-113d-4f7d-9287-210791229689
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958749171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.958749171
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.867079219
Short name T742
Test name
Test status
Simulation time 18437128 ps
CPU time 0.62 seconds
Started Mar 10 01:06:48 PM PDT 24
Finished Mar 10 01:06:49 PM PDT 24
Peak memory 194216 kb
Host smart-3045ffc6-ce27-450d-bdb7-c00cb08954f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867079219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.867079219
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.125370393
Short name T769
Test name
Test status
Simulation time 19710952 ps
CPU time 0.68 seconds
Started Mar 10 01:06:46 PM PDT 24
Finished Mar 10 01:06:47 PM PDT 24
Peak memory 194252 kb
Host smart-b1c4f6c6-cbef-4e2f-98c8-46af595a04f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125370393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.125370393
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1433195601
Short name T807
Test name
Test status
Simulation time 92466140 ps
CPU time 0.63 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:48 PM PDT 24
Peak memory 194280 kb
Host smart-368936b5-ad55-4a73-890c-cd6f6e5d8889
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433195601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1433195601
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3265061572
Short name T750
Test name
Test status
Simulation time 10413907 ps
CPU time 0.56 seconds
Started Mar 10 01:06:46 PM PDT 24
Finished Mar 10 01:06:47 PM PDT 24
Peak memory 194832 kb
Host smart-bf2f24f1-5a28-4176-9615-7c49722b7dbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265061572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3265061572
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.334678637
Short name T837
Test name
Test status
Simulation time 48648363 ps
CPU time 0.61 seconds
Started Mar 10 01:06:46 PM PDT 24
Finished Mar 10 01:06:47 PM PDT 24
Peak memory 194148 kb
Host smart-7db0d6e3-566a-45e7-8af2-545555012b68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334678637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.334678637
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2963845158
Short name T735
Test name
Test status
Simulation time 117384165 ps
CPU time 0.62 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:48 PM PDT 24
Peak memory 194884 kb
Host smart-e888268d-a0bd-46f2-9e77-3a2643de4a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963845158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2963845158
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3331329291
Short name T817
Test name
Test status
Simulation time 12054636 ps
CPU time 0.63 seconds
Started Mar 10 01:06:49 PM PDT 24
Finished Mar 10 01:06:50 PM PDT 24
Peak memory 194332 kb
Host smart-59c95264-68bc-4452-9008-e62a957c5da8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331329291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3331329291
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.204586729
Short name T784
Test name
Test status
Simulation time 14177686 ps
CPU time 0.61 seconds
Started Mar 10 01:06:47 PM PDT 24
Finished Mar 10 01:06:47 PM PDT 24
Peak memory 194200 kb
Host smart-80429e42-51c9-42af-b1fe-32011e65ff79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204586729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.204586729
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.1108005585
Short name T838
Test name
Test status
Simulation time 27194449 ps
CPU time 0.62 seconds
Started Mar 10 01:06:48 PM PDT 24
Finished Mar 10 01:06:49 PM PDT 24
Peak memory 194900 kb
Host smart-e3d78a95-7a5d-40d4-b70c-c228f2c0208c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108005585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.1108005585
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2894907909
Short name T743
Test name
Test status
Simulation time 23200387 ps
CPU time 0.63 seconds
Started Mar 10 01:06:48 PM PDT 24
Finished Mar 10 01:06:49 PM PDT 24
Peak memory 194200 kb
Host smart-d7b98161-059c-47de-8929-1f221710bc12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894907909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2894907909
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.676769931
Short name T768
Test name
Test status
Simulation time 20505991 ps
CPU time 0.68 seconds
Started Mar 10 01:06:25 PM PDT 24
Finished Mar 10 01:06:26 PM PDT 24
Peak memory 194900 kb
Host smart-aeae8529-d480-4fa9-9421-c778ca46f1de
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676769931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.676769931
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1322049387
Short name T99
Test name
Test status
Simulation time 92581799 ps
CPU time 1.45 seconds
Started Mar 10 01:06:26 PM PDT 24
Finished Mar 10 01:06:28 PM PDT 24
Peak memory 197176 kb
Host smart-3e3614fd-2c44-4f95-abd5-c1bd6b473cfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322049387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1322049387
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3358751472
Short name T87
Test name
Test status
Simulation time 58346455 ps
CPU time 0.61 seconds
Started Mar 10 01:06:26 PM PDT 24
Finished Mar 10 01:06:27 PM PDT 24
Peak memory 195152 kb
Host smart-aac70af7-3cc0-4be4-96b9-c99d9d544857
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358751472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3358751472
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3734594104
Short name T813
Test name
Test status
Simulation time 81701936 ps
CPU time 1.08 seconds
Started Mar 10 01:06:29 PM PDT 24
Finished Mar 10 01:06:30 PM PDT 24
Peak memory 198756 kb
Host smart-474c9d24-b30c-4edb-bcc1-1e045040f2c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734594104 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3734594104
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2373864334
Short name T794
Test name
Test status
Simulation time 69021692 ps
CPU time 0.62 seconds
Started Mar 10 01:06:26 PM PDT 24
Finished Mar 10 01:06:27 PM PDT 24
Peak memory 195836 kb
Host smart-7d7f9b0b-aeaf-475f-ac52-b76c29f11033
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373864334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2373864334
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3488069616
Short name T835
Test name
Test status
Simulation time 20409500 ps
CPU time 0.59 seconds
Started Mar 10 01:06:27 PM PDT 24
Finished Mar 10 01:06:28 PM PDT 24
Peak memory 194164 kb
Host smart-cb3eae09-3a49-491c-8353-47c262760374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488069616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3488069616
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.960833626
Short name T92
Test name
Test status
Simulation time 45363014 ps
CPU time 0.65 seconds
Started Mar 10 01:06:26 PM PDT 24
Finished Mar 10 01:06:27 PM PDT 24
Peak memory 195968 kb
Host smart-50cb43b7-db2b-4b80-a795-a4a6d4f264aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960833626 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.960833626
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.258603428
Short name T790
Test name
Test status
Simulation time 92397347 ps
CPU time 1.22 seconds
Started Mar 10 01:06:27 PM PDT 24
Finished Mar 10 01:06:28 PM PDT 24
Peak memory 198504 kb
Host smart-4c2e6f6a-52ad-42c5-9e87-96f8e5b4b6ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258603428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.258603428
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2191514113
Short name T38
Test name
Test status
Simulation time 470597288 ps
CPU time 1.23 seconds
Started Mar 10 01:06:26 PM PDT 24
Finished Mar 10 01:06:28 PM PDT 24
Peak memory 198696 kb
Host smart-9ca67622-22b6-4e9e-95ea-ff72c136c906
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191514113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2191514113
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.386936429
Short name T776
Test name
Test status
Simulation time 26168125 ps
CPU time 0.57 seconds
Started Mar 10 01:06:52 PM PDT 24
Finished Mar 10 01:06:53 PM PDT 24
Peak memory 194824 kb
Host smart-d28135f1-ab9b-4b04-b422-7843a52889f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386936429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.386936429
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.4109053184
Short name T763
Test name
Test status
Simulation time 54516336 ps
CPU time 0.63 seconds
Started Mar 10 01:06:55 PM PDT 24
Finished Mar 10 01:06:57 PM PDT 24
Peak memory 194932 kb
Host smart-b7a3e017-985d-47ad-94f9-5302ab98d3b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109053184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.4109053184
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.1778033628
Short name T748
Test name
Test status
Simulation time 15487954 ps
CPU time 0.57 seconds
Started Mar 10 01:06:56 PM PDT 24
Finished Mar 10 01:06:57 PM PDT 24
Peak memory 194084 kb
Host smart-67799255-9dad-4f1d-a79e-ca2e9b681989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778033628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.1778033628
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.583289123
Short name T727
Test name
Test status
Simulation time 12103650 ps
CPU time 0.58 seconds
Started Mar 10 01:07:02 PM PDT 24
Finished Mar 10 01:07:03 PM PDT 24
Peak memory 194232 kb
Host smart-bbecb649-91f0-411c-91e2-f43e8497c738
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583289123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.583289123
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1004149995
Short name T826
Test name
Test status
Simulation time 38462939 ps
CPU time 0.57 seconds
Started Mar 10 01:07:04 PM PDT 24
Finished Mar 10 01:07:05 PM PDT 24
Peak memory 194252 kb
Host smart-e7aadc24-ad6f-45f7-9cd7-61e4e4e97823
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004149995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1004149995
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3144214597
Short name T820
Test name
Test status
Simulation time 15553456 ps
CPU time 0.63 seconds
Started Mar 10 01:06:54 PM PDT 24
Finished Mar 10 01:06:56 PM PDT 24
Peak memory 194216 kb
Host smart-f8fd94a2-b217-4d2a-866c-95c1c4e03882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144214597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3144214597
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.483702074
Short name T846
Test name
Test status
Simulation time 36293233 ps
CPU time 0.6 seconds
Started Mar 10 01:06:54 PM PDT 24
Finished Mar 10 01:06:55 PM PDT 24
Peak memory 194164 kb
Host smart-d65c0a00-af0e-45ad-baaa-10816781d397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483702074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.483702074
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.626308051
Short name T754
Test name
Test status
Simulation time 89343334 ps
CPU time 0.57 seconds
Started Mar 10 01:07:03 PM PDT 24
Finished Mar 10 01:07:05 PM PDT 24
Peak memory 194296 kb
Host smart-bb060a31-051b-4dfa-adc2-b4e202a21281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626308051 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.626308051
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3254251098
Short name T725
Test name
Test status
Simulation time 16234447 ps
CPU time 0.59 seconds
Started Mar 10 01:06:53 PM PDT 24
Finished Mar 10 01:06:54 PM PDT 24
Peak memory 194180 kb
Host smart-124a6018-48c3-4c1f-bb63-594532d31e1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254251098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3254251098
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.4161759579
Short name T804
Test name
Test status
Simulation time 22246761 ps
CPU time 0.58 seconds
Started Mar 10 01:06:55 PM PDT 24
Finished Mar 10 01:06:57 PM PDT 24
Peak memory 194212 kb
Host smart-46d1c3ee-ddf4-4109-8216-503f820e453b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161759579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.4161759579
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.1991282026
Short name T85
Test name
Test status
Simulation time 36697806 ps
CPU time 0.89 seconds
Started Mar 10 01:06:26 PM PDT 24
Finished Mar 10 01:06:27 PM PDT 24
Peak memory 196516 kb
Host smart-62789396-4c52-4dee-afaf-72b0bcaebf8f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991282026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.1991282026
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.527593377
Short name T100
Test name
Test status
Simulation time 57575400 ps
CPU time 2.26 seconds
Started Mar 10 01:06:34 PM PDT 24
Finished Mar 10 01:06:37 PM PDT 24
Peak memory 198544 kb
Host smart-0e9749ec-efc8-44cf-b0e2-86904f270bc6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527593377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.527593377
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3467454661
Short name T818
Test name
Test status
Simulation time 21298076 ps
CPU time 0.6 seconds
Started Mar 10 01:06:32 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 195436 kb
Host smart-94353bef-e2ee-46fe-9aaf-441a7b8eb43c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467454661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3467454661
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3155596750
Short name T755
Test name
Test status
Simulation time 21935067 ps
CPU time 0.8 seconds
Started Mar 10 01:06:26 PM PDT 24
Finished Mar 10 01:06:27 PM PDT 24
Peak memory 198424 kb
Host smart-237dfbae-dc27-4e5c-bff6-71d24414b6e5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155596750 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3155596750
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3308479698
Short name T82
Test name
Test status
Simulation time 23535695 ps
CPU time 0.58 seconds
Started Mar 10 01:06:29 PM PDT 24
Finished Mar 10 01:06:30 PM PDT 24
Peak memory 195644 kb
Host smart-2b95a39e-931e-4be7-8638-5818074d45c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308479698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3308479698
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1531167819
Short name T774
Test name
Test status
Simulation time 26684414 ps
CPU time 0.57 seconds
Started Mar 10 01:06:24 PM PDT 24
Finished Mar 10 01:06:25 PM PDT 24
Peak memory 194152 kb
Host smart-c0382bdf-7942-49c8-9e3e-e0d1bc741c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531167819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1531167819
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2230900018
Short name T739
Test name
Test status
Simulation time 390950752 ps
CPU time 1.01 seconds
Started Mar 10 01:06:24 PM PDT 24
Finished Mar 10 01:06:25 PM PDT 24
Peak memory 198348 kb
Host smart-1790d89e-47cd-44a6-a75d-5d9e444efb52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230900018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2230900018
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.3723331746
Short name T37
Test name
Test status
Simulation time 35090585 ps
CPU time 0.87 seconds
Started Mar 10 01:06:31 PM PDT 24
Finished Mar 10 01:06:32 PM PDT 24
Peak memory 198336 kb
Host smart-ca607e07-2609-4c44-ac5d-d712aeff07b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723331746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.3723331746
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.517784052
Short name T728
Test name
Test status
Simulation time 48759958 ps
CPU time 0.59 seconds
Started Mar 10 01:06:53 PM PDT 24
Finished Mar 10 01:06:54 PM PDT 24
Peak memory 194912 kb
Host smart-6fed9dc6-30ac-4731-a6f3-a7dd31781dae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517784052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.517784052
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2866698029
Short name T824
Test name
Test status
Simulation time 12749744 ps
CPU time 0.59 seconds
Started Mar 10 01:06:54 PM PDT 24
Finished Mar 10 01:06:56 PM PDT 24
Peak memory 194144 kb
Host smart-4ce10994-467a-4138-a247-5d1f723625c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866698029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2866698029
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1720780288
Short name T822
Test name
Test status
Simulation time 17513825 ps
CPU time 0.63 seconds
Started Mar 10 01:06:58 PM PDT 24
Finished Mar 10 01:06:59 PM PDT 24
Peak memory 194900 kb
Host smart-3fcf4ee5-a2b1-4f06-94b3-c87cf6bdb7e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720780288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1720780288
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3700449342
Short name T726
Test name
Test status
Simulation time 16722013 ps
CPU time 0.67 seconds
Started Mar 10 01:06:54 PM PDT 24
Finished Mar 10 01:06:55 PM PDT 24
Peak memory 194284 kb
Host smart-10ce7704-b956-4d23-b7c9-0b04aeb2b8c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700449342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3700449342
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.759675969
Short name T758
Test name
Test status
Simulation time 70597331 ps
CPU time 0.6 seconds
Started Mar 10 01:06:54 PM PDT 24
Finished Mar 10 01:06:57 PM PDT 24
Peak memory 194224 kb
Host smart-8358facb-19f3-4129-8dcb-927151edcada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759675969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.759675969
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1941621411
Short name T792
Test name
Test status
Simulation time 16350577 ps
CPU time 0.68 seconds
Started Mar 10 01:06:53 PM PDT 24
Finished Mar 10 01:06:54 PM PDT 24
Peak memory 194296 kb
Host smart-6bc0ab09-c3b6-4305-a06e-5331cc25a9a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941621411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1941621411
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.2933359707
Short name T749
Test name
Test status
Simulation time 20391549 ps
CPU time 0.61 seconds
Started Mar 10 01:06:55 PM PDT 24
Finished Mar 10 01:06:57 PM PDT 24
Peak memory 194188 kb
Host smart-3a19ea5a-bc43-49b1-99f9-8f6189d22f0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933359707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.2933359707
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.4002284278
Short name T757
Test name
Test status
Simulation time 20818381 ps
CPU time 0.57 seconds
Started Mar 10 01:06:57 PM PDT 24
Finished Mar 10 01:06:57 PM PDT 24
Peak memory 194084 kb
Host smart-16055d9d-d05f-43b9-ae58-2980211128a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002284278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.4002284278
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2447796918
Short name T831
Test name
Test status
Simulation time 13955539 ps
CPU time 0.59 seconds
Started Mar 10 01:06:58 PM PDT 24
Finished Mar 10 01:06:59 PM PDT 24
Peak memory 194188 kb
Host smart-3e96cc9f-02b8-4fb3-8c7c-61b5a4ea96d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447796918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2447796918
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.1457047424
Short name T732
Test name
Test status
Simulation time 16940529 ps
CPU time 0.61 seconds
Started Mar 10 01:06:52 PM PDT 24
Finished Mar 10 01:06:53 PM PDT 24
Peak memory 194128 kb
Host smart-bd669845-d5d9-4ce0-a9a6-f2ed947b0012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457047424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.1457047424
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3999006649
Short name T781
Test name
Test status
Simulation time 27553862 ps
CPU time 0.85 seconds
Started Mar 10 01:06:32 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 198488 kb
Host smart-69715192-2ae8-4b5f-81e6-1fa6efd03047
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999006649 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3999006649
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1118370602
Short name T88
Test name
Test status
Simulation time 76892612 ps
CPU time 0.61 seconds
Started Mar 10 01:06:32 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 194212 kb
Host smart-75a56f35-71f5-4b2b-aed0-09eca66fbdfb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118370602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1118370602
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1987907314
Short name T788
Test name
Test status
Simulation time 40618189 ps
CPU time 0.64 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 194836 kb
Host smart-d4f467bd-3212-4b0f-960a-ddc6d1c90b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987907314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1987907314
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3153214510
Short name T96
Test name
Test status
Simulation time 52522792 ps
CPU time 0.76 seconds
Started Mar 10 01:06:32 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 195708 kb
Host smart-6de6a085-ac64-4b89-9cf6-5f3ab8e471d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153214510 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3153214510
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.2594598561
Short name T759
Test name
Test status
Simulation time 37986534 ps
CPU time 1.9 seconds
Started Mar 10 01:06:33 PM PDT 24
Finished Mar 10 01:06:36 PM PDT 24
Peak memory 198608 kb
Host smart-ec572b3e-4175-4ac8-abc6-6409e0b751ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594598561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.2594598561
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4060876337
Short name T823
Test name
Test status
Simulation time 73134824 ps
CPU time 1.11 seconds
Started Mar 10 01:06:32 PM PDT 24
Finished Mar 10 01:06:36 PM PDT 24
Peak memory 198588 kb
Host smart-10ff1fa5-e689-4744-bc45-8b93f036255c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060876337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.4060876337
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2420196596
Short name T731
Test name
Test status
Simulation time 115172057 ps
CPU time 0.84 seconds
Started Mar 10 01:06:33 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 198732 kb
Host smart-a6f2d1d9-c60d-4a45-a33b-9fa887d895f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420196596 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2420196596
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1519297575
Short name T89
Test name
Test status
Simulation time 16337619 ps
CPU time 0.63 seconds
Started Mar 10 01:06:31 PM PDT 24
Finished Mar 10 01:06:32 PM PDT 24
Peak memory 195936 kb
Host smart-03bc6705-9a96-4610-a908-52b75fed24b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519297575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1519297575
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.2959824292
Short name T747
Test name
Test status
Simulation time 16230981 ps
CPU time 0.59 seconds
Started Mar 10 01:06:34 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 194576 kb
Host smart-c26b1d82-9a41-45e2-a35f-2913d97576f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959824292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.2959824292
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1178537796
Short name T844
Test name
Test status
Simulation time 83564633 ps
CPU time 0.76 seconds
Started Mar 10 01:06:33 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 197352 kb
Host smart-dd5fc7dc-2c94-4235-8346-d68e012a8bed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178537796 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1178537796
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.487903739
Short name T756
Test name
Test status
Simulation time 503754780 ps
CPU time 2.49 seconds
Started Mar 10 01:06:34 PM PDT 24
Finished Mar 10 01:06:37 PM PDT 24
Peak memory 198892 kb
Host smart-97c14b18-9443-4ab4-94f9-b99a96c92450
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487903739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.487903739
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3101684257
Short name T36
Test name
Test status
Simulation time 167626936 ps
CPU time 1.14 seconds
Started Mar 10 01:06:35 PM PDT 24
Finished Mar 10 01:06:36 PM PDT 24
Peak memory 198540 kb
Host smart-9052cd63-637b-40bf-954c-c7278e3a0903
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101684257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3101684257
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2998000736
Short name T789
Test name
Test status
Simulation time 80503722 ps
CPU time 0.81 seconds
Started Mar 10 01:06:33 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 198380 kb
Host smart-6c1b9ae6-14ec-4da6-bb52-01a4d1dc901b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998000736 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2998000736
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.1910489094
Short name T843
Test name
Test status
Simulation time 52445848 ps
CPU time 0.6 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 195792 kb
Host smart-53a5c54f-6b2a-47c3-8ddf-5c8010040910
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910489094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.1910489094
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1873455025
Short name T733
Test name
Test status
Simulation time 12593451 ps
CPU time 0.63 seconds
Started Mar 10 01:06:33 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 194200 kb
Host smart-5cd8e10c-f7f6-49ae-b450-4c09c139d03d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873455025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1873455025
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.1104186651
Short name T72
Test name
Test status
Simulation time 35295852 ps
CPU time 0.79 seconds
Started Mar 10 01:06:31 PM PDT 24
Finished Mar 10 01:06:32 PM PDT 24
Peak memory 196660 kb
Host smart-d68580f5-af27-44c7-a317-0e6bb3d05740
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104186651 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.gpio_same_csr_outstanding.1104186651
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.3617159223
Short name T821
Test name
Test status
Simulation time 523723392 ps
CPU time 2.39 seconds
Started Mar 10 01:06:35 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 198476 kb
Host smart-fa44bfce-fa7f-45a8-965d-643351148f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617159223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.3617159223
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2794603017
Short name T819
Test name
Test status
Simulation time 100868617 ps
CPU time 1.47 seconds
Started Mar 10 01:06:32 PM PDT 24
Finished Mar 10 01:06:36 PM PDT 24
Peak memory 198544 kb
Host smart-880c6645-9b14-4081-be0e-6cacf7fe5962
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794603017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2794603017
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1870360696
Short name T832
Test name
Test status
Simulation time 239240867 ps
CPU time 1.02 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 198424 kb
Host smart-abcdb564-ade4-4e2c-b50f-5acc9c9e6a85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870360696 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1870360696
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2677946407
Short name T81
Test name
Test status
Simulation time 13142585 ps
CPU time 0.64 seconds
Started Mar 10 01:06:31 PM PDT 24
Finished Mar 10 01:06:32 PM PDT 24
Peak memory 195296 kb
Host smart-84133214-4086-4017-a1ad-1e10bc36ce96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677946407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2677946407
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2644002225
Short name T741
Test name
Test status
Simulation time 18533493 ps
CPU time 0.6 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 194920 kb
Host smart-78053976-1ff3-4541-a4f6-5ae82c73a771
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644002225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2644002225
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1077020466
Short name T91
Test name
Test status
Simulation time 20097404 ps
CPU time 0.75 seconds
Started Mar 10 01:06:33 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 196448 kb
Host smart-85bb2227-147d-43c5-97f8-0a0ee38e1953
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077020466 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1077020466
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1486211574
Short name T793
Test name
Test status
Simulation time 215135805 ps
CPU time 1.35 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:38 PM PDT 24
Peak memory 198584 kb
Host smart-1a254644-4385-4546-9ec6-b6d376022fa7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486211574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1486211574
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2188796862
Short name T809
Test name
Test status
Simulation time 1137624877 ps
CPU time 1.49 seconds
Started Mar 10 01:06:33 PM PDT 24
Finished Mar 10 01:06:36 PM PDT 24
Peak memory 198444 kb
Host smart-aaf69635-7086-4439-9de2-87b925e8e90e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188796862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2188796862
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2971110528
Short name T772
Test name
Test status
Simulation time 151550537 ps
CPU time 1.04 seconds
Started Mar 10 01:06:32 PM PDT 24
Finished Mar 10 01:06:36 PM PDT 24
Peak memory 198384 kb
Host smart-84903c25-8f69-413a-acdb-9c5c39fbe1da
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971110528 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2971110528
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2691308510
Short name T830
Test name
Test status
Simulation time 13859762 ps
CPU time 0.63 seconds
Started Mar 10 01:06:32 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 195276 kb
Host smart-0a4c86f6-6ac8-4bec-9a56-16913bfb4edc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691308510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2691308510
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3315356807
Short name T785
Test name
Test status
Simulation time 64369774 ps
CPU time 0.59 seconds
Started Mar 10 01:06:31 PM PDT 24
Finished Mar 10 01:06:32 PM PDT 24
Peak memory 194804 kb
Host smart-f3c149e1-7699-40fa-9754-731f57128370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315356807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3315356807
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.4144326498
Short name T786
Test name
Test status
Simulation time 14898282 ps
CPU time 0.67 seconds
Started Mar 10 01:06:34 PM PDT 24
Finished Mar 10 01:06:35 PM PDT 24
Peak memory 195284 kb
Host smart-d7e244d7-0374-4d1a-9371-e2b628880f7b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144326498 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.4144326498
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.1446854884
Short name T842
Test name
Test status
Simulation time 165321982 ps
CPU time 2.4 seconds
Started Mar 10 01:06:36 PM PDT 24
Finished Mar 10 01:06:40 PM PDT 24
Peak memory 198556 kb
Host smart-7361e810-315e-4780-bbf3-71c9330750c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446854884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.1446854884
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1361465831
Short name T805
Test name
Test status
Simulation time 262767501 ps
CPU time 1.09 seconds
Started Mar 10 01:06:39 PM PDT 24
Finished Mar 10 01:06:40 PM PDT 24
Peak memory 198588 kb
Host smart-3084b112-6f40-4cb7-9f0e-39521097e4c1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361465831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1361465831
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.4161662737
Short name T717
Test name
Test status
Simulation time 12125579 ps
CPU time 0.6 seconds
Started Mar 10 03:24:28 PM PDT 24
Finished Mar 10 03:24:29 PM PDT 24
Peak memory 194132 kb
Host smart-14f56f2c-883c-4143-84aa-f4da64e4678e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161662737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.4161662737
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.677831831
Short name T653
Test name
Test status
Simulation time 152330836 ps
CPU time 0.92 seconds
Started Mar 10 03:24:16 PM PDT 24
Finished Mar 10 03:24:17 PM PDT 24
Peak memory 196376 kb
Host smart-7640f018-16f8-44d4-956b-4551afa994f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677831831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.677831831
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2721998513
Short name T294
Test name
Test status
Simulation time 691852532 ps
CPU time 21.42 seconds
Started Mar 10 03:24:19 PM PDT 24
Finished Mar 10 03:24:41 PM PDT 24
Peak memory 197092 kb
Host smart-4739ca40-6cee-4ed9-850b-5d1eb515b251
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721998513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2721998513
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.4136524415
Short name T302
Test name
Test status
Simulation time 176452438 ps
CPU time 1.08 seconds
Started Mar 10 03:24:23 PM PDT 24
Finished Mar 10 03:24:25 PM PDT 24
Peak memory 197320 kb
Host smart-5f5734e6-afbe-40d8-8840-17fc4e2f769e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136524415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.4136524415
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2687448013
Short name T105
Test name
Test status
Simulation time 154539161 ps
CPU time 0.97 seconds
Started Mar 10 03:24:19 PM PDT 24
Finished Mar 10 03:24:20 PM PDT 24
Peak memory 196580 kb
Host smart-ca0e7bcc-fe51-4da3-9602-db8ac1416d71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687448013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2687448013
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1345972157
Short name T428
Test name
Test status
Simulation time 150683009 ps
CPU time 1.86 seconds
Started Mar 10 03:24:20 PM PDT 24
Finished Mar 10 03:24:22 PM PDT 24
Peak memory 196596 kb
Host smart-03658f2e-92a0-4c8b-b220-01cecd41663d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345972157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1345972157
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.403671290
Short name T220
Test name
Test status
Simulation time 178267137 ps
CPU time 3.87 seconds
Started Mar 10 03:24:21 PM PDT 24
Finished Mar 10 03:24:25 PM PDT 24
Peak memory 198196 kb
Host smart-870fd777-f52f-47e0-8c1a-ed6aebd47044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403671290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.403671290
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2087500395
Short name T384
Test name
Test status
Simulation time 600499700 ps
CPU time 1.08 seconds
Started Mar 10 03:24:15 PM PDT 24
Finished Mar 10 03:24:16 PM PDT 24
Peak memory 196884 kb
Host smart-58b70160-84c2-481b-b23e-6cecc233f5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087500395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2087500395
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.2082395070
Short name T107
Test name
Test status
Simulation time 32487079 ps
CPU time 0.87 seconds
Started Mar 10 03:24:12 PM PDT 24
Finished Mar 10 03:24:13 PM PDT 24
Peak memory 196576 kb
Host smart-42cf4acf-8e84-4786-9307-fb050a05b86f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082395070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.2082395070
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3261785407
Short name T607
Test name
Test status
Simulation time 70379922 ps
CPU time 3.32 seconds
Started Mar 10 03:24:23 PM PDT 24
Finished Mar 10 03:24:26 PM PDT 24
Peak memory 198100 kb
Host smart-e2741181-17f1-428a-8bbe-c1290d683ada
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261785407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3261785407
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2536252562
Short name T43
Test name
Test status
Simulation time 221897275 ps
CPU time 0.89 seconds
Started Mar 10 03:24:29 PM PDT 24
Finished Mar 10 03:24:31 PM PDT 24
Peak memory 213904 kb
Host smart-67c98c7a-ab8b-40ac-8e3e-e48ce29ae7a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536252562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2536252562
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1136735660
Short name T298
Test name
Test status
Simulation time 162720618 ps
CPU time 1.4 seconds
Started Mar 10 03:24:05 PM PDT 24
Finished Mar 10 03:24:07 PM PDT 24
Peak memory 196936 kb
Host smart-bebdbb92-bad1-4713-a493-24bf332cbf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136735660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1136735660
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.3768497148
Short name T553
Test name
Test status
Simulation time 87454799 ps
CPU time 1.67 seconds
Started Mar 10 03:24:17 PM PDT 24
Finished Mar 10 03:24:19 PM PDT 24
Peak memory 196560 kb
Host smart-51a5555b-24d4-483c-bf19-aee0148c107f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768497148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.3768497148
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.389432433
Short name T108
Test name
Test status
Simulation time 14323099598 ps
CPU time 150.77 seconds
Started Mar 10 03:24:28 PM PDT 24
Finished Mar 10 03:26:59 PM PDT 24
Peak memory 198368 kb
Host smart-0ab345ff-bb1e-4a0b-9b1e-5f7d0a7d3525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389432433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gp
io_stress_all.389432433
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3634476564
Short name T447
Test name
Test status
Simulation time 31221477 ps
CPU time 0.59 seconds
Started Mar 10 03:24:52 PM PDT 24
Finished Mar 10 03:24:52 PM PDT 24
Peak memory 192828 kb
Host smart-f15f7061-7532-48b5-8f4b-98da03cfc1a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634476564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3634476564
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.4261416539
Short name T65
Test name
Test status
Simulation time 570953084 ps
CPU time 1 seconds
Started Mar 10 03:24:42 PM PDT 24
Finished Mar 10 03:24:43 PM PDT 24
Peak memory 196320 kb
Host smart-1e0e7dda-30e6-4953-a494-5cb7281e88ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261416539 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.4261416539
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.2040186293
Short name T194
Test name
Test status
Simulation time 698589426 ps
CPU time 11.12 seconds
Started Mar 10 03:24:58 PM PDT 24
Finished Mar 10 03:25:10 PM PDT 24
Peak memory 195692 kb
Host smart-325488a4-cc0a-4849-a680-7393ad68448b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040186293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.2040186293
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2361915090
Short name T130
Test name
Test status
Simulation time 162977913 ps
CPU time 0.73 seconds
Started Mar 10 03:24:48 PM PDT 24
Finished Mar 10 03:24:49 PM PDT 24
Peak memory 195844 kb
Host smart-cafd5b62-e269-4dce-a947-d663df287dde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361915090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2361915090
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1167510958
Short name T641
Test name
Test status
Simulation time 21001388 ps
CPU time 0.71 seconds
Started Mar 10 03:24:42 PM PDT 24
Finished Mar 10 03:24:43 PM PDT 24
Peak memory 195144 kb
Host smart-3a16466f-370b-4c8b-ba37-4baf4257fa89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167510958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1167510958
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1293534496
Short name T463
Test name
Test status
Simulation time 174099960 ps
CPU time 2.28 seconds
Started Mar 10 03:24:52 PM PDT 24
Finished Mar 10 03:24:54 PM PDT 24
Peak memory 198156 kb
Host smart-43101d65-5fed-4b9e-8425-3655b7ec34a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293534496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1293534496
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3843034410
Short name T216
Test name
Test status
Simulation time 198840139 ps
CPU time 2.25 seconds
Started Mar 10 03:24:37 PM PDT 24
Finished Mar 10 03:24:40 PM PDT 24
Peak memory 197132 kb
Host smart-2a039959-fdb3-498a-8ad2-b686a3765af1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843034410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3843034410
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2854464609
Short name T410
Test name
Test status
Simulation time 129511923 ps
CPU time 1.24 seconds
Started Mar 10 03:24:38 PM PDT 24
Finished Mar 10 03:24:39 PM PDT 24
Peak memory 196896 kb
Host smart-314e5442-b62e-4bcb-b86e-474f30cd5256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854464609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2854464609
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1592139027
Short name T127
Test name
Test status
Simulation time 207602140 ps
CPU time 0.94 seconds
Started Mar 10 03:24:48 PM PDT 24
Finished Mar 10 03:24:49 PM PDT 24
Peak memory 196252 kb
Host smart-14cc53f5-51d7-4c91-8dbc-e400a4cb1b84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592139027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1592139027
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2754266736
Short name T687
Test name
Test status
Simulation time 2183451523 ps
CPU time 6.04 seconds
Started Mar 10 03:24:50 PM PDT 24
Finished Mar 10 03:24:57 PM PDT 24
Peak memory 198316 kb
Host smart-9e0ccd0b-45bb-4cda-98ec-def881a5efeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754266736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2754266736
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.2196865934
Short name T31
Test name
Test status
Simulation time 37235085 ps
CPU time 0.83 seconds
Started Mar 10 03:24:59 PM PDT 24
Finished Mar 10 03:25:00 PM PDT 24
Peak memory 213836 kb
Host smart-1a2903b5-913a-4edd-b418-549547567215
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196865934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.2196865934
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3745183800
Short name T217
Test name
Test status
Simulation time 59630307 ps
CPU time 1.37 seconds
Started Mar 10 03:24:30 PM PDT 24
Finished Mar 10 03:24:32 PM PDT 24
Peak memory 196424 kb
Host smart-0c9ac2ba-3bad-48e7-aa6b-163dec9d10c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745183800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3745183800
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1122895427
Short name T326
Test name
Test status
Simulation time 237820501 ps
CPU time 1.16 seconds
Started Mar 10 03:24:32 PM PDT 24
Finished Mar 10 03:24:33 PM PDT 24
Peak memory 195912 kb
Host smart-383a9ead-6cfd-4b12-9c6b-ae8400a91af2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122895427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1122895427
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.178919467
Short name T3
Test name
Test status
Simulation time 9241168218 ps
CPU time 63.75 seconds
Started Mar 10 03:24:46 PM PDT 24
Finished Mar 10 03:25:50 PM PDT 24
Peak memory 198284 kb
Host smart-90a3bb72-a6a3-43ff-b256-8ac487f8d73a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178919467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.178919467
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.2165636108
Short name T525
Test name
Test status
Simulation time 133550447018 ps
CPU time 2403.64 seconds
Started Mar 10 03:24:58 PM PDT 24
Finished Mar 10 04:05:02 PM PDT 24
Peak memory 198528 kb
Host smart-85df1aff-0acb-493b-aa7a-644db5a4ec15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2165636108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.2165636108
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1831581830
Short name T400
Test name
Test status
Simulation time 47338794 ps
CPU time 0.77 seconds
Started Mar 10 03:26:39 PM PDT 24
Finished Mar 10 03:26:40 PM PDT 24
Peak memory 194964 kb
Host smart-3cdea84b-5edf-47d3-bd40-35baf814f839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831581830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1831581830
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.2780066630
Short name T115
Test name
Test status
Simulation time 340967960 ps
CPU time 9.58 seconds
Started Mar 10 03:26:41 PM PDT 24
Finished Mar 10 03:26:51 PM PDT 24
Peak memory 197052 kb
Host smart-066adc02-02e9-483b-a9b5-3e5ee437a1d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780066630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.2780066630
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.749723134
Short name T351
Test name
Test status
Simulation time 67218765 ps
CPU time 1 seconds
Started Mar 10 03:26:47 PM PDT 24
Finished Mar 10 03:26:49 PM PDT 24
Peak memory 197220 kb
Host smart-e50ccf16-c2b4-45fb-8597-d0f53b57b0b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749723134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.749723134
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1690831254
Short name T211
Test name
Test status
Simulation time 265745198 ps
CPU time 1.07 seconds
Started Mar 10 03:26:40 PM PDT 24
Finished Mar 10 03:26:41 PM PDT 24
Peak memory 196688 kb
Host smart-bd483e9b-71bf-4e77-8236-9fad98588f9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690831254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1690831254
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1965203419
Short name T253
Test name
Test status
Simulation time 123591948 ps
CPU time 1.45 seconds
Started Mar 10 03:26:38 PM PDT 24
Finished Mar 10 03:26:40 PM PDT 24
Peak memory 198212 kb
Host smart-15335a7a-5c9e-4f99-b9fc-e840874f4d64
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965203419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1965203419
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3415158139
Short name T450
Test name
Test status
Simulation time 178704274 ps
CPU time 2.54 seconds
Started Mar 10 03:26:40 PM PDT 24
Finished Mar 10 03:26:42 PM PDT 24
Peak memory 198224 kb
Host smart-8655a4bf-c66e-4285-bb38-d40879378cfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415158139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3415158139
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2022816119
Short name T599
Test name
Test status
Simulation time 28669797 ps
CPU time 1.11 seconds
Started Mar 10 03:26:35 PM PDT 24
Finished Mar 10 03:26:37 PM PDT 24
Peak memory 196004 kb
Host smart-65fa1229-eb8b-4656-a0c8-9c58330f09cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022816119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2022816119
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.4223747176
Short name T186
Test name
Test status
Simulation time 110526655 ps
CPU time 0.91 seconds
Started Mar 10 03:26:41 PM PDT 24
Finished Mar 10 03:26:42 PM PDT 24
Peak memory 195436 kb
Host smart-18fc1f4f-537d-485a-9242-20f133d3cf08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223747176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.4223747176
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.146570680
Short name T369
Test name
Test status
Simulation time 516433952 ps
CPU time 1.88 seconds
Started Mar 10 03:26:47 PM PDT 24
Finished Mar 10 03:26:50 PM PDT 24
Peak memory 198196 kb
Host smart-ce8ca556-6297-4009-8d34-f9d455053131
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146570680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ran
dom_long_reg_writes_reg_reads.146570680
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2893112844
Short name T533
Test name
Test status
Simulation time 46201726 ps
CPU time 1.43 seconds
Started Mar 10 03:26:24 PM PDT 24
Finished Mar 10 03:26:25 PM PDT 24
Peak memory 195648 kb
Host smart-ea1c1e67-ff22-4f72-bd98-b67009fc2d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893112844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2893112844
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.2835280632
Short name T696
Test name
Test status
Simulation time 224530994 ps
CPU time 1.2 seconds
Started Mar 10 03:26:29 PM PDT 24
Finished Mar 10 03:26:31 PM PDT 24
Peak memory 196604 kb
Host smart-22f69216-0bd3-45e1-93b5-8e2b56d5d780
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835280632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.2835280632
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1642003386
Short name T136
Test name
Test status
Simulation time 10192766703 ps
CPU time 180.86 seconds
Started Mar 10 03:27:13 PM PDT 24
Finished Mar 10 03:30:15 PM PDT 24
Peak memory 198400 kb
Host smart-c3ca8ea7-f40b-454d-a867-8623e0e4d732
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642003386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1642003386
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1314112242
Short name T354
Test name
Test status
Simulation time 69768968 ps
CPU time 0.53 seconds
Started Mar 10 03:26:58 PM PDT 24
Finished Mar 10 03:26:59 PM PDT 24
Peak memory 194108 kb
Host smart-d44ba23b-9963-494c-8af0-7ee040fa2d83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314112242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1314112242
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.3212078941
Short name T44
Test name
Test status
Simulation time 80884325 ps
CPU time 1.04 seconds
Started Mar 10 03:26:57 PM PDT 24
Finished Mar 10 03:26:58 PM PDT 24
Peak memory 197396 kb
Host smart-48295e8d-1cc7-4097-9a06-3b41e8e6ce9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212078941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.3212078941
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.331978272
Short name T166
Test name
Test status
Simulation time 205113639 ps
CPU time 10.85 seconds
Started Mar 10 03:26:57 PM PDT 24
Finished Mar 10 03:27:08 PM PDT 24
Peak memory 195716 kb
Host smart-3a6a98b7-faf4-4364-b8a9-80cc69c0ce06
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331978272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.331978272
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3623519200
Short name T246
Test name
Test status
Simulation time 123179770 ps
CPU time 0.78 seconds
Started Mar 10 03:27:12 PM PDT 24
Finished Mar 10 03:27:13 PM PDT 24
Peak memory 196004 kb
Host smart-63786e73-92f0-426f-b214-708f0472f5bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623519200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3623519200
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.2185134844
Short name T195
Test name
Test status
Simulation time 1080367964 ps
CPU time 1.27 seconds
Started Mar 10 03:26:56 PM PDT 24
Finished Mar 10 03:26:58 PM PDT 24
Peak memory 196312 kb
Host smart-787cfcfa-ff91-4921-85e9-85691f7e74ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185134844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.2185134844
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2087080568
Short name T334
Test name
Test status
Simulation time 317440764 ps
CPU time 3.43 seconds
Started Mar 10 03:26:59 PM PDT 24
Finished Mar 10 03:27:03 PM PDT 24
Peak memory 198168 kb
Host smart-bd3c426b-e944-4384-8f6c-35371626d7a8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087080568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2087080568
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.294762791
Short name T47
Test name
Test status
Simulation time 375157853 ps
CPU time 2.99 seconds
Started Mar 10 03:26:56 PM PDT 24
Finished Mar 10 03:27:00 PM PDT 24
Peak memory 197100 kb
Host smart-c9540e54-633e-469c-907d-d8f5347502f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294762791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
294762791
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.4286665761
Short name T233
Test name
Test status
Simulation time 37683801 ps
CPU time 1.27 seconds
Started Mar 10 03:26:56 PM PDT 24
Finished Mar 10 03:26:58 PM PDT 24
Peak memory 195996 kb
Host smart-2d287c40-668c-43a0-880f-30047bdb522d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286665761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.4286665761
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1908735688
Short name T694
Test name
Test status
Simulation time 49500936 ps
CPU time 1.19 seconds
Started Mar 10 03:26:55 PM PDT 24
Finished Mar 10 03:26:56 PM PDT 24
Peak memory 196756 kb
Host smart-0dde71f0-f082-43d6-ba6a-40ef5c5b2fd7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908735688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1908735688
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3487643905
Short name T658
Test name
Test status
Simulation time 7225088432 ps
CPU time 6.57 seconds
Started Mar 10 03:26:56 PM PDT 24
Finished Mar 10 03:27:03 PM PDT 24
Peak memory 198272 kb
Host smart-80f40568-bae3-4826-b487-8c9d0c3df885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487643905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3487643905
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3984364883
Short name T723
Test name
Test status
Simulation time 91489665 ps
CPU time 1.5 seconds
Started Mar 10 03:26:55 PM PDT 24
Finished Mar 10 03:26:58 PM PDT 24
Peak memory 196428 kb
Host smart-3d15c822-084c-4418-977f-f7262ed2a2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984364883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3984364883
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.455969982
Short name T284
Test name
Test status
Simulation time 35068240 ps
CPU time 1.07 seconds
Started Mar 10 03:26:57 PM PDT 24
Finished Mar 10 03:26:58 PM PDT 24
Peak memory 195740 kb
Host smart-35ae37d0-42d8-4875-b168-07a2ae592fa6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455969982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.455969982
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.2839127293
Short name T685
Test name
Test status
Simulation time 70386845637 ps
CPU time 289.02 seconds
Started Mar 10 03:27:01 PM PDT 24
Finished Mar 10 03:31:50 PM PDT 24
Peak memory 198404 kb
Host smart-5668cb33-3800-43eb-870f-ec3071fb9528
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839127293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.2839127293
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.3360285032
Short name T439
Test name
Test status
Simulation time 55653135259 ps
CPU time 618.49 seconds
Started Mar 10 03:27:12 PM PDT 24
Finished Mar 10 03:37:31 PM PDT 24
Peak memory 198552 kb
Host smart-299bbd71-1965-430a-bcc2-e861abd1600e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3360285032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.3360285032
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1395248084
Short name T60
Test name
Test status
Simulation time 135589404 ps
CPU time 0.6 seconds
Started Mar 10 03:27:05 PM PDT 24
Finished Mar 10 03:27:06 PM PDT 24
Peak memory 194312 kb
Host smart-27c9a36b-8dfb-42f0-b806-71d97a7b390e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395248084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1395248084
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2817692849
Short name T664
Test name
Test status
Simulation time 25567377 ps
CPU time 0.73 seconds
Started Mar 10 03:27:12 PM PDT 24
Finished Mar 10 03:27:13 PM PDT 24
Peak memory 194928 kb
Host smart-19ea14af-b01b-41d6-8b88-b47a2fadf77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817692849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2817692849
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.3503477018
Short name T364
Test name
Test status
Simulation time 113309531 ps
CPU time 4.19 seconds
Started Mar 10 03:27:00 PM PDT 24
Finished Mar 10 03:27:04 PM PDT 24
Peak memory 196132 kb
Host smart-f2390ad9-f8e0-4903-be94-8e537a1472b6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503477018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.3503477018
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1574610876
Short name T234
Test name
Test status
Simulation time 121697717 ps
CPU time 0.97 seconds
Started Mar 10 03:27:07 PM PDT 24
Finished Mar 10 03:27:08 PM PDT 24
Peak memory 197264 kb
Host smart-3e3bb6ed-2faf-4d70-a4e2-9e13e27ae6e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574610876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1574610876
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1977649847
Short name T370
Test name
Test status
Simulation time 44922849 ps
CPU time 1.03 seconds
Started Mar 10 03:27:02 PM PDT 24
Finished Mar 10 03:27:04 PM PDT 24
Peak memory 196612 kb
Host smart-c6b4eda9-50ad-4a11-ae11-e6fdf656677d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977649847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1977649847
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.4200507993
Short name T654
Test name
Test status
Simulation time 458409502 ps
CPU time 3.83 seconds
Started Mar 10 03:27:12 PM PDT 24
Finished Mar 10 03:27:16 PM PDT 24
Peak memory 198332 kb
Host smart-4727ca82-da73-4de8-9e6f-e766ff34ea6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200507993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.4200507993
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1247042589
Short name T437
Test name
Test status
Simulation time 502096781 ps
CPU time 2.6 seconds
Started Mar 10 03:27:01 PM PDT 24
Finished Mar 10 03:27:04 PM PDT 24
Peak memory 197248 kb
Host smart-179dd8d2-428d-4079-89b5-070f2e5383d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247042589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1247042589
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.1077503347
Short name T359
Test name
Test status
Simulation time 44777942 ps
CPU time 1.24 seconds
Started Mar 10 03:27:01 PM PDT 24
Finished Mar 10 03:27:03 PM PDT 24
Peak memory 196072 kb
Host smart-573cfc0e-6afe-4c3d-b7f5-a96dfceb7088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077503347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.1077503347
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.393623579
Short name T650
Test name
Test status
Simulation time 29423496 ps
CPU time 0.71 seconds
Started Mar 10 03:27:12 PM PDT 24
Finished Mar 10 03:27:13 PM PDT 24
Peak memory 194420 kb
Host smart-13a7d8e1-8fc9-450d-a792-2dc94183e07b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393623579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.393623579
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2625038212
Short name T389
Test name
Test status
Simulation time 84617048 ps
CPU time 4.14 seconds
Started Mar 10 03:27:02 PM PDT 24
Finished Mar 10 03:27:06 PM PDT 24
Peak memory 198092 kb
Host smart-26d12fbc-cae7-4985-8f05-e97f3a69e7dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625038212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2625038212
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2868140984
Short name T373
Test name
Test status
Simulation time 301005883 ps
CPU time 1.49 seconds
Started Mar 10 03:27:03 PM PDT 24
Finished Mar 10 03:27:04 PM PDT 24
Peak memory 195644 kb
Host smart-3fcfc848-96a7-4880-9c06-44b75b54a230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868140984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2868140984
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1836268541
Short name T669
Test name
Test status
Simulation time 128217418 ps
CPU time 1.15 seconds
Started Mar 10 03:27:00 PM PDT 24
Finished Mar 10 03:27:02 PM PDT 24
Peak memory 195908 kb
Host smart-e158b278-264f-4c2b-b56d-b4c65f926528
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836268541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1836268541
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.4166356880
Short name T226
Test name
Test status
Simulation time 8696573583 ps
CPU time 111.81 seconds
Started Mar 10 03:27:07 PM PDT 24
Finished Mar 10 03:28:59 PM PDT 24
Peak memory 198332 kb
Host smart-06f1a751-ac46-4b74-95e3-a6aa64dbbbfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166356880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.4166356880
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.479268555
Short name T24
Test name
Test status
Simulation time 72720029585 ps
CPU time 962.16 seconds
Started Mar 10 03:27:05 PM PDT 24
Finished Mar 10 03:43:07 PM PDT 24
Peak memory 198496 kb
Host smart-75b67144-28ff-4996-959f-dfc0ee7963c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=479268555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.479268555
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1410422391
Short name T547
Test name
Test status
Simulation time 12829759 ps
CPU time 0.62 seconds
Started Mar 10 03:27:15 PM PDT 24
Finished Mar 10 03:27:15 PM PDT 24
Peak memory 194156 kb
Host smart-3dc30088-4dec-41fd-bec3-ae9b16e02f36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410422391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1410422391
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3838214237
Short name T673
Test name
Test status
Simulation time 26828012 ps
CPU time 0.82 seconds
Started Mar 10 03:27:07 PM PDT 24
Finished Mar 10 03:27:08 PM PDT 24
Peak memory 196036 kb
Host smart-bcca1b85-19f9-411f-830f-a83164478b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838214237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3838214237
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.630199735
Short name T422
Test name
Test status
Simulation time 2069604153 ps
CPU time 31.03 seconds
Started Mar 10 03:27:09 PM PDT 24
Finished Mar 10 03:27:40 PM PDT 24
Peak memory 197176 kb
Host smart-7889f41e-032d-4ea6-aa2f-d9f9039abce1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630199735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stres
s.630199735
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1207439596
Short name T376
Test name
Test status
Simulation time 242710680 ps
CPU time 1.23 seconds
Started Mar 10 03:27:20 PM PDT 24
Finished Mar 10 03:27:22 PM PDT 24
Peak memory 196588 kb
Host smart-5ffbf0cd-0058-447e-8db8-d5942b7b3e1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207439596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1207439596
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.1631566490
Short name T434
Test name
Test status
Simulation time 36193202 ps
CPU time 1.09 seconds
Started Mar 10 03:27:07 PM PDT 24
Finished Mar 10 03:27:09 PM PDT 24
Peak memory 196240 kb
Host smart-a02efe89-631d-44bc-ad33-cce135b033ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631566490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.1631566490
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3363109446
Short name T397
Test name
Test status
Simulation time 69937102 ps
CPU time 1.54 seconds
Started Mar 10 03:27:09 PM PDT 24
Finished Mar 10 03:27:11 PM PDT 24
Peak memory 196976 kb
Host smart-af264f14-72e2-41d3-9aca-d9101600fc18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363109446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3363109446
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3119647336
Short name T126
Test name
Test status
Simulation time 370596896 ps
CPU time 2.41 seconds
Started Mar 10 03:27:05 PM PDT 24
Finished Mar 10 03:27:08 PM PDT 24
Peak memory 197076 kb
Host smart-13bfdd77-e4f9-4ed5-95e3-8022d66b4078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119647336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3119647336
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.455563713
Short name T416
Test name
Test status
Simulation time 28032866 ps
CPU time 1.04 seconds
Started Mar 10 03:27:05 PM PDT 24
Finished Mar 10 03:27:07 PM PDT 24
Peak memory 196924 kb
Host smart-7142db7c-14e6-47ca-8015-468a72121aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455563713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.455563713
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2067124326
Short name T505
Test name
Test status
Simulation time 80415648 ps
CPU time 0.95 seconds
Started Mar 10 03:27:04 PM PDT 24
Finished Mar 10 03:27:06 PM PDT 24
Peak memory 196044 kb
Host smart-615f1e9a-46e0-42fd-8547-471ff34cac99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067124326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2067124326
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2056314476
Short name T559
Test name
Test status
Simulation time 67628531 ps
CPU time 1.66 seconds
Started Mar 10 03:27:09 PM PDT 24
Finished Mar 10 03:27:11 PM PDT 24
Peak memory 198184 kb
Host smart-27f2ff1e-da7a-4735-a16e-d9b3668bcf7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056314476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2056314476
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1014257891
Short name T589
Test name
Test status
Simulation time 57795883 ps
CPU time 0.88 seconds
Started Mar 10 03:27:04 PM PDT 24
Finished Mar 10 03:27:05 PM PDT 24
Peak memory 195260 kb
Host smart-f7cf0c4e-a725-4287-929c-b6428cb5fdd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014257891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1014257891
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2810331907
Short name T258
Test name
Test status
Simulation time 245788874 ps
CPU time 1.34 seconds
Started Mar 10 03:27:05 PM PDT 24
Finished Mar 10 03:27:07 PM PDT 24
Peak memory 196932 kb
Host smart-796d5ad2-4cb0-4dd6-9d76-e98fa22a17aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810331907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2810331907
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1932621040
Short name T431
Test name
Test status
Simulation time 18724644501 ps
CPU time 233.31 seconds
Started Mar 10 03:27:12 PM PDT 24
Finished Mar 10 03:31:05 PM PDT 24
Peak memory 198336 kb
Host smart-a822a6d3-85c2-425b-a823-79862c7fdc0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932621040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1932621040
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.2011479184
Short name T51
Test name
Test status
Simulation time 61551099137 ps
CPU time 600.71 seconds
Started Mar 10 03:27:36 PM PDT 24
Finished Mar 10 03:37:37 PM PDT 24
Peak memory 198520 kb
Host smart-fc61244b-4b3d-4796-abd6-628f84bc75bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2011479184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.2011479184
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.1644415139
Short name T146
Test name
Test status
Simulation time 13651909 ps
CPU time 0.61 seconds
Started Mar 10 03:27:23 PM PDT 24
Finished Mar 10 03:27:24 PM PDT 24
Peak memory 194836 kb
Host smart-16353b2f-9a78-4a19-94d4-6ad58c5950ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644415139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.1644415139
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.1368944362
Short name T510
Test name
Test status
Simulation time 32836316 ps
CPU time 0.71 seconds
Started Mar 10 03:27:16 PM PDT 24
Finished Mar 10 03:27:17 PM PDT 24
Peak memory 195348 kb
Host smart-9f64d334-5b0b-430b-9847-fcc9ed43cf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368944362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.1368944362
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3587860069
Short name T139
Test name
Test status
Simulation time 10311021148 ps
CPU time 20.03 seconds
Started Mar 10 03:27:19 PM PDT 24
Finished Mar 10 03:27:39 PM PDT 24
Peak memory 198256 kb
Host smart-b8e52a4f-b376-4bc4-a7a5-4f6c21de4e9b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587860069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3587860069
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1219525073
Short name T114
Test name
Test status
Simulation time 91591182 ps
CPU time 1.19 seconds
Started Mar 10 03:27:32 PM PDT 24
Finished Mar 10 03:27:33 PM PDT 24
Peak memory 197860 kb
Host smart-73c8eccb-c106-4a76-a979-b80b1ef72ffa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219525073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1219525073
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3082569969
Short name T393
Test name
Test status
Simulation time 38084156 ps
CPU time 1.2 seconds
Started Mar 10 03:27:24 PM PDT 24
Finished Mar 10 03:27:26 PM PDT 24
Peak memory 196984 kb
Host smart-29142dcc-1db9-46b8-85d1-fb7aa47656b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082569969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3082569969
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3662917511
Short name T665
Test name
Test status
Simulation time 351542682 ps
CPU time 3.38 seconds
Started Mar 10 03:27:20 PM PDT 24
Finished Mar 10 03:27:24 PM PDT 24
Peak memory 196580 kb
Host smart-d7576001-f7e0-4f52-a238-66630d9f7478
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662917511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3662917511
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2973535005
Short name T45
Test name
Test status
Simulation time 401964462 ps
CPU time 3.95 seconds
Started Mar 10 03:27:19 PM PDT 24
Finished Mar 10 03:27:24 PM PDT 24
Peak memory 197300 kb
Host smart-17c791e2-7f89-47ff-b17f-2e18b3850071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973535005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2973535005
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.529833476
Short name T149
Test name
Test status
Simulation time 241788081 ps
CPU time 1.16 seconds
Started Mar 10 03:27:23 PM PDT 24
Finished Mar 10 03:27:24 PM PDT 24
Peak memory 196268 kb
Host smart-aa8b3698-996d-4f04-91d7-ce717c93d6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529833476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.529833476
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2329560118
Short name T630
Test name
Test status
Simulation time 22852558 ps
CPU time 0.94 seconds
Started Mar 10 03:27:17 PM PDT 24
Finished Mar 10 03:27:18 PM PDT 24
Peak memory 194344 kb
Host smart-ee62296c-7911-4bff-884a-92b4e0b4a9bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329560118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2329560118
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2343340663
Short name T608
Test name
Test status
Simulation time 645525860 ps
CPU time 3.06 seconds
Started Mar 10 03:27:33 PM PDT 24
Finished Mar 10 03:27:37 PM PDT 24
Peak memory 198132 kb
Host smart-c10cb119-1dad-4d9f-a3d9-a01d54d7bd7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343340663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2343340663
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1089772694
Short name T336
Test name
Test status
Simulation time 73189290 ps
CPU time 1.45 seconds
Started Mar 10 03:27:20 PM PDT 24
Finished Mar 10 03:27:22 PM PDT 24
Peak memory 195752 kb
Host smart-f912f8a2-fdde-4cd4-8f81-60056254f772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089772694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1089772694
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.17977126
Short name T251
Test name
Test status
Simulation time 72110716 ps
CPU time 1.46 seconds
Started Mar 10 03:27:16 PM PDT 24
Finished Mar 10 03:27:18 PM PDT 24
Peak memory 196056 kb
Host smart-784cd1f8-03df-4e1a-b3f0-fcbec280d11e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17977126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.17977126
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1006140996
Short name T157
Test name
Test status
Simulation time 6562654051 ps
CPU time 55.53 seconds
Started Mar 10 03:27:26 PM PDT 24
Finished Mar 10 03:28:22 PM PDT 24
Peak memory 198304 kb
Host smart-0a4d6c45-08fb-48d7-8558-e1bb4dc5282e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006140996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1006140996
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2186359314
Short name T144
Test name
Test status
Simulation time 108227062 ps
CPU time 0.63 seconds
Started Mar 10 03:27:34 PM PDT 24
Finished Mar 10 03:27:34 PM PDT 24
Peak memory 194024 kb
Host smart-e1aefe61-a2de-41cc-a752-5d9d80c55bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186359314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2186359314
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.1310092354
Short name T235
Test name
Test status
Simulation time 219943120 ps
CPU time 0.68 seconds
Started Mar 10 03:27:27 PM PDT 24
Finished Mar 10 03:27:28 PM PDT 24
Peak memory 194156 kb
Host smart-85dbde23-1f08-4659-b0a5-a26da4df411f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310092354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.1310092354
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.3294214343
Short name T597
Test name
Test status
Simulation time 846137023 ps
CPU time 31.69 seconds
Started Mar 10 03:27:34 PM PDT 24
Finished Mar 10 03:28:06 PM PDT 24
Peak memory 197004 kb
Host smart-8b8415d7-e60d-4cee-87b8-be3be73b7acd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294214343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.3294214343
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3717301090
Short name T691
Test name
Test status
Simulation time 204364697 ps
CPU time 0.89 seconds
Started Mar 10 03:27:33 PM PDT 24
Finished Mar 10 03:27:34 PM PDT 24
Peak memory 196060 kb
Host smart-c7aef43e-be19-44e8-a9b5-5b41ab3b1460
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717301090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3717301090
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.4283503177
Short name T169
Test name
Test status
Simulation time 58498602 ps
CPU time 0.75 seconds
Started Mar 10 03:27:29 PM PDT 24
Finished Mar 10 03:27:31 PM PDT 24
Peak memory 194440 kb
Host smart-f6c7933f-1a27-4259-b8a0-58bb84b7f9d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283503177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.4283503177
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.2609092088
Short name T609
Test name
Test status
Simulation time 114637373 ps
CPU time 4.15 seconds
Started Mar 10 03:27:37 PM PDT 24
Finished Mar 10 03:27:42 PM PDT 24
Peak memory 196476 kb
Host smart-0336d4d8-3a6d-4b18-8334-462cc2a45328
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609092088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.2609092088
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2506193077
Short name T134
Test name
Test status
Simulation time 63328885 ps
CPU time 1.37 seconds
Started Mar 10 03:27:33 PM PDT 24
Finished Mar 10 03:27:35 PM PDT 24
Peak memory 196844 kb
Host smart-09521884-dc24-485c-896b-8a2e44a68dfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506193077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2506193077
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.3959337418
Short name T488
Test name
Test status
Simulation time 228907544 ps
CPU time 1.55 seconds
Started Mar 10 03:27:26 PM PDT 24
Finished Mar 10 03:27:28 PM PDT 24
Peak memory 198240 kb
Host smart-9821440c-1d7e-4ddc-b395-bf80350b16c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959337418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.3959337418
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3051639403
Short name T184
Test name
Test status
Simulation time 95800941 ps
CPU time 0.83 seconds
Started Mar 10 03:27:26 PM PDT 24
Finished Mar 10 03:27:27 PM PDT 24
Peak memory 195620 kb
Host smart-f24e8963-7230-4653-aaf1-f6fae8291187
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051639403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3051639403
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3743889301
Short name T10
Test name
Test status
Simulation time 325337264 ps
CPU time 5 seconds
Started Mar 10 03:27:32 PM PDT 24
Finished Mar 10 03:27:37 PM PDT 24
Peak memory 198120 kb
Host smart-312b9e33-36d3-4dcd-8ec2-62db012a9a54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743889301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3743889301
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.538813904
Short name T118
Test name
Test status
Simulation time 138745378 ps
CPU time 1.52 seconds
Started Mar 10 03:27:22 PM PDT 24
Finished Mar 10 03:27:24 PM PDT 24
Peak memory 195716 kb
Host smart-cd1dcceb-87ef-4a6e-a0a4-8aac823ad605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538813904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.538813904
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3636571547
Short name T503
Test name
Test status
Simulation time 51390061 ps
CPU time 1.11 seconds
Started Mar 10 03:27:27 PM PDT 24
Finished Mar 10 03:27:29 PM PDT 24
Peak memory 196388 kb
Host smart-4f7a57ce-4a57-4510-802d-ad695daf08e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636571547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3636571547
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.994263146
Short name T594
Test name
Test status
Simulation time 24315991844 ps
CPU time 175.7 seconds
Started Mar 10 03:27:32 PM PDT 24
Finished Mar 10 03:30:28 PM PDT 24
Peak memory 198404 kb
Host smart-0dbde6b9-0ddd-40bc-9b69-4f79db762fb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994263146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.994263146
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.628604612
Short name T54
Test name
Test status
Simulation time 949421297372 ps
CPU time 2071.96 seconds
Started Mar 10 03:27:33 PM PDT 24
Finished Mar 10 04:02:05 PM PDT 24
Peak memory 198472 kb
Host smart-616e4a66-adff-4895-be15-4550d847d8db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=628604612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.628604612
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3083254474
Short name T574
Test name
Test status
Simulation time 12710112 ps
CPU time 0.62 seconds
Started Mar 10 03:27:42 PM PDT 24
Finished Mar 10 03:27:43 PM PDT 24
Peak memory 194840 kb
Host smart-414b6a93-e362-415e-a8f8-32cab480b7f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083254474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3083254474
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.710915789
Short name T112
Test name
Test status
Simulation time 80825342 ps
CPU time 0.9 seconds
Started Mar 10 03:27:42 PM PDT 24
Finished Mar 10 03:27:43 PM PDT 24
Peak memory 195976 kb
Host smart-3e851adb-5520-45b9-829d-9691c27df1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710915789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.710915789
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.2033657796
Short name T18
Test name
Test status
Simulation time 186299018 ps
CPU time 7.11 seconds
Started Mar 10 03:27:37 PM PDT 24
Finished Mar 10 03:27:44 PM PDT 24
Peak memory 198144 kb
Host smart-2e28d2a6-0481-44f0-8967-8bf0e7a18dad
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033657796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.2033657796
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3899085220
Short name T435
Test name
Test status
Simulation time 18258740 ps
CPU time 0.64 seconds
Started Mar 10 03:27:39 PM PDT 24
Finished Mar 10 03:27:40 PM PDT 24
Peak memory 194504 kb
Host smart-bbcb7614-bbe5-4ae0-b8c8-dfabde85eb8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899085220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3899085220
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1355981859
Short name T444
Test name
Test status
Simulation time 96347599 ps
CPU time 0.86 seconds
Started Mar 10 03:27:37 PM PDT 24
Finished Mar 10 03:27:38 PM PDT 24
Peak memory 196320 kb
Host smart-fe20457d-23ce-49f3-b4b9-82c16458c9b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355981859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1355981859
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2330954685
Short name T476
Test name
Test status
Simulation time 86985933 ps
CPU time 2.14 seconds
Started Mar 10 03:27:37 PM PDT 24
Finished Mar 10 03:27:40 PM PDT 24
Peak memory 198192 kb
Host smart-7321998c-dad8-4b56-97e7-505d9a4e4892
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330954685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2330954685
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2966657133
Short name T109
Test name
Test status
Simulation time 63573188 ps
CPU time 2.13 seconds
Started Mar 10 03:27:35 PM PDT 24
Finished Mar 10 03:27:38 PM PDT 24
Peak memory 197344 kb
Host smart-85c5d541-cc0a-40d9-83a3-cf1f43d3e773
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966657133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2966657133
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1204422237
Short name T462
Test name
Test status
Simulation time 25960335 ps
CPU time 1.13 seconds
Started Mar 10 03:27:42 PM PDT 24
Finished Mar 10 03:27:44 PM PDT 24
Peak memory 196072 kb
Host smart-3d788dcd-1ac5-45c4-a493-c6309ff60531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204422237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1204422237
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3777630151
Short name T632
Test name
Test status
Simulation time 45944323 ps
CPU time 1.05 seconds
Started Mar 10 03:27:34 PM PDT 24
Finished Mar 10 03:27:35 PM PDT 24
Peak memory 196176 kb
Host smart-fd918f94-a197-4795-9324-6021fd389add
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777630151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3777630151
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.4150609862
Short name T565
Test name
Test status
Simulation time 150092839 ps
CPU time 2.4 seconds
Started Mar 10 03:27:47 PM PDT 24
Finished Mar 10 03:27:49 PM PDT 24
Peak memory 198128 kb
Host smart-3aa539e2-6b35-4d7a-9424-8d3a67b80989
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150609862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.4150609862
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2215890315
Short name T468
Test name
Test status
Simulation time 63713375 ps
CPU time 0.88 seconds
Started Mar 10 03:27:33 PM PDT 24
Finished Mar 10 03:27:35 PM PDT 24
Peak memory 195340 kb
Host smart-b01c41b1-43a1-43dd-ab32-670ebc5b2899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215890315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2215890315
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.744275368
Short name T398
Test name
Test status
Simulation time 75254482 ps
CPU time 1.15 seconds
Started Mar 10 03:27:36 PM PDT 24
Finished Mar 10 03:27:38 PM PDT 24
Peak memory 195976 kb
Host smart-71dd08d0-867e-4d97-9964-29f6aa3335bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744275368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.744275368
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1610261513
Short name T350
Test name
Test status
Simulation time 20525793442 ps
CPU time 160.52 seconds
Started Mar 10 03:27:41 PM PDT 24
Finished Mar 10 03:30:22 PM PDT 24
Peak memory 198308 kb
Host smart-31bfda5b-2f07-4e21-87df-b874a75bed28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610261513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1610261513
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1640070886
Short name T56
Test name
Test status
Simulation time 105121055173 ps
CPU time 547.99 seconds
Started Mar 10 03:27:40 PM PDT 24
Finished Mar 10 03:36:48 PM PDT 24
Peak memory 198488 kb
Host smart-adfb33ac-2e57-4609-a7ad-ae2dd0cef838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1640070886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1640070886
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2794364860
Short name T545
Test name
Test status
Simulation time 13224992 ps
CPU time 0.59 seconds
Started Mar 10 03:27:48 PM PDT 24
Finished Mar 10 03:27:49 PM PDT 24
Peak memory 193784 kb
Host smart-7972f14c-fabc-4d07-9b94-aee0b899a348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794364860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2794364860
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.1402046034
Short name T159
Test name
Test status
Simulation time 45800534 ps
CPU time 0.91 seconds
Started Mar 10 03:27:41 PM PDT 24
Finished Mar 10 03:27:42 PM PDT 24
Peak memory 196708 kb
Host smart-898bda87-e177-41f1-9430-d955d5a3c917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402046034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.1402046034
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.1638477566
Short name T261
Test name
Test status
Simulation time 2201247458 ps
CPU time 26.88 seconds
Started Mar 10 03:27:50 PM PDT 24
Finished Mar 10 03:28:17 PM PDT 24
Peak memory 197024 kb
Host smart-2b79df3d-11de-43a6-86ee-2ed3485f4e67
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638477566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.1638477566
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2484774079
Short name T280
Test name
Test status
Simulation time 196879557 ps
CPU time 1.07 seconds
Started Mar 10 03:27:48 PM PDT 24
Finished Mar 10 03:27:49 PM PDT 24
Peak memory 197312 kb
Host smart-de09bf69-f9b6-48c8-80d1-b760cc07797a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484774079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2484774079
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.206518214
Short name T192
Test name
Test status
Simulation time 86039140 ps
CPU time 1.22 seconds
Started Mar 10 03:27:39 PM PDT 24
Finished Mar 10 03:27:41 PM PDT 24
Peak memory 196036 kb
Host smart-7c1116b4-32dc-4949-b850-f880efe4e4a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206518214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.206518214
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1686714279
Short name T156
Test name
Test status
Simulation time 341297527 ps
CPU time 2.21 seconds
Started Mar 10 03:27:40 PM PDT 24
Finished Mar 10 03:27:42 PM PDT 24
Peak memory 196604 kb
Host smart-12dd10ce-ecbc-44c5-b750-338115f2db33
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686714279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1686714279
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.926781593
Short name T455
Test name
Test status
Simulation time 51500779 ps
CPU time 1.95 seconds
Started Mar 10 03:27:41 PM PDT 24
Finished Mar 10 03:27:43 PM PDT 24
Peak memory 196124 kb
Host smart-a8d524d3-a36e-4563-944d-a5a1aca2ddf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926781593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
926781593
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.794444443
Short name T518
Test name
Test status
Simulation time 53175965 ps
CPU time 0.86 seconds
Started Mar 10 03:27:41 PM PDT 24
Finished Mar 10 03:27:42 PM PDT 24
Peak memory 196320 kb
Host smart-1acadd51-601d-4067-b2bc-02c1e9566497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794444443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.794444443
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2560883680
Short name T177
Test name
Test status
Simulation time 117909786 ps
CPU time 1.52 seconds
Started Mar 10 03:27:40 PM PDT 24
Finished Mar 10 03:27:42 PM PDT 24
Peak memory 197116 kb
Host smart-d1eb601c-c01e-4f4a-a25b-4a309dba3d44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560883680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2560883680
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3908374821
Short name T617
Test name
Test status
Simulation time 2009525586 ps
CPU time 5.77 seconds
Started Mar 10 03:27:48 PM PDT 24
Finished Mar 10 03:27:54 PM PDT 24
Peak memory 197824 kb
Host smart-cb061905-f709-4181-bc04-19b6aaef99e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908374821 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3908374821
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.433598548
Short name T647
Test name
Test status
Simulation time 42891365 ps
CPU time 1.14 seconds
Started Mar 10 03:27:40 PM PDT 24
Finished Mar 10 03:27:42 PM PDT 24
Peak memory 195972 kb
Host smart-eb9118c8-ce45-44f9-9191-868da1dd70d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433598548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.433598548
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1782710425
Short name T349
Test name
Test status
Simulation time 191691333 ps
CPU time 1.55 seconds
Started Mar 10 03:27:41 PM PDT 24
Finished Mar 10 03:27:43 PM PDT 24
Peak memory 195692 kb
Host smart-22c37f8e-072a-4e3b-a29e-8c8cda5ef91d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782710425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1782710425
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1964512085
Short name T252
Test name
Test status
Simulation time 4709883773 ps
CPU time 32.07 seconds
Started Mar 10 03:27:45 PM PDT 24
Finished Mar 10 03:28:17 PM PDT 24
Peak memory 198276 kb
Host smart-7be619ac-1ae4-4583-9dfe-78c24fb3261b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964512085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1964512085
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2963237875
Short name T710
Test name
Test status
Simulation time 22138432 ps
CPU time 0.6 seconds
Started Mar 10 03:27:54 PM PDT 24
Finished Mar 10 03:27:55 PM PDT 24
Peak memory 194100 kb
Host smart-0f861694-af99-40a7-88ec-43a4cf833984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963237875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2963237875
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1818937666
Short name T530
Test name
Test status
Simulation time 42634633 ps
CPU time 0.86 seconds
Started Mar 10 03:27:49 PM PDT 24
Finished Mar 10 03:27:49 PM PDT 24
Peak memory 195452 kb
Host smart-f1eb1339-bace-45d6-9754-9864575fff71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818937666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1818937666
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.3963394323
Short name T332
Test name
Test status
Simulation time 1535103150 ps
CPU time 21.99 seconds
Started Mar 10 03:27:49 PM PDT 24
Finished Mar 10 03:28:11 PM PDT 24
Peak memory 196664 kb
Host smart-af5b5976-eea1-4993-abf3-059144b2bc70
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963394323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.3963394323
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.199830491
Short name T153
Test name
Test status
Simulation time 344158265 ps
CPU time 0.95 seconds
Started Mar 10 03:28:03 PM PDT 24
Finished Mar 10 03:28:04 PM PDT 24
Peak memory 196132 kb
Host smart-0d8b5129-17c7-465f-bf33-2e9b67224b13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199830491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.199830491
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.386176461
Short name T120
Test name
Test status
Simulation time 100928506 ps
CPU time 1.42 seconds
Started Mar 10 03:27:49 PM PDT 24
Finished Mar 10 03:27:51 PM PDT 24
Peak memory 197220 kb
Host smart-2216e49f-5613-4c0a-8dcf-4b0849e17489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386176461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.386176461
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1000090814
Short name T627
Test name
Test status
Simulation time 110727820 ps
CPU time 2.62 seconds
Started Mar 10 03:27:48 PM PDT 24
Finished Mar 10 03:27:51 PM PDT 24
Peak memory 198216 kb
Host smart-8ecd303a-ce21-42fb-aa78-371193e45eb4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000090814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1000090814
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3064031082
Short name T616
Test name
Test status
Simulation time 210295568 ps
CPU time 4.13 seconds
Started Mar 10 03:27:48 PM PDT 24
Finished Mar 10 03:27:53 PM PDT 24
Peak memory 197284 kb
Host smart-b2500217-9ae4-483f-a815-75f1d990dc19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064031082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3064031082
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3495377735
Short name T66
Test name
Test status
Simulation time 50096441 ps
CPU time 0.92 seconds
Started Mar 10 03:27:42 PM PDT 24
Finished Mar 10 03:27:43 PM PDT 24
Peak memory 196812 kb
Host smart-0ca6d3fb-f59a-4f2f-ae94-7ef2ff713287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495377735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3495377735
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.2408478375
Short name T495
Test name
Test status
Simulation time 92528472 ps
CPU time 1.16 seconds
Started Mar 10 03:28:10 PM PDT 24
Finished Mar 10 03:28:12 PM PDT 24
Peak memory 196092 kb
Host smart-e669bd33-2db5-4657-abc5-9d9a4a1d8e6c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408478375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.2408478375
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.343110728
Short name T339
Test name
Test status
Simulation time 537540965 ps
CPU time 5.12 seconds
Started Mar 10 03:27:49 PM PDT 24
Finished Mar 10 03:27:54 PM PDT 24
Peak memory 198112 kb
Host smart-7ab5d02b-68a1-45d7-9f8d-7a68825de979
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343110728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.343110728
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2638570108
Short name T403
Test name
Test status
Simulation time 163974576 ps
CPU time 1.25 seconds
Started Mar 10 03:27:42 PM PDT 24
Finished Mar 10 03:27:44 PM PDT 24
Peak memory 196984 kb
Host smart-d8e5af28-503a-4d62-851c-ff60a772ee8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638570108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2638570108
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2794590026
Short name T432
Test name
Test status
Simulation time 210490442 ps
CPU time 1.22 seconds
Started Mar 10 03:27:45 PM PDT 24
Finished Mar 10 03:27:47 PM PDT 24
Peak memory 196624 kb
Host smart-171e0cd8-65b1-4f74-8bae-a8cfc1136443
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794590026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2794590026
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1484888241
Short name T382
Test name
Test status
Simulation time 33001778078 ps
CPU time 213.8 seconds
Started Mar 10 03:27:55 PM PDT 24
Finished Mar 10 03:31:29 PM PDT 24
Peak memory 198364 kb
Host smart-be5b3641-a7b1-47d1-b265-96425bdff485
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484888241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1484888241
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.4104319037
Short name T67
Test name
Test status
Simulation time 319821001409 ps
CPU time 1787.25 seconds
Started Mar 10 03:27:58 PM PDT 24
Finished Mar 10 03:57:46 PM PDT 24
Peak memory 198524 kb
Host smart-f82c81c9-b5f4-472a-af42-908eb7a8867b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4104319037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.4104319037
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2401217849
Short name T571
Test name
Test status
Simulation time 13837948 ps
CPU time 0.64 seconds
Started Mar 10 03:28:04 PM PDT 24
Finished Mar 10 03:28:05 PM PDT 24
Peak memory 194084 kb
Host smart-e7fcc83e-295c-4949-9a80-3311a1d7d58b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401217849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2401217849
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1482244749
Short name T131
Test name
Test status
Simulation time 126001436 ps
CPU time 0.71 seconds
Started Mar 10 03:28:06 PM PDT 24
Finished Mar 10 03:28:07 PM PDT 24
Peak memory 194228 kb
Host smart-229ff4dc-8d41-49a9-a08b-ce5e06451368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482244749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1482244749
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.731306709
Short name T129
Test name
Test status
Simulation time 792664345 ps
CPU time 22.85 seconds
Started Mar 10 03:28:01 PM PDT 24
Finished Mar 10 03:28:24 PM PDT 24
Peak memory 195696 kb
Host smart-407c44e8-7dd1-48a1-9eb3-9b1dcbc74ca1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731306709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.731306709
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.865456358
Short name T709
Test name
Test status
Simulation time 56715919 ps
CPU time 1.17 seconds
Started Mar 10 03:28:05 PM PDT 24
Finished Mar 10 03:28:06 PM PDT 24
Peak memory 196812 kb
Host smart-02191c00-a40c-4504-80fb-114e176a3c76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865456358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.865456358
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1210988441
Short name T562
Test name
Test status
Simulation time 108495233 ps
CPU time 1.11 seconds
Started Mar 10 03:28:01 PM PDT 24
Finished Mar 10 03:28:02 PM PDT 24
Peak memory 196316 kb
Host smart-e82920ad-b744-4aa0-85c5-04151d27fd18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210988441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1210988441
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1331731252
Short name T622
Test name
Test status
Simulation time 350633233 ps
CPU time 3.85 seconds
Started Mar 10 03:28:00 PM PDT 24
Finished Mar 10 03:28:05 PM PDT 24
Peak memory 198240 kb
Host smart-6261ecb4-c94c-4cc2-bd9b-91b6f89e3459
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331731252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1331731252
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.2125079819
Short name T14
Test name
Test status
Simulation time 117007980 ps
CPU time 3.13 seconds
Started Mar 10 03:27:58 PM PDT 24
Finished Mar 10 03:28:02 PM PDT 24
Peak memory 197276 kb
Host smart-39b05220-cdab-4e60-a97d-26fb0a372c9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125079819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.2125079819
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1732964202
Short name T249
Test name
Test status
Simulation time 134836425 ps
CPU time 1.34 seconds
Started Mar 10 03:28:01 PM PDT 24
Finished Mar 10 03:28:03 PM PDT 24
Peak memory 198240 kb
Host smart-8cb6d13d-37f3-4027-9ab5-b0dd33681412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732964202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1732964202
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1110333989
Short name T230
Test name
Test status
Simulation time 90097644 ps
CPU time 1.22 seconds
Started Mar 10 03:27:59 PM PDT 24
Finished Mar 10 03:28:01 PM PDT 24
Peak memory 196020 kb
Host smart-3b1188ee-c872-4848-b6b1-b1be890d4263
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110333989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1110333989
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1927310103
Short name T458
Test name
Test status
Simulation time 290256573 ps
CPU time 1.81 seconds
Started Mar 10 03:28:02 PM PDT 24
Finished Mar 10 03:28:04 PM PDT 24
Peak memory 198200 kb
Host smart-c7c80294-ce3a-4bcf-acfa-4770588e0b11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927310103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1927310103
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.4059939616
Short name T209
Test name
Test status
Simulation time 358069731 ps
CPU time 1.49 seconds
Started Mar 10 03:27:53 PM PDT 24
Finished Mar 10 03:27:55 PM PDT 24
Peak memory 195792 kb
Host smart-dd794b4a-c606-4f57-a94c-88fc76abbbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059939616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.4059939616
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3652224054
Short name T644
Test name
Test status
Simulation time 159851416 ps
CPU time 1.43 seconds
Started Mar 10 03:27:59 PM PDT 24
Finished Mar 10 03:28:01 PM PDT 24
Peak memory 196368 kb
Host smart-3c8007d2-9fd1-42cf-8dcf-ef55d10fe5fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652224054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3652224054
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.684211417
Short name T683
Test name
Test status
Simulation time 23672068758 ps
CPU time 172.47 seconds
Started Mar 10 03:28:03 PM PDT 24
Finished Mar 10 03:30:56 PM PDT 24
Peak memory 198388 kb
Host smart-b647cd65-383c-45a1-a20e-8492594e4323
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684211417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.g
pio_stress_all.684211417
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.2348862716
Short name T702
Test name
Test status
Simulation time 156972714717 ps
CPU time 1678.32 seconds
Started Mar 10 03:28:04 PM PDT 24
Finished Mar 10 03:56:02 PM PDT 24
Peak memory 198440 kb
Host smart-5591b58a-acc3-4fb8-8983-6c2109cf910a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2348862716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.2348862716
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2865560717
Short name T478
Test name
Test status
Simulation time 13766828 ps
CPU time 0.58 seconds
Started Mar 10 03:25:04 PM PDT 24
Finished Mar 10 03:25:05 PM PDT 24
Peak memory 194792 kb
Host smart-ad555e32-7cf2-42a5-a73f-a45e33cd41b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865560717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2865560717
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1422692430
Short name T319
Test name
Test status
Simulation time 41109776 ps
CPU time 1.06 seconds
Started Mar 10 03:24:56 PM PDT 24
Finished Mar 10 03:24:57 PM PDT 24
Peak memory 197216 kb
Host smart-3741e3e9-de22-483f-9530-bd36d0d0bce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422692430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1422692430
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2492201573
Short name T165
Test name
Test status
Simulation time 102058365 ps
CPU time 3.94 seconds
Started Mar 10 03:25:06 PM PDT 24
Finished Mar 10 03:25:10 PM PDT 24
Peak memory 196384 kb
Host smart-fe182161-3eba-4774-a16c-1a6da21c51e5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492201573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2492201573
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2405820632
Short name T629
Test name
Test status
Simulation time 172805481 ps
CPU time 0.87 seconds
Started Mar 10 03:25:00 PM PDT 24
Finished Mar 10 03:25:01 PM PDT 24
Peak memory 196176 kb
Host smart-ec5bf65f-213f-455e-8089-f223bc3ef0dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405820632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2405820632
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1502134294
Short name T639
Test name
Test status
Simulation time 94376859 ps
CPU time 1.15 seconds
Started Mar 10 03:24:57 PM PDT 24
Finished Mar 10 03:24:58 PM PDT 24
Peak memory 195896 kb
Host smart-27719cdb-1f51-46a5-927e-b60b3c28c237
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502134294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1502134294
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.438212588
Short name T175
Test name
Test status
Simulation time 284363991 ps
CPU time 3.31 seconds
Started Mar 10 03:24:55 PM PDT 24
Finished Mar 10 03:24:58 PM PDT 24
Peak memory 198168 kb
Host smart-594a3eb2-25bd-431e-9249-e5c501c3ca99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438212588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.gpio_intr_with_filter_rand_intr_event.438212588
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.76688768
Short name T515
Test name
Test status
Simulation time 208171030 ps
CPU time 4.63 seconds
Started Mar 10 03:25:09 PM PDT 24
Finished Mar 10 03:25:14 PM PDT 24
Peak memory 198192 kb
Host smart-410a222b-5be2-482a-a0e6-f6ae1fcc3709
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76688768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.76688768
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3953034643
Short name T399
Test name
Test status
Simulation time 53683305 ps
CPU time 1.11 seconds
Started Mar 10 03:24:53 PM PDT 24
Finished Mar 10 03:24:54 PM PDT 24
Peak memory 196908 kb
Host smart-2e93138b-b79a-49ab-a284-44a3229d46f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953034643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3953034643
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1358378805
Short name T404
Test name
Test status
Simulation time 243677967 ps
CPU time 1.21 seconds
Started Mar 10 03:24:54 PM PDT 24
Finished Mar 10 03:24:55 PM PDT 24
Peak memory 196224 kb
Host smart-2f17c94b-bbc1-422a-9da6-9a9bd8be4190
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358378805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1358378805
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1205765046
Short name T357
Test name
Test status
Simulation time 461820318 ps
CPU time 2.03 seconds
Started Mar 10 03:24:59 PM PDT 24
Finished Mar 10 03:25:01 PM PDT 24
Peak memory 198112 kb
Host smart-98107330-ccb2-425f-9186-037d3dbcd613
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205765046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1205765046
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1938075814
Short name T42
Test name
Test status
Simulation time 127826455 ps
CPU time 1 seconds
Started Mar 10 03:25:04 PM PDT 24
Finished Mar 10 03:25:05 PM PDT 24
Peak memory 213760 kb
Host smart-e046a4ff-0f70-4988-9d4d-2661883c8397
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938075814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1938075814
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.502779778
Short name T501
Test name
Test status
Simulation time 165459221 ps
CPU time 1.09 seconds
Started Mar 10 03:24:50 PM PDT 24
Finished Mar 10 03:24:51 PM PDT 24
Peak memory 195868 kb
Host smart-e0787095-93e5-4c4f-bb4f-5dea031963ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502779778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.502779778
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3873363000
Short name T578
Test name
Test status
Simulation time 106181667 ps
CPU time 0.94 seconds
Started Mar 10 03:24:55 PM PDT 24
Finished Mar 10 03:24:56 PM PDT 24
Peak memory 196548 kb
Host smart-6db65be1-5ba2-479d-ae69-2126da14db0c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873363000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3873363000
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2373611415
Short name T413
Test name
Test status
Simulation time 20291797716 ps
CPU time 165.83 seconds
Started Mar 10 03:25:03 PM PDT 24
Finished Mar 10 03:27:48 PM PDT 24
Peak memory 198332 kb
Host smart-87f79ed9-3111-4803-a3ae-41c18c99033c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373611415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2373611415
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1206368538
Short name T724
Test name
Test status
Simulation time 16096873 ps
CPU time 0.61 seconds
Started Mar 10 03:28:12 PM PDT 24
Finished Mar 10 03:28:12 PM PDT 24
Peak memory 194072 kb
Host smart-b1b633ce-9841-45b9-8188-42cc715acd0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206368538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1206368538
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2803843987
Short name T695
Test name
Test status
Simulation time 64962290 ps
CPU time 0.68 seconds
Started Mar 10 03:28:08 PM PDT 24
Finished Mar 10 03:28:09 PM PDT 24
Peak memory 194864 kb
Host smart-a9888226-5d09-4d88-be3d-9d819a65e2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803843987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2803843987
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3101523146
Short name T207
Test name
Test status
Simulation time 731462221 ps
CPU time 21.88 seconds
Started Mar 10 03:28:12 PM PDT 24
Finished Mar 10 03:28:34 PM PDT 24
Peak memory 196440 kb
Host smart-11ee45aa-5059-4b91-b0e4-4f15019319dd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101523146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3101523146
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.428153763
Short name T531
Test name
Test status
Simulation time 285282732 ps
CPU time 1.2 seconds
Started Mar 10 03:28:22 PM PDT 24
Finished Mar 10 03:28:23 PM PDT 24
Peak memory 196764 kb
Host smart-0b2905f8-f3fd-4272-8829-e8657cefca4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428153763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.428153763
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2057492455
Short name T133
Test name
Test status
Simulation time 255046474 ps
CPU time 1.33 seconds
Started Mar 10 03:28:11 PM PDT 24
Finished Mar 10 03:28:12 PM PDT 24
Peak memory 196172 kb
Host smart-f84a0110-dcc1-4e6e-a90a-e31b4a68bca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057492455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2057492455
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3986005711
Short name T23
Test name
Test status
Simulation time 132437461 ps
CPU time 3.07 seconds
Started Mar 10 03:28:15 PM PDT 24
Finished Mar 10 03:28:18 PM PDT 24
Peak memory 198268 kb
Host smart-ae4f8afc-4579-455f-b9e4-1d47c9674031
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986005711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3986005711
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.858925522
Short name T651
Test name
Test status
Simulation time 1085581773 ps
CPU time 2.27 seconds
Started Mar 10 03:28:12 PM PDT 24
Finished Mar 10 03:28:15 PM PDT 24
Peak memory 196448 kb
Host smart-688e7673-6393-43b1-a55d-1e557b3a725a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858925522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger.
858925522
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3491408594
Short name T536
Test name
Test status
Simulation time 23719261 ps
CPU time 1.03 seconds
Started Mar 10 03:28:13 PM PDT 24
Finished Mar 10 03:28:14 PM PDT 24
Peak memory 196032 kb
Host smart-5cb793cd-5b82-4a7f-8636-ccc15ade8a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491408594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3491408594
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2797885376
Short name T676
Test name
Test status
Simulation time 166910737 ps
CPU time 1.39 seconds
Started Mar 10 03:28:08 PM PDT 24
Finished Mar 10 03:28:10 PM PDT 24
Peak memory 198208 kb
Host smart-7291130e-03fa-4770-a725-d3261caa6c3c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797885376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2797885376
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1125916436
Short name T318
Test name
Test status
Simulation time 273257106 ps
CPU time 3.83 seconds
Started Mar 10 03:28:12 PM PDT 24
Finished Mar 10 03:28:16 PM PDT 24
Peak memory 198180 kb
Host smart-8e24026a-6953-48a1-96ae-078941528c1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125916436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1125916436
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3793622900
Short name T212
Test name
Test status
Simulation time 165011087 ps
CPU time 0.8 seconds
Started Mar 10 03:28:04 PM PDT 24
Finished Mar 10 03:28:05 PM PDT 24
Peak memory 194260 kb
Host smart-7bfe633a-e6a0-4793-a01d-6d02abb80d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793622900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3793622900
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.3572998673
Short name T438
Test name
Test status
Simulation time 67468777 ps
CPU time 1.58 seconds
Started Mar 10 03:28:06 PM PDT 24
Finished Mar 10 03:28:08 PM PDT 24
Peak memory 196896 kb
Host smart-fc5acc2f-a3f1-434f-b775-2b909f94f62f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572998673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.3572998673
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.758783194
Short name T623
Test name
Test status
Simulation time 22117092746 ps
CPU time 165.14 seconds
Started Mar 10 03:28:21 PM PDT 24
Finished Mar 10 03:31:07 PM PDT 24
Peak memory 198324 kb
Host smart-ad617f92-a0c8-4810-ba6d-de983b8dc7bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758783194 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.758783194
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.849278460
Short name T98
Test name
Test status
Simulation time 101730868397 ps
CPU time 2161.78 seconds
Started Mar 10 03:28:13 PM PDT 24
Finished Mar 10 04:04:15 PM PDT 24
Peak memory 198504 kb
Host smart-682e6937-11c7-46b0-a40b-3a177d0db2b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=849278460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.849278460
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.237353305
Short name T137
Test name
Test status
Simulation time 20059416 ps
CPU time 0.64 seconds
Started Mar 10 03:28:19 PM PDT 24
Finished Mar 10 03:28:20 PM PDT 24
Peak memory 194828 kb
Host smart-b24df7a9-329e-4f20-9bb6-3bc2503ee3c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237353305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.237353305
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2009257497
Short name T414
Test name
Test status
Simulation time 27645232 ps
CPU time 0.76 seconds
Started Mar 10 03:28:17 PM PDT 24
Finished Mar 10 03:28:18 PM PDT 24
Peak memory 194264 kb
Host smart-7c0e4833-9a2f-4aa4-be6e-05b4c6b1bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009257497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2009257497
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3049934975
Short name T467
Test name
Test status
Simulation time 536661333 ps
CPU time 20.96 seconds
Started Mar 10 03:28:19 PM PDT 24
Finished Mar 10 03:28:40 PM PDT 24
Peak memory 198216 kb
Host smart-6a718946-4610-4583-9fa1-538fea4e1a31
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049934975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3049934975
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1163004166
Short name T721
Test name
Test status
Simulation time 160539894 ps
CPU time 0.86 seconds
Started Mar 10 03:28:16 PM PDT 24
Finished Mar 10 03:28:18 PM PDT 24
Peak memory 196628 kb
Host smart-7650f5eb-9f5f-406e-aa0f-d3b0cbc82faa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163004166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1163004166
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.4234015104
Short name T561
Test name
Test status
Simulation time 124539896 ps
CPU time 1.14 seconds
Started Mar 10 03:28:15 PM PDT 24
Finished Mar 10 03:28:17 PM PDT 24
Peak memory 196952 kb
Host smart-aa8cd04a-7762-4b08-8ccd-2e404d1a6ff5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234015104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.4234015104
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.1092013352
Short name T527
Test name
Test status
Simulation time 255454378 ps
CPU time 2.88 seconds
Started Mar 10 03:28:16 PM PDT 24
Finished Mar 10 03:28:19 PM PDT 24
Peak memory 198308 kb
Host smart-8e587499-4825-43f5-a117-df5de4b31ec3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092013352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.1092013352
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3697370519
Short name T385
Test name
Test status
Simulation time 77172126 ps
CPU time 1.27 seconds
Started Mar 10 03:28:21 PM PDT 24
Finished Mar 10 03:28:23 PM PDT 24
Peak memory 196260 kb
Host smart-7e4c6dc4-6866-4231-8aaa-6d110cd694ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697370519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3697370519
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2326962133
Short name T506
Test name
Test status
Simulation time 58203191 ps
CPU time 1.01 seconds
Started Mar 10 03:28:15 PM PDT 24
Finished Mar 10 03:28:17 PM PDT 24
Peak memory 196872 kb
Host smart-e9c982b7-5dfb-480b-a20c-a1f698226ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326962133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2326962133
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1977452532
Short name T287
Test name
Test status
Simulation time 52755685 ps
CPU time 1.25 seconds
Started Mar 10 03:28:16 PM PDT 24
Finished Mar 10 03:28:17 PM PDT 24
Peak memory 196276 kb
Host smart-14ee2c4b-e4f7-4699-92f4-6d653d787f06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977452532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1977452532
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3020077991
Short name T247
Test name
Test status
Simulation time 1556298552 ps
CPU time 6.07 seconds
Started Mar 10 03:28:19 PM PDT 24
Finished Mar 10 03:28:26 PM PDT 24
Peak memory 198156 kb
Host smart-07ed7827-fb36-4862-ac24-d4f171830309
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020077991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3020077991
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.655857978
Short name T15
Test name
Test status
Simulation time 236068129 ps
CPU time 1.26 seconds
Started Mar 10 03:28:11 PM PDT 24
Finished Mar 10 03:28:13 PM PDT 24
Peak memory 195912 kb
Host smart-07dc31ac-3ece-4112-a7e0-4d7df624fbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655857978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.655857978
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1705449903
Short name T575
Test name
Test status
Simulation time 47515732 ps
CPU time 1.38 seconds
Started Mar 10 03:28:13 PM PDT 24
Finished Mar 10 03:28:15 PM PDT 24
Peak memory 198172 kb
Host smart-4f67f637-bebe-4ec9-854b-75880b0a4622
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705449903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1705449903
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.3786695069
Short name T358
Test name
Test status
Simulation time 12383804877 ps
CPU time 100.47 seconds
Started Mar 10 03:28:13 PM PDT 24
Finished Mar 10 03:29:54 PM PDT 24
Peak memory 198352 kb
Host smart-33ea6279-0dca-4bb1-97b3-e57be315d047
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786695069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.3786695069
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.4286654668
Short name T568
Test name
Test status
Simulation time 18666689916 ps
CPU time 305.26 seconds
Started Mar 10 03:28:15 PM PDT 24
Finished Mar 10 03:33:21 PM PDT 24
Peak memory 198404 kb
Host smart-66d100e6-0a97-4f69-b30e-cdcc9aff44ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4286654668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.4286654668
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.2395146432
Short name T323
Test name
Test status
Simulation time 24564567 ps
CPU time 0.65 seconds
Started Mar 10 03:28:28 PM PDT 24
Finished Mar 10 03:28:29 PM PDT 24
Peak memory 194096 kb
Host smart-b5de3f05-d3aa-435a-8137-5001a4018c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395146432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.2395146432
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.418404466
Short name T586
Test name
Test status
Simulation time 87975693 ps
CPU time 0.86 seconds
Started Mar 10 03:28:24 PM PDT 24
Finished Mar 10 03:28:25 PM PDT 24
Peak memory 195472 kb
Host smart-a7e87091-a2c4-438c-9347-f22e14e9d28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418404466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.418404466
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.3421061728
Short name T125
Test name
Test status
Simulation time 240191500 ps
CPU time 12.35 seconds
Started Mar 10 03:28:22 PM PDT 24
Finished Mar 10 03:28:34 PM PDT 24
Peak memory 195696 kb
Host smart-0dc5e366-2bc1-42f2-a658-2d8e4da6d536
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421061728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.3421061728
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2203447414
Short name T355
Test name
Test status
Simulation time 98294023 ps
CPU time 1.24 seconds
Started Mar 10 03:28:28 PM PDT 24
Finished Mar 10 03:28:30 PM PDT 24
Peak memory 196508 kb
Host smart-433f93b0-93ed-430c-accc-d1c0ee3c9ebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203447414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2203447414
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2168123706
Short name T513
Test name
Test status
Simulation time 196147253 ps
CPU time 1.37 seconds
Started Mar 10 03:28:21 PM PDT 24
Finished Mar 10 03:28:23 PM PDT 24
Peak memory 197340 kb
Host smart-2596f193-e27a-4121-9755-ea92f130c9aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168123706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2168123706
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.738531325
Short name T140
Test name
Test status
Simulation time 69990498 ps
CPU time 1.91 seconds
Started Mar 10 03:28:20 PM PDT 24
Finished Mar 10 03:28:22 PM PDT 24
Peak memory 198236 kb
Host smart-a96728c4-277b-489b-959d-f696298ae81a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738531325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.738531325
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2885426040
Short name T248
Test name
Test status
Simulation time 182637169 ps
CPU time 3.26 seconds
Started Mar 10 03:28:20 PM PDT 24
Finished Mar 10 03:28:24 PM PDT 24
Peak memory 197432 kb
Host smart-78191c89-7fe8-4ef5-85dc-5aac2d0056f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885426040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2885426040
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2347094518
Short name T63
Test name
Test status
Simulation time 66724174 ps
CPU time 1.04 seconds
Started Mar 10 03:28:19 PM PDT 24
Finished Mar 10 03:28:21 PM PDT 24
Peak memory 196852 kb
Host smart-5d967034-6cc8-4c52-a2d3-5cad3d6af52f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347094518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2347094518
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2501304409
Short name T509
Test name
Test status
Simulation time 59383662 ps
CPU time 1.42 seconds
Started Mar 10 03:28:21 PM PDT 24
Finished Mar 10 03:28:23 PM PDT 24
Peak memory 197208 kb
Host smart-8214d0d8-8c1e-4acb-a532-79699a853be0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501304409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2501304409
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3870049090
Short name T537
Test name
Test status
Simulation time 96999475 ps
CPU time 4.6 seconds
Started Mar 10 03:28:20 PM PDT 24
Finished Mar 10 03:28:25 PM PDT 24
Peak memory 198016 kb
Host smart-158d1bad-b3e5-47e7-b4f5-9a5f741dd246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870049090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3870049090
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3918816202
Short name T649
Test name
Test status
Simulation time 44003748 ps
CPU time 1.33 seconds
Started Mar 10 03:28:20 PM PDT 24
Finished Mar 10 03:28:22 PM PDT 24
Peak memory 196960 kb
Host smart-44b7a3ed-062d-4ecd-b1fa-34598c67d194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918816202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3918816202
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.309552501
Short name T472
Test name
Test status
Simulation time 22705384 ps
CPU time 0.83 seconds
Started Mar 10 03:28:23 PM PDT 24
Finished Mar 10 03:28:24 PM PDT 24
Peak memory 195372 kb
Host smart-1f4cd015-095f-4f09-967b-0f4b55f781df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309552501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.309552501
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.2060401291
Short name T322
Test name
Test status
Simulation time 11538923054 ps
CPU time 183.08 seconds
Started Mar 10 03:28:26 PM PDT 24
Finished Mar 10 03:31:29 PM PDT 24
Peak memory 198336 kb
Host smart-8c364bdc-4d68-4329-8256-1430a4755f27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060401291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.2060401291
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1010433053
Short name T290
Test name
Test status
Simulation time 14240193 ps
CPU time 0.6 seconds
Started Mar 10 03:28:29 PM PDT 24
Finished Mar 10 03:28:30 PM PDT 24
Peak memory 194844 kb
Host smart-bca11c8f-17f6-410b-aa85-415bcf28bc34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010433053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1010433053
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.1930158140
Short name T331
Test name
Test status
Simulation time 59974148 ps
CPU time 0.89 seconds
Started Mar 10 03:28:32 PM PDT 24
Finished Mar 10 03:28:33 PM PDT 24
Peak memory 195508 kb
Host smart-34e902b0-8c4d-4d91-a84f-f02e05775b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930158140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.1930158140
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.1976742134
Short name T206
Test name
Test status
Simulation time 653542754 ps
CPU time 20.58 seconds
Started Mar 10 03:28:32 PM PDT 24
Finished Mar 10 03:28:53 PM PDT 24
Peak memory 198148 kb
Host smart-d5bbbd60-ee30-41ff-a225-0105144c01ab
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976742134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.1976742134
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1131022383
Short name T588
Test name
Test status
Simulation time 264597614 ps
CPU time 0.92 seconds
Started Mar 10 03:28:28 PM PDT 24
Finished Mar 10 03:28:29 PM PDT 24
Peak memory 197180 kb
Host smart-57186563-0b4b-4756-86ef-a3f57ffed6c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131022383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1131022383
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.2163115206
Short name T498
Test name
Test status
Simulation time 127964157 ps
CPU time 1.21 seconds
Started Mar 10 03:28:26 PM PDT 24
Finished Mar 10 03:28:28 PM PDT 24
Peak memory 196612 kb
Host smart-34cec2ec-3ff1-4f5a-a32e-03523a72ae65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163115206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.2163115206
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3777317281
Short name T368
Test name
Test status
Simulation time 342537722 ps
CPU time 3.77 seconds
Started Mar 10 03:28:29 PM PDT 24
Finished Mar 10 03:28:33 PM PDT 24
Peak memory 198212 kb
Host smart-939fb8cb-1192-48ca-8f79-b373606b9670
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777317281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3777317281
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1846444249
Short name T394
Test name
Test status
Simulation time 331425319 ps
CPU time 2.66 seconds
Started Mar 10 03:28:32 PM PDT 24
Finished Mar 10 03:28:35 PM PDT 24
Peak memory 197380 kb
Host smart-aa8f9a47-be11-4e53-9dc2-432a1884b97a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846444249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1846444249
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.385657794
Short name T152
Test name
Test status
Simulation time 88145258 ps
CPU time 0.86 seconds
Started Mar 10 03:28:24 PM PDT 24
Finished Mar 10 03:28:25 PM PDT 24
Peak memory 195656 kb
Host smart-133d10e0-20a5-4e2d-8328-3c45c1b409c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385657794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.385657794
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.595291647
Short name T299
Test name
Test status
Simulation time 60833401 ps
CPU time 1.19 seconds
Started Mar 10 03:28:24 PM PDT 24
Finished Mar 10 03:28:25 PM PDT 24
Peak memory 197292 kb
Host smart-5b01a80e-9cb5-47fe-a5f1-6365d81c61fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595291647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.595291647
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.1037581322
Short name T558
Test name
Test status
Simulation time 51603099 ps
CPU time 1.36 seconds
Started Mar 10 03:28:30 PM PDT 24
Finished Mar 10 03:28:32 PM PDT 24
Peak memory 198148 kb
Host smart-5547d96d-669f-4380-a8cc-46079163f3ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037581322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.1037581322
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.406359079
Short name T666
Test name
Test status
Simulation time 173526168 ps
CPU time 1.02 seconds
Started Mar 10 03:28:27 PM PDT 24
Finished Mar 10 03:28:29 PM PDT 24
Peak memory 196432 kb
Host smart-b8bf6b29-0ef5-4a0b-a693-742d4842ee0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406359079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.406359079
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2340223888
Short name T367
Test name
Test status
Simulation time 49044016 ps
CPU time 1.37 seconds
Started Mar 10 03:28:31 PM PDT 24
Finished Mar 10 03:28:33 PM PDT 24
Peak memory 197136 kb
Host smart-0713a5d4-e94d-4a25-8062-5a047928acaf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340223888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2340223888
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2846476634
Short name T122
Test name
Test status
Simulation time 1452098196 ps
CPU time 44.02 seconds
Started Mar 10 03:28:31 PM PDT 24
Finished Mar 10 03:29:16 PM PDT 24
Peak memory 198172 kb
Host smart-2089e8c7-b8ad-40c6-95a7-d447b30f06a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846476634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2846476634
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.1575640512
Short name T408
Test name
Test status
Simulation time 15812462 ps
CPU time 0.6 seconds
Started Mar 10 03:28:39 PM PDT 24
Finished Mar 10 03:28:40 PM PDT 24
Peak memory 194108 kb
Host smart-acf87c72-9a76-4de5-bfb3-787ab8f8a7cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575640512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.1575640512
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.13771574
Short name T496
Test name
Test status
Simulation time 30958744 ps
CPU time 0.82 seconds
Started Mar 10 03:28:38 PM PDT 24
Finished Mar 10 03:28:39 PM PDT 24
Peak memory 195408 kb
Host smart-bcb3707c-47af-4eb4-8085-eaf6409800e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13771574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.13771574
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3148488364
Short name T563
Test name
Test status
Simulation time 674318568 ps
CPU time 25.72 seconds
Started Mar 10 03:28:37 PM PDT 24
Finished Mar 10 03:29:03 PM PDT 24
Peak memory 196896 kb
Host smart-e697a8cc-1220-4770-a39d-28f27efc897d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148488364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3148488364
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.30137522
Short name T327
Test name
Test status
Simulation time 356608911 ps
CPU time 1.14 seconds
Started Mar 10 03:28:41 PM PDT 24
Finished Mar 10 03:28:42 PM PDT 24
Peak memory 198096 kb
Host smart-9a6e382f-0059-4408-a24b-7ace91caa3ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30137522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.30137522
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.859359244
Short name T451
Test name
Test status
Simulation time 171396749 ps
CPU time 1.32 seconds
Started Mar 10 03:28:39 PM PDT 24
Finished Mar 10 03:28:40 PM PDT 24
Peak memory 196216 kb
Host smart-662f2c3d-8593-4b92-a1ea-d012a2d39fba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859359244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.859359244
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.1282438654
Short name T446
Test name
Test status
Simulation time 60559375 ps
CPU time 2.8 seconds
Started Mar 10 03:28:38 PM PDT 24
Finished Mar 10 03:28:40 PM PDT 24
Peak memory 198192 kb
Host smart-e1e96e6e-9308-4f6b-ac61-bd175f9ced2e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282438654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.1282438654
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.2515037335
Short name T117
Test name
Test status
Simulation time 380424739 ps
CPU time 2.99 seconds
Started Mar 10 03:28:38 PM PDT 24
Finished Mar 10 03:28:41 PM PDT 24
Peak memory 197204 kb
Host smart-84759306-9f66-48ee-9e1d-e49350ee888c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515037335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.2515037335
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.508489954
Short name T283
Test name
Test status
Simulation time 25731845 ps
CPU time 0.91 seconds
Started Mar 10 03:28:36 PM PDT 24
Finished Mar 10 03:28:37 PM PDT 24
Peak memory 196280 kb
Host smart-1d959f00-7c9f-4348-ba22-efbbe3054502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508489954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.508489954
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.626743353
Short name T544
Test name
Test status
Simulation time 59545125 ps
CPU time 1.53 seconds
Started Mar 10 03:28:35 PM PDT 24
Finished Mar 10 03:28:37 PM PDT 24
Peak memory 198280 kb
Host smart-0c936781-d478-42a9-9ee4-3c6367691ed1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626743353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.626743353
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1573697361
Short name T391
Test name
Test status
Simulation time 848689655 ps
CPU time 5.64 seconds
Started Mar 10 03:28:41 PM PDT 24
Finished Mar 10 03:28:47 PM PDT 24
Peak memory 198160 kb
Host smart-467d9b1d-51b2-4318-b4b1-5b4a10b88091
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573697361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1573697361
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.261821856
Short name T162
Test name
Test status
Simulation time 66750284 ps
CPU time 1.06 seconds
Started Mar 10 03:28:31 PM PDT 24
Finished Mar 10 03:28:33 PM PDT 24
Peak memory 195748 kb
Host smart-c8dc3eba-11a0-408c-9d42-0f2bba43e9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261821856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.261821856
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.1441488893
Short name T482
Test name
Test status
Simulation time 39745014 ps
CPU time 1.28 seconds
Started Mar 10 03:28:34 PM PDT 24
Finished Mar 10 03:28:35 PM PDT 24
Peak memory 196672 kb
Host smart-4d444602-611a-4377-9965-05f766dbb304
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441488893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.1441488893
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3863919733
Short name T164
Test name
Test status
Simulation time 110533631320 ps
CPU time 196.81 seconds
Started Mar 10 03:28:51 PM PDT 24
Finished Mar 10 03:32:08 PM PDT 24
Peak memory 198268 kb
Host smart-3f6142a0-3e8d-466c-9480-298bf7d51622
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863919733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3863919733
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.622304271
Short name T474
Test name
Test status
Simulation time 31298907 ps
CPU time 0.62 seconds
Started Mar 10 03:28:49 PM PDT 24
Finished Mar 10 03:28:50 PM PDT 24
Peak memory 194124 kb
Host smart-6ed2b767-d574-4a97-bf6b-7fbc80980e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622304271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.622304271
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3968773442
Short name T383
Test name
Test status
Simulation time 23978812 ps
CPU time 0.88 seconds
Started Mar 10 03:28:46 PM PDT 24
Finished Mar 10 03:28:47 PM PDT 24
Peak memory 195236 kb
Host smart-0de5dfe8-c277-4815-8222-295c891c08d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968773442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3968773442
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.153664201
Short name T333
Test name
Test status
Simulation time 151100666 ps
CPU time 5.16 seconds
Started Mar 10 03:28:44 PM PDT 24
Finished Mar 10 03:28:49 PM PDT 24
Peak memory 196932 kb
Host smart-58ae7247-4d97-42ac-9fe1-a9d46c97b12f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153664201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.153664201
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.4261014430
Short name T464
Test name
Test status
Simulation time 102405974 ps
CPU time 1.01 seconds
Started Mar 10 03:28:43 PM PDT 24
Finished Mar 10 03:28:44 PM PDT 24
Peak memory 196152 kb
Host smart-d0df2f8e-e6a2-45ee-9cf0-ba96c8e871d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261014430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.4261014430
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1764706657
Short name T652
Test name
Test status
Simulation time 31211682 ps
CPU time 0.82 seconds
Started Mar 10 03:28:42 PM PDT 24
Finished Mar 10 03:28:43 PM PDT 24
Peak memory 195564 kb
Host smart-2d9f8b41-ae85-4e25-b15d-53e5f1f7a758
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764706657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1764706657
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.1314445983
Short name T128
Test name
Test status
Simulation time 41361964 ps
CPU time 1.78 seconds
Started Mar 10 03:28:45 PM PDT 24
Finished Mar 10 03:28:47 PM PDT 24
Peak memory 197008 kb
Host smart-96502145-11de-4942-970e-ab97b3dadcdf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314445983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.1314445983
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.933051375
Short name T522
Test name
Test status
Simulation time 113676649 ps
CPU time 1 seconds
Started Mar 10 03:28:42 PM PDT 24
Finished Mar 10 03:28:44 PM PDT 24
Peak memory 195816 kb
Host smart-8a8883cb-cc17-4444-ae00-1e408e257edc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933051375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
933051375
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1046888238
Short name T324
Test name
Test status
Simulation time 47937113 ps
CPU time 1.24 seconds
Started Mar 10 03:28:44 PM PDT 24
Finished Mar 10 03:28:45 PM PDT 24
Peak memory 196680 kb
Host smart-043893b0-115d-4962-9e72-78d0cfe98140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046888238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1046888238
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.862192729
Short name T179
Test name
Test status
Simulation time 32948424 ps
CPU time 1 seconds
Started Mar 10 03:28:46 PM PDT 24
Finished Mar 10 03:28:47 PM PDT 24
Peak memory 197424 kb
Host smart-b635ece4-207b-45b4-976a-897bafca3928
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862192729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.862192729
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1925968066
Short name T406
Test name
Test status
Simulation time 98900459 ps
CPU time 4.92 seconds
Started Mar 10 03:28:45 PM PDT 24
Finished Mar 10 03:28:50 PM PDT 24
Peak memory 198124 kb
Host smart-ed4ffdc5-7948-4887-af17-8031ec7d1e39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925968066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1925968066
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3469419322
Short name T64
Test name
Test status
Simulation time 58315882 ps
CPU time 0.99 seconds
Started Mar 10 03:28:38 PM PDT 24
Finished Mar 10 03:28:39 PM PDT 24
Peak memory 195972 kb
Host smart-b63b3189-4410-482a-887d-7f657a20c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469419322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3469419322
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.3264654021
Short name T291
Test name
Test status
Simulation time 1271859716 ps
CPU time 1.3 seconds
Started Mar 10 03:28:43 PM PDT 24
Finished Mar 10 03:28:45 PM PDT 24
Peak memory 197008 kb
Host smart-94768909-fc56-40d1-b126-a27c2303e3a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264654021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.3264654021
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.4099785455
Short name T460
Test name
Test status
Simulation time 24101752468 ps
CPU time 173.23 seconds
Started Mar 10 03:28:44 PM PDT 24
Finished Mar 10 03:31:37 PM PDT 24
Peak memory 198412 kb
Host smart-2bef4e66-8d3c-4ece-bcee-2462e49b2b41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099785455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.4099785455
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2371408756
Short name T638
Test name
Test status
Simulation time 57222100 ps
CPU time 0.58 seconds
Started Mar 10 03:28:52 PM PDT 24
Finished Mar 10 03:28:53 PM PDT 24
Peak memory 194032 kb
Host smart-5bb39899-eef6-4bf6-ab13-bdfae3e85ad1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371408756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2371408756
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1409723599
Short name T500
Test name
Test status
Simulation time 40735394 ps
CPU time 0.87 seconds
Started Mar 10 03:28:50 PM PDT 24
Finished Mar 10 03:28:51 PM PDT 24
Peak memory 195492 kb
Host smart-6cb49f72-2245-4f6a-85ad-7d2ff0a5f291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409723599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1409723599
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.674781107
Short name T604
Test name
Test status
Simulation time 3077162723 ps
CPU time 20.49 seconds
Started Mar 10 03:28:55 PM PDT 24
Finished Mar 10 03:29:15 PM PDT 24
Peak memory 197636 kb
Host smart-ac29a84c-72b0-47bc-8888-51c32547d98f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674781107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.674781107
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.477519734
Short name T242
Test name
Test status
Simulation time 204055953 ps
CPU time 1 seconds
Started Mar 10 03:28:53 PM PDT 24
Finished Mar 10 03:28:54 PM PDT 24
Peak memory 197084 kb
Host smart-f240cc84-bd38-4801-8aba-76c430e19489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477519734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.477519734
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2821140272
Short name T700
Test name
Test status
Simulation time 45562695 ps
CPU time 1.35 seconds
Started Mar 10 03:28:53 PM PDT 24
Finished Mar 10 03:28:54 PM PDT 24
Peak memory 196844 kb
Host smart-4309e08d-d416-4e8b-98ac-31dd281da073
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821140272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2821140272
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3156191144
Short name T267
Test name
Test status
Simulation time 48446268 ps
CPU time 1.24 seconds
Started Mar 10 03:28:53 PM PDT 24
Finished Mar 10 03:28:55 PM PDT 24
Peak memory 197928 kb
Host smart-c0310bf1-a014-48e0-9a7d-c0efc94f90ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156191144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3156191144
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2409413583
Short name T479
Test name
Test status
Simulation time 119523173 ps
CPU time 1.32 seconds
Started Mar 10 03:28:57 PM PDT 24
Finished Mar 10 03:28:59 PM PDT 24
Peak memory 195828 kb
Host smart-a6888267-d6e2-44fd-821a-d2fc3298b1a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409413583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2409413583
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.1952987228
Short name T692
Test name
Test status
Simulation time 665683654 ps
CPU time 1.47 seconds
Started Mar 10 03:28:48 PM PDT 24
Finished Mar 10 03:28:50 PM PDT 24
Peak memory 197192 kb
Host smart-556a11e9-fdb3-4956-8d65-8e7b43b4de38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952987228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.1952987228
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1716203719
Short name T168
Test name
Test status
Simulation time 67342014 ps
CPU time 1.12 seconds
Started Mar 10 03:28:47 PM PDT 24
Finished Mar 10 03:28:48 PM PDT 24
Peak memory 196808 kb
Host smart-e7140c13-d3c1-4fd8-8f90-e4f08bb00c38
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716203719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1716203719
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1351241381
Short name T215
Test name
Test status
Simulation time 849280954 ps
CPU time 3.91 seconds
Started Mar 10 03:28:55 PM PDT 24
Finished Mar 10 03:28:59 PM PDT 24
Peak memory 198108 kb
Host smart-d70d6323-effa-4be9-8a5d-879b768ed5ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351241381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1351241381
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.1415970629
Short name T703
Test name
Test status
Simulation time 28845267 ps
CPU time 0.89 seconds
Started Mar 10 03:28:48 PM PDT 24
Finished Mar 10 03:28:50 PM PDT 24
Peak memory 195356 kb
Host smart-c38c9056-8e03-47b0-885b-763685b178d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415970629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.1415970629
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3605850396
Short name T170
Test name
Test status
Simulation time 98335093 ps
CPU time 1.33 seconds
Started Mar 10 03:28:47 PM PDT 24
Finished Mar 10 03:28:49 PM PDT 24
Peak memory 195656 kb
Host smart-0d8e3038-37ec-46fe-9443-4a8efd3aa4b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605850396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3605850396
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3350743279
Short name T620
Test name
Test status
Simulation time 4803298200 ps
CPU time 76.67 seconds
Started Mar 10 03:28:53 PM PDT 24
Finished Mar 10 03:30:10 PM PDT 24
Peak memory 198360 kb
Host smart-49c2b899-2469-4fe8-b3be-003dd8045a21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350743279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3350743279
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.2953276305
Short name T55
Test name
Test status
Simulation time 13683862237 ps
CPU time 467.75 seconds
Started Mar 10 03:28:56 PM PDT 24
Finished Mar 10 03:36:44 PM PDT 24
Peak memory 198492 kb
Host smart-fc234b69-e6e0-4576-8dd9-9d59f4d6e657
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2953276305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.2953276305
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1940224117
Short name T33
Test name
Test status
Simulation time 24989541 ps
CPU time 0.61 seconds
Started Mar 10 03:28:58 PM PDT 24
Finished Mar 10 03:28:59 PM PDT 24
Peak memory 194964 kb
Host smart-d43b2289-349f-4203-bc13-4d75a7eb2c5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940224117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1940224117
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.730438469
Short name T225
Test name
Test status
Simulation time 22877033 ps
CPU time 0.87 seconds
Started Mar 10 03:28:54 PM PDT 24
Finished Mar 10 03:28:55 PM PDT 24
Peak memory 196204 kb
Host smart-3879f754-7aac-4075-8628-b62fccd4a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730438469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.730438469
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.3170272553
Short name T281
Test name
Test status
Simulation time 6639980596 ps
CPU time 12.29 seconds
Started Mar 10 03:28:57 PM PDT 24
Finished Mar 10 03:29:09 PM PDT 24
Peak memory 196908 kb
Host smart-17320a1c-8e58-4f14-bddc-0e9a1bfeeef5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170272553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.3170272553
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.2682956868
Short name T667
Test name
Test status
Simulation time 98466311 ps
CPU time 1.14 seconds
Started Mar 10 03:28:55 PM PDT 24
Finished Mar 10 03:28:56 PM PDT 24
Peak memory 196804 kb
Host smart-7fc7aaf0-3753-415a-8fdc-90feb2c8fe8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682956868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.2682956868
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3243717012
Short name T271
Test name
Test status
Simulation time 78530600 ps
CPU time 1.33 seconds
Started Mar 10 03:29:02 PM PDT 24
Finished Mar 10 03:29:04 PM PDT 24
Peak memory 197208 kb
Host smart-2fc35b07-21cf-45d6-bc7f-02ecd4821776
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243717012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3243717012
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.272092001
Short name T611
Test name
Test status
Simulation time 46901241 ps
CPU time 2.12 seconds
Started Mar 10 03:28:56 PM PDT 24
Finished Mar 10 03:28:58 PM PDT 24
Peak memory 198176 kb
Host smart-d9363094-8f29-4e89-a487-3e4a3c957fd4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272092001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.272092001
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1813607339
Short name T50
Test name
Test status
Simulation time 56839315 ps
CPU time 1.26 seconds
Started Mar 10 03:29:02 PM PDT 24
Finished Mar 10 03:29:04 PM PDT 24
Peak memory 197356 kb
Host smart-74663c11-891b-4a80-a28b-ec67bb2cae17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813607339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1813607339
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.4205903162
Short name T457
Test name
Test status
Simulation time 42433667 ps
CPU time 1.14 seconds
Started Mar 10 03:28:55 PM PDT 24
Finished Mar 10 03:28:56 PM PDT 24
Peak memory 196616 kb
Host smart-cbeb9ece-bf28-480e-b2bc-12a97c3e117f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205903162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.4205903162
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3626129091
Short name T199
Test name
Test status
Simulation time 190510689 ps
CPU time 1.13 seconds
Started Mar 10 03:28:56 PM PDT 24
Finished Mar 10 03:28:57 PM PDT 24
Peak memory 196260 kb
Host smart-4c3b383a-c04c-40f3-a2c3-e16b558b2cc9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626129091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3626129091
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2544894334
Short name T309
Test name
Test status
Simulation time 344537245 ps
CPU time 4.48 seconds
Started Mar 10 03:29:02 PM PDT 24
Finished Mar 10 03:29:07 PM PDT 24
Peak memory 198148 kb
Host smart-36888e6a-470d-42ce-91d5-a99922243e93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544894334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2544894334
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.961905326
Short name T697
Test name
Test status
Simulation time 139679780 ps
CPU time 1.53 seconds
Started Mar 10 03:28:52 PM PDT 24
Finished Mar 10 03:28:54 PM PDT 24
Peak memory 196972 kb
Host smart-66024541-3afe-4b8b-aa29-0f058af949a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961905326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.961905326
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2293543152
Short name T556
Test name
Test status
Simulation time 88168764 ps
CPU time 1.45 seconds
Started Mar 10 03:28:56 PM PDT 24
Finished Mar 10 03:28:58 PM PDT 24
Peak memory 197080 kb
Host smart-e622046f-7805-47b2-9227-db55297d8d15
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293543152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2293543152
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.2594879702
Short name T719
Test name
Test status
Simulation time 12587063241 ps
CPU time 86.7 seconds
Started Mar 10 03:28:56 PM PDT 24
Finished Mar 10 03:30:23 PM PDT 24
Peak memory 198408 kb
Host smart-897c3f53-1628-4b9a-8acf-b408bd83ed29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594879702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.2594879702
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.3938843251
Short name T502
Test name
Test status
Simulation time 45865069968 ps
CPU time 367.11 seconds
Started Mar 10 03:28:57 PM PDT 24
Finished Mar 10 03:35:04 PM PDT 24
Peak memory 198528 kb
Host smart-d27ee146-6dd6-4d0b-b281-cc42fc068dfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3938843251 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.3938843251
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3208891538
Short name T296
Test name
Test status
Simulation time 25980285 ps
CPU time 0.65 seconds
Started Mar 10 03:29:01 PM PDT 24
Finished Mar 10 03:29:01 PM PDT 24
Peak memory 195036 kb
Host smart-35c63353-7697-4ae2-bedf-847bd6e0f269
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208891538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3208891538
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.1411942340
Short name T668
Test name
Test status
Simulation time 46646259 ps
CPU time 0.72 seconds
Started Mar 10 03:29:02 PM PDT 24
Finished Mar 10 03:29:03 PM PDT 24
Peak memory 196136 kb
Host smart-d91123d8-4945-438f-b87c-1887f22efe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411942340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.1411942340
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.761704601
Short name T602
Test name
Test status
Simulation time 537239890 ps
CPU time 30.14 seconds
Started Mar 10 03:29:02 PM PDT 24
Finished Mar 10 03:29:32 PM PDT 24
Peak memory 196784 kb
Host smart-a14a8bed-fabf-432f-aaca-573762a6417c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761704601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.761704601
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1722206223
Short name T441
Test name
Test status
Simulation time 46306638 ps
CPU time 0.9 seconds
Started Mar 10 03:29:02 PM PDT 24
Finished Mar 10 03:29:03 PM PDT 24
Peak memory 196164 kb
Host smart-4b15167d-a08d-42e8-a149-e45a25b3743a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722206223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1722206223
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.837580605
Short name T549
Test name
Test status
Simulation time 77762164 ps
CPU time 1.38 seconds
Started Mar 10 03:29:01 PM PDT 24
Finished Mar 10 03:29:03 PM PDT 24
Peak memory 196308 kb
Host smart-e190e9bf-4c40-482c-ae8c-567ddce8a6ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837580605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.837580605
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2951869841
Short name T236
Test name
Test status
Simulation time 53122945 ps
CPU time 2.25 seconds
Started Mar 10 03:29:01 PM PDT 24
Finished Mar 10 03:29:03 PM PDT 24
Peak memory 198172 kb
Host smart-a6886c24-9af8-4a80-bca5-e90da50c4c03
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951869841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2951869841
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3536036006
Short name T573
Test name
Test status
Simulation time 119529713 ps
CPU time 2.97 seconds
Started Mar 10 03:29:03 PM PDT 24
Finished Mar 10 03:29:06 PM PDT 24
Peak memory 197284 kb
Host smart-f139f478-30c1-480b-a3e2-5d800429c6bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536036006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3536036006
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.4111418905
Short name T263
Test name
Test status
Simulation time 111336709 ps
CPU time 0.97 seconds
Started Mar 10 03:28:56 PM PDT 24
Finished Mar 10 03:28:57 PM PDT 24
Peak memory 196068 kb
Host smart-afd81433-41b9-46a4-80b1-6f3bf66042b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111418905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.4111418905
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2592076179
Short name T648
Test name
Test status
Simulation time 119178003 ps
CPU time 1.14 seconds
Started Mar 10 03:28:57 PM PDT 24
Finished Mar 10 03:28:59 PM PDT 24
Peak memory 196888 kb
Host smart-ce495ad4-6bde-4ed5-873d-259a9a423d6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592076179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2592076179
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.2364725648
Short name T596
Test name
Test status
Simulation time 2214842033 ps
CPU time 6.93 seconds
Started Mar 10 03:28:59 PM PDT 24
Finished Mar 10 03:29:06 PM PDT 24
Peak memory 198268 kb
Host smart-a7a4c5a9-d07b-4a59-b55e-3dd867de2bb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364725648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.2364725648
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.2352544067
Short name T295
Test name
Test status
Simulation time 37356600 ps
CPU time 0.98 seconds
Started Mar 10 03:29:03 PM PDT 24
Finished Mar 10 03:29:04 PM PDT 24
Peak memory 195976 kb
Host smart-7b68a6c2-a396-4e69-9dda-84aec2a842c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352544067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.2352544067
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.2873321104
Short name T325
Test name
Test status
Simulation time 35049567 ps
CPU time 0.95 seconds
Started Mar 10 03:29:02 PM PDT 24
Finished Mar 10 03:29:03 PM PDT 24
Peak memory 195908 kb
Host smart-42c0b50c-d02e-43ed-9cbb-2d61aea87e6f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873321104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.2873321104
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1829097034
Short name T465
Test name
Test status
Simulation time 8123616714 ps
CPU time 129.44 seconds
Started Mar 10 03:29:09 PM PDT 24
Finished Mar 10 03:31:19 PM PDT 24
Peak memory 198264 kb
Host smart-19b69f64-6cd3-45b8-8b1a-d0073efbee27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829097034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1829097034
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3464396465
Short name T689
Test name
Test status
Simulation time 48561931 ps
CPU time 0.64 seconds
Started Mar 10 03:29:12 PM PDT 24
Finished Mar 10 03:29:13 PM PDT 24
Peak memory 194332 kb
Host smart-0fad11b1-8a75-4fdf-b5ae-86e4d26bf6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464396465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3464396465
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1488593008
Short name T293
Test name
Test status
Simulation time 69646288 ps
CPU time 0.85 seconds
Started Mar 10 03:29:09 PM PDT 24
Finished Mar 10 03:29:09 PM PDT 24
Peak memory 195372 kb
Host smart-88cfca0d-384a-462d-bee1-b5517d515c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488593008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1488593008
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.154753692
Short name T548
Test name
Test status
Simulation time 4040422443 ps
CPU time 27.52 seconds
Started Mar 10 03:29:06 PM PDT 24
Finished Mar 10 03:29:34 PM PDT 24
Peak memory 196884 kb
Host smart-df52abd8-1d02-43fd-8769-a20692271fee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154753692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.154753692
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2371033151
Short name T119
Test name
Test status
Simulation time 140657552 ps
CPU time 1.25 seconds
Started Mar 10 03:29:10 PM PDT 24
Finished Mar 10 03:29:11 PM PDT 24
Peak memory 196812 kb
Host smart-4079c59f-4a9f-410e-8325-19e921b6e295
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371033151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2371033151
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.4195042542
Short name T452
Test name
Test status
Simulation time 65200794 ps
CPU time 0.7 seconds
Started Mar 10 03:29:08 PM PDT 24
Finished Mar 10 03:29:08 PM PDT 24
Peak memory 194468 kb
Host smart-6041ddd0-68d1-48c1-a082-8b14300fad96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195042542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.4195042542
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2836656324
Short name T282
Test name
Test status
Simulation time 35927030 ps
CPU time 0.95 seconds
Started Mar 10 03:29:04 PM PDT 24
Finished Mar 10 03:29:05 PM PDT 24
Peak memory 196976 kb
Host smart-cf00f281-1332-4c84-9d23-e8bde3491eae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836656324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2836656324
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1139194482
Short name T477
Test name
Test status
Simulation time 122704972 ps
CPU time 3.81 seconds
Started Mar 10 03:29:05 PM PDT 24
Finished Mar 10 03:29:08 PM PDT 24
Peak memory 197188 kb
Host smart-b7350491-8c25-44d6-ad01-e496b2316942
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139194482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1139194482
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2616101723
Short name T262
Test name
Test status
Simulation time 168328190 ps
CPU time 1.41 seconds
Started Mar 10 03:29:04 PM PDT 24
Finished Mar 10 03:29:05 PM PDT 24
Peak memory 195956 kb
Host smart-42617ca9-21cf-4cac-9253-bd4afe30de4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616101723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2616101723
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.3032797269
Short name T185
Test name
Test status
Simulation time 51031262 ps
CPU time 1.17 seconds
Started Mar 10 03:29:05 PM PDT 24
Finished Mar 10 03:29:06 PM PDT 24
Peak memory 196724 kb
Host smart-22d3485e-2c38-4690-bd26-a7dfcb16785a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032797269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.3032797269
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.3772563099
Short name T402
Test name
Test status
Simulation time 756637980 ps
CPU time 3.37 seconds
Started Mar 10 03:29:06 PM PDT 24
Finished Mar 10 03:29:10 PM PDT 24
Peak memory 198140 kb
Host smart-9a185e03-8e52-49dd-95f2-fd10e1bfad1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772563099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.3772563099
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.885207943
Short name T171
Test name
Test status
Simulation time 717397121 ps
CPU time 1.28 seconds
Started Mar 10 03:29:11 PM PDT 24
Finished Mar 10 03:29:13 PM PDT 24
Peak memory 195968 kb
Host smart-5a53c6b0-0b69-4a36-a3ba-d66ab5c29dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885207943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.885207943
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.4103243217
Short name T396
Test name
Test status
Simulation time 208622623 ps
CPU time 0.86 seconds
Started Mar 10 03:29:06 PM PDT 24
Finished Mar 10 03:29:07 PM PDT 24
Peak memory 195304 kb
Host smart-09f04512-fec0-4b73-bd06-c926fb8cb7a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103243217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.4103243217
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2245273697
Short name T680
Test name
Test status
Simulation time 2066748682 ps
CPU time 29.79 seconds
Started Mar 10 03:29:09 PM PDT 24
Finished Mar 10 03:29:39 PM PDT 24
Peak memory 198068 kb
Host smart-65648865-538c-4ff9-bf4f-da2d6c277f2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245273697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2245273697
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1771422767
Short name T423
Test name
Test status
Simulation time 42708514412 ps
CPU time 937.04 seconds
Started Mar 10 03:29:10 PM PDT 24
Finished Mar 10 03:44:47 PM PDT 24
Peak memory 198532 kb
Host smart-a8e75367-2e95-4eeb-99b6-2160b1a8d6ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1771422767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.1771422767
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.1640204473
Short name T640
Test name
Test status
Simulation time 21793732 ps
CPU time 0.58 seconds
Started Mar 10 03:25:36 PM PDT 24
Finished Mar 10 03:25:37 PM PDT 24
Peak memory 195064 kb
Host smart-8572e995-c26a-4a6b-b50f-e3b02fc0eb72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640204473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.1640204473
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3244514510
Short name T395
Test name
Test status
Simulation time 40606164 ps
CPU time 0.96 seconds
Started Mar 10 03:25:11 PM PDT 24
Finished Mar 10 03:25:12 PM PDT 24
Peak memory 197140 kb
Host smart-c56644d5-b904-4f38-bc73-fe9ca8d6c355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244514510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3244514510
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1214139409
Short name T646
Test name
Test status
Simulation time 239501896 ps
CPU time 13.04 seconds
Started Mar 10 03:25:22 PM PDT 24
Finished Mar 10 03:25:35 PM PDT 24
Peak memory 197316 kb
Host smart-97754982-2ea5-401a-92fb-859d47c54e60
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214139409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1214139409
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.494350172
Short name T440
Test name
Test status
Simulation time 296797596 ps
CPU time 0.65 seconds
Started Mar 10 03:25:18 PM PDT 24
Finished Mar 10 03:25:19 PM PDT 24
Peak memory 194588 kb
Host smart-cad78799-1845-49ee-a430-de35e1ac7a97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494350172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.494350172
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.242172647
Short name T552
Test name
Test status
Simulation time 71779492 ps
CPU time 1.2 seconds
Started Mar 10 03:25:09 PM PDT 24
Finished Mar 10 03:25:10 PM PDT 24
Peak memory 195976 kb
Host smart-1b0caec9-9e6a-4634-9641-71d73d1f7f2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242172647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.242172647
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1555817968
Short name T442
Test name
Test status
Simulation time 119294562 ps
CPU time 2.98 seconds
Started Mar 10 03:25:39 PM PDT 24
Finished Mar 10 03:25:43 PM PDT 24
Peak memory 198292 kb
Host smart-539e86a2-cf3d-4921-b35a-438bfdc7b0c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555817968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1555817968
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2301076531
Short name T231
Test name
Test status
Simulation time 115110209 ps
CPU time 2.64 seconds
Started Mar 10 03:25:09 PM PDT 24
Finished Mar 10 03:25:12 PM PDT 24
Peak memory 197192 kb
Host smart-ffb920be-b447-408f-a31d-e63998c1edfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301076531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2301076531
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.1010765927
Short name T268
Test name
Test status
Simulation time 42782137 ps
CPU time 1.26 seconds
Started Mar 10 03:25:11 PM PDT 24
Finished Mar 10 03:25:12 PM PDT 24
Peak memory 196144 kb
Host smart-fecffbd3-3c69-4df6-b4b6-1b8befe2f176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010765927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.1010765927
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1145526600
Short name T304
Test name
Test status
Simulation time 137641580 ps
CPU time 0.93 seconds
Started Mar 10 03:25:05 PM PDT 24
Finished Mar 10 03:25:06 PM PDT 24
Peak memory 196540 kb
Host smart-486f7db3-b298-4c4a-9b78-f5a096e4ff6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145526600 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1145526600
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.2373171541
Short name T329
Test name
Test status
Simulation time 293691465 ps
CPU time 3.66 seconds
Started Mar 10 03:25:17 PM PDT 24
Finished Mar 10 03:25:21 PM PDT 24
Peak memory 198140 kb
Host smart-5366bfb9-b27a-43d3-a73d-f62299862784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373171541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.2373171541
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.3806745632
Short name T430
Test name
Test status
Simulation time 219163252 ps
CPU time 1.11 seconds
Started Mar 10 03:25:03 PM PDT 24
Finished Mar 10 03:25:04 PM PDT 24
Peak memory 195720 kb
Host smart-4c1338cd-1896-4c05-9e08-921b29f33d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806745632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3806745632
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3741287415
Short name T618
Test name
Test status
Simulation time 43207100 ps
CPU time 1.11 seconds
Started Mar 10 03:25:11 PM PDT 24
Finished Mar 10 03:25:12 PM PDT 24
Peak memory 196636 kb
Host smart-dc1c4fbe-d38e-4df0-add8-49dc5106f54f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741287415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3741287415
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.981325417
Short name T592
Test name
Test status
Simulation time 36579087909 ps
CPU time 237.53 seconds
Started Mar 10 03:25:17 PM PDT 24
Finished Mar 10 03:29:14 PM PDT 24
Peak memory 198316 kb
Host smart-ef15e55c-694c-48f8-a87b-84e909158bec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981325417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gp
io_stress_all.981325417
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1419093336
Short name T532
Test name
Test status
Simulation time 18281196 ps
CPU time 0.61 seconds
Started Mar 10 03:29:17 PM PDT 24
Finished Mar 10 03:29:18 PM PDT 24
Peak memory 194104 kb
Host smart-91b8acb8-b9bb-4b81-ba82-d63f6d1f3e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419093336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1419093336
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.743333598
Short name T459
Test name
Test status
Simulation time 61131059 ps
CPU time 0.92 seconds
Started Mar 10 03:29:11 PM PDT 24
Finished Mar 10 03:29:12 PM PDT 24
Peak memory 195292 kb
Host smart-ff435a12-649e-4400-aea4-4a8b93bc721a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743333598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.743333598
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2243325788
Short name T534
Test name
Test status
Simulation time 1931719115 ps
CPU time 14.54 seconds
Started Mar 10 03:29:16 PM PDT 24
Finished Mar 10 03:29:31 PM PDT 24
Peak memory 196952 kb
Host smart-d90748ec-48bf-44ac-bb72-1f42ae1b165d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243325788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2243325788
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.348350311
Short name T546
Test name
Test status
Simulation time 181239710 ps
CPU time 0.84 seconds
Started Mar 10 03:29:13 PM PDT 24
Finished Mar 10 03:29:14 PM PDT 24
Peak memory 195908 kb
Host smart-8213441d-bce5-4857-a719-01820dc21d27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348350311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.348350311
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3312128847
Short name T415
Test name
Test status
Simulation time 57838201 ps
CPU time 1.15 seconds
Started Mar 10 03:29:11 PM PDT 24
Finished Mar 10 03:29:12 PM PDT 24
Peak memory 196188 kb
Host smart-d9fa6efe-0a08-48cb-a503-41993d9b0530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312128847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3312128847
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2169952739
Short name T245
Test name
Test status
Simulation time 48744531 ps
CPU time 2.29 seconds
Started Mar 10 03:29:16 PM PDT 24
Finished Mar 10 03:29:18 PM PDT 24
Peak memory 198252 kb
Host smart-f9549243-8d58-4c3f-b20b-e7a7965ce99b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169952739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2169952739
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.3041903935
Short name T158
Test name
Test status
Simulation time 137896364 ps
CPU time 1.4 seconds
Started Mar 10 03:29:10 PM PDT 24
Finished Mar 10 03:29:12 PM PDT 24
Peak memory 196248 kb
Host smart-10a921ef-8f87-4cec-8978-ac044dfddc4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041903935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.3041903935
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2951199739
Short name T142
Test name
Test status
Simulation time 134663339 ps
CPU time 1.37 seconds
Started Mar 10 03:29:09 PM PDT 24
Finished Mar 10 03:29:10 PM PDT 24
Peak memory 197232 kb
Host smart-1b737e84-893c-41d5-be40-e21d441f3809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951199739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2951199739
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2161594166
Short name T278
Test name
Test status
Simulation time 32154273 ps
CPU time 1.14 seconds
Started Mar 10 03:29:11 PM PDT 24
Finished Mar 10 03:29:12 PM PDT 24
Peak memory 196156 kb
Host smart-c3ef2044-c55b-406d-af9a-5befc71588ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161594166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2161594166
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1399560720
Short name T232
Test name
Test status
Simulation time 210943991 ps
CPU time 3.89 seconds
Started Mar 10 03:29:15 PM PDT 24
Finished Mar 10 03:29:19 PM PDT 24
Peak memory 198164 kb
Host smart-8a462389-3feb-46b4-86e7-94ce831eeb99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399560720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1399560720
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1920206836
Short name T297
Test name
Test status
Simulation time 124171493 ps
CPU time 0.92 seconds
Started Mar 10 03:29:09 PM PDT 24
Finished Mar 10 03:29:09 PM PDT 24
Peak memory 196056 kb
Host smart-122405d6-dcb8-4ecc-b6eb-8688b48d0905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920206836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1920206836
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.3338553231
Short name T473
Test name
Test status
Simulation time 28548684 ps
CPU time 0.84 seconds
Started Mar 10 03:29:09 PM PDT 24
Finished Mar 10 03:29:10 PM PDT 24
Peak memory 196028 kb
Host smart-a17d73ad-6e93-492f-9c7d-39f1a5ea33ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338553231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.3338553231
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1297488938
Short name T662
Test name
Test status
Simulation time 18342023411 ps
CPU time 78.27 seconds
Started Mar 10 03:29:17 PM PDT 24
Finished Mar 10 03:30:35 PM PDT 24
Peak memory 198376 kb
Host smart-b1573b6d-3111-46d0-a723-3057ab05a88f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297488938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1297488938
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1457413760
Short name T97
Test name
Test status
Simulation time 39437553899 ps
CPU time 1167.51 seconds
Started Mar 10 03:29:16 PM PDT 24
Finished Mar 10 03:48:43 PM PDT 24
Peak memory 198468 kb
Host smart-398b6467-0ea5-4449-80d9-997a766dcba0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1457413760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1457413760
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1546662752
Short name T183
Test name
Test status
Simulation time 15814701 ps
CPU time 0.63 seconds
Started Mar 10 03:29:32 PM PDT 24
Finished Mar 10 03:29:34 PM PDT 24
Peak memory 194324 kb
Host smart-50c0b7a2-f937-4c74-928c-50c53f51daef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546662752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1546662752
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2312678988
Short name T58
Test name
Test status
Simulation time 15948811 ps
CPU time 0.71 seconds
Started Mar 10 03:29:20 PM PDT 24
Finished Mar 10 03:29:21 PM PDT 24
Peak memory 194856 kb
Host smart-23532d89-5615-4f13-ba63-a91a526ab445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312678988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2312678988
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.1275952654
Short name T491
Test name
Test status
Simulation time 125634237 ps
CPU time 6.21 seconds
Started Mar 10 03:29:21 PM PDT 24
Finished Mar 10 03:29:27 PM PDT 24
Peak memory 196460 kb
Host smart-bb731dd0-4d17-45f7-94d3-7e40d73e563e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275952654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.1275952654
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.438563303
Short name T523
Test name
Test status
Simulation time 46773008 ps
CPU time 0.74 seconds
Started Mar 10 03:29:32 PM PDT 24
Finished Mar 10 03:29:33 PM PDT 24
Peak memory 194884 kb
Host smart-3d0046fa-f43c-412f-8a52-7670904483e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438563303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.438563303
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2096120211
Short name T577
Test name
Test status
Simulation time 726665910 ps
CPU time 1.69 seconds
Started Mar 10 03:29:21 PM PDT 24
Finished Mar 10 03:29:23 PM PDT 24
Peak memory 198268 kb
Host smart-ee6590b8-dc32-4291-bf7e-e5c71f3a49df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096120211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2096120211
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2897419153
Short name T615
Test name
Test status
Simulation time 231500072 ps
CPU time 3.32 seconds
Started Mar 10 03:29:20 PM PDT 24
Finished Mar 10 03:29:23 PM PDT 24
Peak memory 198164 kb
Host smart-64e995b8-5f5d-494f-b038-e068df977987
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897419153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2897419153
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.2605722966
Short name T550
Test name
Test status
Simulation time 579816142 ps
CPU time 1.53 seconds
Started Mar 10 03:29:19 PM PDT 24
Finished Mar 10 03:29:20 PM PDT 24
Peak memory 196196 kb
Host smart-5ceebaa8-ed51-496c-9dd9-2f6f461ee204
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605722966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.2605722966
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.145021939
Short name T173
Test name
Test status
Simulation time 200177597 ps
CPU time 0.83 seconds
Started Mar 10 03:29:20 PM PDT 24
Finished Mar 10 03:29:21 PM PDT 24
Peak memory 195508 kb
Host smart-0892855d-3dc3-4a95-b9c3-20119d8d2297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145021939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.145021939
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3130270666
Short name T219
Test name
Test status
Simulation time 19459657 ps
CPU time 0.82 seconds
Started Mar 10 03:29:20 PM PDT 24
Finished Mar 10 03:29:21 PM PDT 24
Peak memory 195596 kb
Host smart-f2fa8ea7-f36f-4855-986e-2a5715e2f6b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130270666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3130270666
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.64579213
Short name T497
Test name
Test status
Simulation time 252554252 ps
CPU time 4.94 seconds
Started Mar 10 03:29:19 PM PDT 24
Finished Mar 10 03:29:24 PM PDT 24
Peak memory 198120 kb
Host smart-a781166d-885b-4b7e-8ab4-2fcd6d8868cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64579213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand
om_long_reg_writes_reg_reads.64579213
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2210418824
Short name T542
Test name
Test status
Simulation time 55667250 ps
CPU time 1.24 seconds
Started Mar 10 03:29:20 PM PDT 24
Finished Mar 10 03:29:21 PM PDT 24
Peak memory 196628 kb
Host smart-f3e6d63e-ed62-4663-8a32-aa5e96aabf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210418824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2210418824
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.699605425
Short name T412
Test name
Test status
Simulation time 83528711 ps
CPU time 0.9 seconds
Started Mar 10 03:29:14 PM PDT 24
Finished Mar 10 03:29:15 PM PDT 24
Peak memory 196584 kb
Host smart-d25db8d9-5f67-4d75-a70e-29011c40145e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699605425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.699605425
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3572507626
Short name T239
Test name
Test status
Simulation time 9438681045 ps
CPU time 134.82 seconds
Started Mar 10 03:29:27 PM PDT 24
Finished Mar 10 03:31:42 PM PDT 24
Peak memory 198388 kb
Host smart-4e9606e8-5a25-4552-9fe6-960b376625c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572507626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3572507626
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1648564321
Short name T53
Test name
Test status
Simulation time 90919906157 ps
CPU time 2014.12 seconds
Started Mar 10 03:29:22 PM PDT 24
Finished Mar 10 04:02:56 PM PDT 24
Peak memory 198516 kb
Host smart-d3184e69-f943-48cb-b5cb-ee3f70fc09a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1648564321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1648564321
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1707623454
Short name T693
Test name
Test status
Simulation time 15729838 ps
CPU time 0.61 seconds
Started Mar 10 03:29:30 PM PDT 24
Finished Mar 10 03:29:31 PM PDT 24
Peak memory 195072 kb
Host smart-0a5ec4a7-6c3c-496b-a99c-20bfaea6e012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707623454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1707623454
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1561920252
Short name T421
Test name
Test status
Simulation time 28376791 ps
CPU time 0.97 seconds
Started Mar 10 03:29:26 PM PDT 24
Finished Mar 10 03:29:27 PM PDT 24
Peak memory 196116 kb
Host smart-4a32797a-fa84-409f-b151-af1736b79a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561920252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1561920252
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.212850660
Short name T132
Test name
Test status
Simulation time 1931936950 ps
CPU time 28.04 seconds
Started Mar 10 03:29:25 PM PDT 24
Finished Mar 10 03:29:53 PM PDT 24
Peak memory 197296 kb
Host smart-be8e88bf-0c49-495d-b22f-e1b99ad8cf46
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212850660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.212850660
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.1411748146
Short name T20
Test name
Test status
Simulation time 84246907 ps
CPU time 1.09 seconds
Started Mar 10 03:29:30 PM PDT 24
Finished Mar 10 03:29:32 PM PDT 24
Peak memory 196828 kb
Host smart-69c97a1f-d08e-4424-9f52-da2fa79e2ac5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411748146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.1411748146
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3611056138
Short name T343
Test name
Test status
Simulation time 82438768 ps
CPU time 0.75 seconds
Started Mar 10 03:29:25 PM PDT 24
Finished Mar 10 03:29:26 PM PDT 24
Peak memory 194488 kb
Host smart-53be47cf-279a-4c6b-b791-6185b727bddc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611056138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3611056138
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.3207192578
Short name T305
Test name
Test status
Simulation time 85247164 ps
CPU time 3.45 seconds
Started Mar 10 03:29:25 PM PDT 24
Finished Mar 10 03:29:28 PM PDT 24
Peak memory 198196 kb
Host smart-2f9f8778-f4bc-4a36-83b8-51169397fced
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207192578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.3207192578
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.3977369854
Short name T524
Test name
Test status
Simulation time 103546793 ps
CPU time 3.19 seconds
Started Mar 10 03:29:23 PM PDT 24
Finished Mar 10 03:29:26 PM PDT 24
Peak memory 197220 kb
Host smart-121b0be7-09dd-4844-8a63-df2458f78e29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977369854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.3977369854
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2376336529
Short name T417
Test name
Test status
Simulation time 148335229 ps
CPU time 0.95 seconds
Started Mar 10 03:29:23 PM PDT 24
Finished Mar 10 03:29:24 PM PDT 24
Peak memory 196880 kb
Host smart-0a5e9e39-c0c9-469a-b6a5-57c1ca203070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376336529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2376336529
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.564434137
Short name T449
Test name
Test status
Simulation time 35428187 ps
CPU time 0.97 seconds
Started Mar 10 03:29:26 PM PDT 24
Finished Mar 10 03:29:27 PM PDT 24
Peak memory 197436 kb
Host smart-6fa1d185-37c1-407f-99fa-1504126d2539
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564434137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullup
_pulldown.564434137
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.581306078
Short name T289
Test name
Test status
Simulation time 98396761 ps
CPU time 5.26 seconds
Started Mar 10 03:29:27 PM PDT 24
Finished Mar 10 03:29:32 PM PDT 24
Peak memory 198168 kb
Host smart-1c166038-4779-40b5-b680-9ec82ecf87bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581306078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.581306078
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.4001479522
Short name T196
Test name
Test status
Simulation time 235170797 ps
CPU time 1.5 seconds
Started Mar 10 03:29:26 PM PDT 24
Finished Mar 10 03:29:28 PM PDT 24
Peak memory 196456 kb
Host smart-fd8a7ba6-fc31-4fd8-a178-5d118fb3c6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001479522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.4001479522
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3038322269
Short name T238
Test name
Test status
Simulation time 108007636 ps
CPU time 1.07 seconds
Started Mar 10 03:29:23 PM PDT 24
Finished Mar 10 03:29:24 PM PDT 24
Peak memory 195740 kb
Host smart-36f1d681-42a4-4658-8700-cb7381c13787
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038322269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3038322269
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3082069162
Short name T62
Test name
Test status
Simulation time 32300555529 ps
CPU time 96.74 seconds
Started Mar 10 03:29:28 PM PDT 24
Finished Mar 10 03:31:05 PM PDT 24
Peak memory 198336 kb
Host smart-8a2e7e17-ac1a-4235-90e3-81e4c9961142
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082069162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3082069162
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.1772947305
Short name T25
Test name
Test status
Simulation time 83237726508 ps
CPU time 1626.76 seconds
Started Mar 10 03:29:31 PM PDT 24
Finished Mar 10 03:56:39 PM PDT 24
Peak memory 198548 kb
Host smart-07af9dd3-d831-4886-90cf-cd5a4d75b532
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1772947305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.1772947305
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.254622923
Short name T320
Test name
Test status
Simulation time 53935055 ps
CPU time 0.61 seconds
Started Mar 10 03:29:33 PM PDT 24
Finished Mar 10 03:29:34 PM PDT 24
Peak memory 194964 kb
Host smart-f907c0d2-eaaa-4475-b3a5-612a88fc92c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254622923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.254622923
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3915558739
Short name T344
Test name
Test status
Simulation time 94092200 ps
CPU time 0.78 seconds
Started Mar 10 03:29:35 PM PDT 24
Finished Mar 10 03:29:36 PM PDT 24
Peak memory 194172 kb
Host smart-451bad46-5d04-4ba8-adad-4ab3aed8b7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915558739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3915558739
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.2136073182
Short name T224
Test name
Test status
Simulation time 3000066177 ps
CPU time 22.34 seconds
Started Mar 10 03:29:33 PM PDT 24
Finished Mar 10 03:29:55 PM PDT 24
Peak memory 196844 kb
Host smart-c764b494-a11c-48da-b1f2-abc4ff12c511
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136073182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.2136073182
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1925492281
Short name T555
Test name
Test status
Simulation time 81493982 ps
CPU time 0.82 seconds
Started Mar 10 03:29:33 PM PDT 24
Finished Mar 10 03:29:34 PM PDT 24
Peak memory 194912 kb
Host smart-756f0573-71f6-49ee-8b03-6bfb157ca244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925492281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1925492281
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.503989887
Short name T229
Test name
Test status
Simulation time 97506792 ps
CPU time 0.81 seconds
Started Mar 10 03:29:32 PM PDT 24
Finished Mar 10 03:29:34 PM PDT 24
Peak memory 195520 kb
Host smart-5ba6f6f0-2b5e-431a-b0f3-1f3b3a437728
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503989887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.503989887
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3907256339
Short name T720
Test name
Test status
Simulation time 49589678 ps
CPU time 2.14 seconds
Started Mar 10 03:29:33 PM PDT 24
Finished Mar 10 03:29:35 PM PDT 24
Peak memory 198192 kb
Host smart-f52a6404-5b75-4073-b73d-713900164422
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907256339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3907256339
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.3511629212
Short name T420
Test name
Test status
Simulation time 57677644 ps
CPU time 1.68 seconds
Started Mar 10 03:29:33 PM PDT 24
Finished Mar 10 03:29:35 PM PDT 24
Peak memory 196264 kb
Host smart-0ab60bb5-9a4e-4426-81b2-c4b3cbe8c695
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511629212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.3511629212
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3045230368
Short name T481
Test name
Test status
Simulation time 324694143 ps
CPU time 1.2 seconds
Started Mar 10 03:29:31 PM PDT 24
Finished Mar 10 03:29:33 PM PDT 24
Peak memory 196148 kb
Host smart-489c9726-d78d-4749-9cd4-9d5d479cae65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045230368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3045230368
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3592182605
Short name T580
Test name
Test status
Simulation time 379620725 ps
CPU time 1.19 seconds
Started Mar 10 03:29:31 PM PDT 24
Finished Mar 10 03:29:32 PM PDT 24
Peak memory 196856 kb
Host smart-17c45887-a337-48ee-874d-67694770adb3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592182605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3592182605
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2067664835
Short name T301
Test name
Test status
Simulation time 358298495 ps
CPU time 5.31 seconds
Started Mar 10 03:29:33 PM PDT 24
Finished Mar 10 03:29:39 PM PDT 24
Peak memory 198212 kb
Host smart-b6ebe722-fdc1-40a0-ba82-308196f92c68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067664835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2067664835
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3786171811
Short name T560
Test name
Test status
Simulation time 317266095 ps
CPU time 1.48 seconds
Started Mar 10 03:29:30 PM PDT 24
Finished Mar 10 03:29:32 PM PDT 24
Peak memory 195708 kb
Host smart-6ef42216-ad52-4454-a0ef-15921ca7f084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786171811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3786171811
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.2678551514
Short name T392
Test name
Test status
Simulation time 179577302 ps
CPU time 1.02 seconds
Started Mar 10 03:29:30 PM PDT 24
Finished Mar 10 03:29:31 PM PDT 24
Peak memory 196288 kb
Host smart-0c5b6e79-04e9-4639-a7db-ce2556caf190
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678551514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.2678551514
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1678984410
Short name T113
Test name
Test status
Simulation time 6878815257 ps
CPU time 51.13 seconds
Started Mar 10 03:29:34 PM PDT 24
Finished Mar 10 03:30:25 PM PDT 24
Peak memory 198304 kb
Host smart-2e346a85-90d5-4ef8-bc54-7f6caa502203
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678984410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1678984410
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3310420286
Short name T314
Test name
Test status
Simulation time 38148222 ps
CPU time 0.58 seconds
Started Mar 10 03:29:42 PM PDT 24
Finished Mar 10 03:29:43 PM PDT 24
Peak memory 194088 kb
Host smart-ae6f2554-5661-4d28-9b4c-f65ae3ba6ab2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310420286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3310420286
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.765441881
Short name T148
Test name
Test status
Simulation time 160638628 ps
CPU time 1.02 seconds
Started Mar 10 03:29:35 PM PDT 24
Finished Mar 10 03:29:37 PM PDT 24
Peak memory 196164 kb
Host smart-b4983359-67c9-4218-9ac9-d24770512e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765441881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.765441881
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3859781257
Short name T307
Test name
Test status
Simulation time 194317241 ps
CPU time 7.14 seconds
Started Mar 10 03:29:38 PM PDT 24
Finished Mar 10 03:29:46 PM PDT 24
Peak memory 197032 kb
Host smart-8ac51180-0435-4a77-a746-54ab32915ad2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859781257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3859781257
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.734630528
Short name T135
Test name
Test status
Simulation time 75673981 ps
CPU time 1.04 seconds
Started Mar 10 03:29:36 PM PDT 24
Finished Mar 10 03:29:38 PM PDT 24
Peak memory 196468 kb
Host smart-2d2af161-314d-4a83-a60e-5b59ec894248
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734630528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.734630528
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3658492648
Short name T407
Test name
Test status
Simulation time 114063635 ps
CPU time 1.43 seconds
Started Mar 10 03:29:39 PM PDT 24
Finished Mar 10 03:29:42 PM PDT 24
Peak memory 197308 kb
Host smart-5b2096d6-4945-456b-a8d9-825ef524b057
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658492648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3658492648
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.2877810376
Short name T182
Test name
Test status
Simulation time 72189196 ps
CPU time 3.05 seconds
Started Mar 10 03:29:36 PM PDT 24
Finished Mar 10 03:29:39 PM PDT 24
Peak memory 196512 kb
Host smart-f6d4043b-7903-4c78-a75e-110140dd1e61
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877810376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.2877810376
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2674298527
Short name T585
Test name
Test status
Simulation time 111162044 ps
CPU time 2.17 seconds
Started Mar 10 03:29:38 PM PDT 24
Finished Mar 10 03:29:41 PM PDT 24
Peak memory 196084 kb
Host smart-cb779b13-0164-40c4-bd59-3cdb20713276
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674298527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2674298527
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.4156286310
Short name T11
Test name
Test status
Simulation time 35562947 ps
CPU time 1.25 seconds
Started Mar 10 03:29:33 PM PDT 24
Finished Mar 10 03:29:34 PM PDT 24
Peak memory 197032 kb
Host smart-b8791acc-1252-4ea4-91ad-4f4b09705fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156286310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.4156286310
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.200598667
Short name T424
Test name
Test status
Simulation time 100678221 ps
CPU time 1.31 seconds
Started Mar 10 03:29:39 PM PDT 24
Finished Mar 10 03:29:41 PM PDT 24
Peak memory 197204 kb
Host smart-c02b7f2a-e976-4802-8170-81375d5d94d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200598667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.200598667
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2230064191
Short name T273
Test name
Test status
Simulation time 43774644 ps
CPU time 2.34 seconds
Started Mar 10 03:29:37 PM PDT 24
Finished Mar 10 03:29:40 PM PDT 24
Peak memory 198144 kb
Host smart-f5fa4fac-6f5d-43e0-9385-7e8451465a8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230064191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2230064191
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3454295133
Short name T19
Test name
Test status
Simulation time 74066103 ps
CPU time 0.82 seconds
Started Mar 10 03:29:34 PM PDT 24
Finished Mar 10 03:29:35 PM PDT 24
Peak memory 195320 kb
Host smart-e75155c7-7c15-4c76-b72e-86e87ebbce14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454295133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3454295133
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1800313461
Short name T705
Test name
Test status
Simulation time 40787727 ps
CPU time 0.89 seconds
Started Mar 10 03:29:33 PM PDT 24
Finished Mar 10 03:29:34 PM PDT 24
Peak memory 195392 kb
Host smart-a267e622-46c2-4598-b0f6-cfee33b66e49
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800313461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1800313461
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3833006172
Short name T454
Test name
Test status
Simulation time 29784386321 ps
CPU time 98.33 seconds
Started Mar 10 03:29:35 PM PDT 24
Finished Mar 10 03:31:14 PM PDT 24
Peak memory 198384 kb
Host smart-9685e32d-1441-497e-8253-037d955d6df6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833006172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3833006172
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.698880204
Short name T172
Test name
Test status
Simulation time 13449153 ps
CPU time 0.62 seconds
Started Mar 10 03:29:46 PM PDT 24
Finished Mar 10 03:29:47 PM PDT 24
Peak memory 195040 kb
Host smart-3d8bac9c-6713-4a4d-85e0-f3af42722e8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698880204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.698880204
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2588318744
Short name T688
Test name
Test status
Simulation time 33807370 ps
CPU time 0.9 seconds
Started Mar 10 03:29:41 PM PDT 24
Finished Mar 10 03:29:43 PM PDT 24
Peak memory 195264 kb
Host smart-ef61f8e4-1f78-4506-a0be-eeaf37ba430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588318744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2588318744
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1040249783
Short name T250
Test name
Test status
Simulation time 895091783 ps
CPU time 24.39 seconds
Started Mar 10 03:29:42 PM PDT 24
Finished Mar 10 03:30:06 PM PDT 24
Peak memory 195696 kb
Host smart-1186989d-71e5-4992-bdf0-ab483d3651cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040249783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1040249783
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2272193597
Short name T356
Test name
Test status
Simulation time 109041158 ps
CPU time 0.85 seconds
Started Mar 10 03:29:45 PM PDT 24
Finished Mar 10 03:29:46 PM PDT 24
Peak memory 196180 kb
Host smart-137469f6-ce2a-44fb-a55e-faaaae4d5857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272193597 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2272193597
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3847295552
Short name T228
Test name
Test status
Simulation time 74085667 ps
CPU time 0.78 seconds
Started Mar 10 03:29:43 PM PDT 24
Finished Mar 10 03:29:44 PM PDT 24
Peak memory 195236 kb
Host smart-ff10bc9d-d4b7-4ec2-bea7-db8510022cab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847295552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3847295552
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2608462112
Short name T103
Test name
Test status
Simulation time 132793788 ps
CPU time 3.13 seconds
Started Mar 10 03:29:48 PM PDT 24
Finished Mar 10 03:29:51 PM PDT 24
Peak memory 198220 kb
Host smart-acd0ae51-131b-4e33-b148-e345442e04ae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608462112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2608462112
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1822451477
Short name T366
Test name
Test status
Simulation time 410766177 ps
CPU time 2.37 seconds
Started Mar 10 03:29:44 PM PDT 24
Finished Mar 10 03:29:47 PM PDT 24
Peak memory 196376 kb
Host smart-c8f40167-3636-4f07-8bfa-b0c911347ba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822451477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1822451477
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3499499242
Short name T360
Test name
Test status
Simulation time 193819758 ps
CPU time 1.3 seconds
Started Mar 10 03:29:43 PM PDT 24
Finished Mar 10 03:29:45 PM PDT 24
Peak memory 197284 kb
Host smart-dde8da34-154b-4bc7-9d0a-a1efbdd98ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499499242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3499499242
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.3980100852
Short name T188
Test name
Test status
Simulation time 133478859 ps
CPU time 1.26 seconds
Started Mar 10 03:29:47 PM PDT 24
Finished Mar 10 03:29:49 PM PDT 24
Peak memory 196212 kb
Host smart-8b630410-fa24-403e-8a0a-72d070250a93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980100852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.3980100852
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.2421212689
Short name T427
Test name
Test status
Simulation time 566030259 ps
CPU time 6.38 seconds
Started Mar 10 03:29:49 PM PDT 24
Finished Mar 10 03:29:56 PM PDT 24
Peak memory 198096 kb
Host smart-f3aad360-360c-4779-a577-65e36b070af1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421212689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.2421212689
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.3713339843
Short name T540
Test name
Test status
Simulation time 130115901 ps
CPU time 1.12 seconds
Started Mar 10 03:29:41 PM PDT 24
Finished Mar 10 03:29:43 PM PDT 24
Peak memory 195932 kb
Host smart-336ec950-9127-4005-b6db-218ac544174e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713339843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.3713339843
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2499081763
Short name T541
Test name
Test status
Simulation time 42385796 ps
CPU time 1.26 seconds
Started Mar 10 03:29:42 PM PDT 24
Finished Mar 10 03:29:43 PM PDT 24
Peak memory 195736 kb
Host smart-57a63580-51d0-48bc-bd30-2a37e5f34f06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499081763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2499081763
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.2733314547
Short name T8
Test name
Test status
Simulation time 51179070185 ps
CPU time 159 seconds
Started Mar 10 03:29:46 PM PDT 24
Finished Mar 10 03:32:26 PM PDT 24
Peak memory 191944 kb
Host smart-c7b3ae05-4baf-4a98-9feb-b343c8af7aaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733314547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.2733314547
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.600688053
Short name T605
Test name
Test status
Simulation time 37307980 ps
CPU time 0.6 seconds
Started Mar 10 03:29:53 PM PDT 24
Finished Mar 10 03:29:54 PM PDT 24
Peak memory 194848 kb
Host smart-7877e70e-a489-403d-85fa-3bd19f78f7b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600688053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.600688053
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.4257472441
Short name T471
Test name
Test status
Simulation time 42111954 ps
CPU time 0.94 seconds
Started Mar 10 03:29:46 PM PDT 24
Finished Mar 10 03:29:48 PM PDT 24
Peak memory 197408 kb
Host smart-78b579ba-b55e-4671-bb15-ff5e2f5a186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257472441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.4257472441
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.1319845430
Short name T190
Test name
Test status
Simulation time 659507480 ps
CPU time 25.75 seconds
Started Mar 10 03:29:46 PM PDT 24
Finished Mar 10 03:30:13 PM PDT 24
Peak memory 197016 kb
Host smart-6b9e8477-075c-450e-a90c-bfa323e4cbe8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319845430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.1319845430
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.1075292099
Short name T678
Test name
Test status
Simulation time 39800271 ps
CPU time 0.86 seconds
Started Mar 10 03:29:51 PM PDT 24
Finished Mar 10 03:29:52 PM PDT 24
Peak memory 195840 kb
Host smart-c01c8c03-f521-4c6e-bbce-7c8c9e8b554a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075292099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.1075292099
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.3085506255
Short name T526
Test name
Test status
Simulation time 80485089 ps
CPU time 1.48 seconds
Started Mar 10 03:29:46 PM PDT 24
Finished Mar 10 03:29:49 PM PDT 24
Peak memory 197332 kb
Host smart-fe2feec2-3eb0-4196-932d-dd03f9080489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085506255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.3085506255
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.241031739
Short name T557
Test name
Test status
Simulation time 74883963 ps
CPU time 3.11 seconds
Started Mar 10 03:29:45 PM PDT 24
Finished Mar 10 03:29:48 PM PDT 24
Peak memory 198252 kb
Host smart-47f6246f-abca-42f8-9774-e28760603a39
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241031739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.241031739
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.735075310
Short name T551
Test name
Test status
Simulation time 390078044 ps
CPU time 2.67 seconds
Started Mar 10 03:29:45 PM PDT 24
Finished Mar 10 03:29:48 PM PDT 24
Peak memory 198140 kb
Host smart-4bb7c363-91de-49f6-86a1-067f61f519e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735075310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger.
735075310
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1789680935
Short name T635
Test name
Test status
Simulation time 285575794 ps
CPU time 1.42 seconds
Started Mar 10 03:29:45 PM PDT 24
Finished Mar 10 03:29:47 PM PDT 24
Peak memory 197256 kb
Host smart-0b67fecd-9543-42b5-a60a-048b5176bbef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789680935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1789680935
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3767053989
Short name T254
Test name
Test status
Simulation time 126276103 ps
CPU time 1.19 seconds
Started Mar 10 03:29:45 PM PDT 24
Finished Mar 10 03:29:47 PM PDT 24
Peak memory 197168 kb
Host smart-fe7455bb-b7a7-4559-b782-c7bc2e005131
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767053989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3767053989
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1767611837
Short name T191
Test name
Test status
Simulation time 245765157 ps
CPU time 1.61 seconds
Started Mar 10 03:29:46 PM PDT 24
Finished Mar 10 03:29:48 PM PDT 24
Peak memory 198164 kb
Host smart-7e3becf2-0597-4f6e-af46-0496170172a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767611837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1767611837
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1841476302
Short name T584
Test name
Test status
Simulation time 58553324 ps
CPU time 0.89 seconds
Started Mar 10 03:29:46 PM PDT 24
Finished Mar 10 03:29:48 PM PDT 24
Peak memory 195336 kb
Host smart-b877b737-3bd5-4eaa-8852-1e1366c94828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841476302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1841476302
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3805095909
Short name T348
Test name
Test status
Simulation time 66440075 ps
CPU time 1.29 seconds
Started Mar 10 03:29:46 PM PDT 24
Finished Mar 10 03:29:48 PM PDT 24
Peak memory 195736 kb
Host smart-81ee22a9-f2ca-4039-9e24-f95c27ceaf7e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805095909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3805095909
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.580433489
Short name T7
Test name
Test status
Simulation time 40515069577 ps
CPU time 236.26 seconds
Started Mar 10 03:29:59 PM PDT 24
Finished Mar 10 03:33:56 PM PDT 24
Peak memory 198320 kb
Host smart-7e671c0e-0096-446a-9ebf-75af134901ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580433489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.580433489
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.421356234
Short name T288
Test name
Test status
Simulation time 13514847 ps
CPU time 0.62 seconds
Started Mar 10 03:30:00 PM PDT 24
Finished Mar 10 03:30:01 PM PDT 24
Peak memory 194312 kb
Host smart-6a26cbc0-c7e6-4034-9559-2248d5333a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421356234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.421356234
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.134566376
Short name T388
Test name
Test status
Simulation time 41042459 ps
CPU time 0.64 seconds
Started Mar 10 03:29:54 PM PDT 24
Finished Mar 10 03:29:55 PM PDT 24
Peak memory 194616 kb
Host smart-b3c5aac0-951d-4ac1-b740-e7f54976150f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134566376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.134566376
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.3844188581
Short name T306
Test name
Test status
Simulation time 638559062 ps
CPU time 4.7 seconds
Started Mar 10 03:29:55 PM PDT 24
Finished Mar 10 03:30:00 PM PDT 24
Peak memory 196060 kb
Host smart-bc27bcc3-ec19-459f-b93f-739e8e9d0433
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844188581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.3844188581
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3576463046
Short name T330
Test name
Test status
Simulation time 95876526 ps
CPU time 0.92 seconds
Started Mar 10 03:30:00 PM PDT 24
Finished Mar 10 03:30:01 PM PDT 24
Peak memory 196136 kb
Host smart-c633ac03-ed03-46f2-928d-6c12679d4372
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576463046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3576463046
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.2601917274
Short name T672
Test name
Test status
Simulation time 216911644 ps
CPU time 1.24 seconds
Started Mar 10 03:29:55 PM PDT 24
Finished Mar 10 03:29:56 PM PDT 24
Peak memory 196168 kb
Host smart-0cb7b336-ec84-4d53-ae57-14be1f36f752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601917274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.2601917274
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.4102732187
Short name T335
Test name
Test status
Simulation time 324894469 ps
CPU time 2.05 seconds
Started Mar 10 03:29:56 PM PDT 24
Finished Mar 10 03:29:59 PM PDT 24
Peak memory 198220 kb
Host smart-213b25bf-1fe5-4300-9f97-3bc22ad07871
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102732187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.4102732187
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.362742293
Short name T237
Test name
Test status
Simulation time 163282616 ps
CPU time 1.91 seconds
Started Mar 10 03:29:56 PM PDT 24
Finished Mar 10 03:29:58 PM PDT 24
Peak memory 196668 kb
Host smart-69a3dfd7-84a6-4e7f-94ef-54b2f1f68783
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362742293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
362742293
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3387068498
Short name T569
Test name
Test status
Simulation time 42486621 ps
CPU time 1.05 seconds
Started Mar 10 03:29:55 PM PDT 24
Finished Mar 10 03:29:57 PM PDT 24
Peak memory 196140 kb
Host smart-f99cdf15-0919-49ef-ab57-2fb0ebdda487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387068498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3387068498
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3344666379
Short name T643
Test name
Test status
Simulation time 114187289 ps
CPU time 1.23 seconds
Started Mar 10 03:29:55 PM PDT 24
Finished Mar 10 03:29:56 PM PDT 24
Peak memory 196944 kb
Host smart-0ac68df1-c71c-4ed4-882a-01933c22ecb1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344666379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3344666379
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.3363277088
Short name T587
Test name
Test status
Simulation time 442815575 ps
CPU time 5.37 seconds
Started Mar 10 03:30:00 PM PDT 24
Finished Mar 10 03:30:06 PM PDT 24
Peak memory 198164 kb
Host smart-e836a5cf-0111-4646-ba2b-b58a3bc59920
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363277088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.3363277088
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.609271338
Short name T657
Test name
Test status
Simulation time 27697369 ps
CPU time 0.99 seconds
Started Mar 10 03:29:53 PM PDT 24
Finished Mar 10 03:29:54 PM PDT 24
Peak memory 195700 kb
Host smart-1783eae6-5483-41f7-8b32-9782488b2ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609271338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.609271338
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.4243534382
Short name T292
Test name
Test status
Simulation time 84648586 ps
CPU time 1.62 seconds
Started Mar 10 03:29:52 PM PDT 24
Finished Mar 10 03:29:54 PM PDT 24
Peak memory 196520 kb
Host smart-f9c521f0-9c6d-49cc-9d08-a54543d0a658
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243534382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.4243534382
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2352302759
Short name T21
Test name
Test status
Simulation time 4940882180 ps
CPU time 59.37 seconds
Started Mar 10 03:30:00 PM PDT 24
Finished Mar 10 03:31:00 PM PDT 24
Peak memory 198292 kb
Host smart-24340719-eef4-4090-9fe9-07e00a88ffad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352302759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2352302759
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.4128248856
Short name T59
Test name
Test status
Simulation time 455304787309 ps
CPU time 1126.51 seconds
Started Mar 10 03:29:58 PM PDT 24
Finished Mar 10 03:48:45 PM PDT 24
Peak memory 198560 kb
Host smart-a1e3b459-3b09-4dfc-b6e7-6ac462045100
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4128248856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.4128248856
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2397049874
Short name T713
Test name
Test status
Simulation time 14656462 ps
CPU time 0.66 seconds
Started Mar 10 03:30:10 PM PDT 24
Finished Mar 10 03:30:12 PM PDT 24
Peak memory 194300 kb
Host smart-82c35a5e-d33a-4d29-89a9-adb31633a718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397049874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2397049874
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.560465469
Short name T315
Test name
Test status
Simulation time 221163462 ps
CPU time 0.64 seconds
Started Mar 10 03:30:03 PM PDT 24
Finished Mar 10 03:30:04 PM PDT 24
Peak memory 194764 kb
Host smart-10eb7876-3852-4b26-9d11-0401d4e166f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560465469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.560465469
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1353511360
Short name T631
Test name
Test status
Simulation time 298863220 ps
CPU time 5.3 seconds
Started Mar 10 03:30:03 PM PDT 24
Finished Mar 10 03:30:08 PM PDT 24
Peak memory 195948 kb
Host smart-df265439-e113-4f81-8cb0-e7bbb84351d4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353511360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1353511360
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3162392899
Short name T4
Test name
Test status
Simulation time 251719768 ps
CPU time 1.24 seconds
Started Mar 10 03:30:02 PM PDT 24
Finished Mar 10 03:30:04 PM PDT 24
Peak memory 196608 kb
Host smart-ed6a7aaf-023d-4aaf-8c29-3f470918d342
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162392899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3162392899
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2227888917
Short name T528
Test name
Test status
Simulation time 305728821 ps
CPU time 1.57 seconds
Started Mar 10 03:30:03 PM PDT 24
Finished Mar 10 03:30:05 PM PDT 24
Peak memory 196780 kb
Host smart-fd573345-c89a-435d-98fc-c8da89acb6b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227888917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2227888917
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3117114201
Short name T378
Test name
Test status
Simulation time 604835767 ps
CPU time 4.01 seconds
Started Mar 10 03:30:01 PM PDT 24
Finished Mar 10 03:30:06 PM PDT 24
Peak memory 198228 kb
Host smart-29f70dcc-c3d3-4d14-814d-a514ca8f7f76
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117114201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3117114201
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.1655138696
Short name T626
Test name
Test status
Simulation time 285832447 ps
CPU time 3.54 seconds
Started Mar 10 03:30:07 PM PDT 24
Finished Mar 10 03:30:11 PM PDT 24
Peak memory 197396 kb
Host smart-4999653e-7fd1-4b52-8957-60d905d2a411
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655138696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.1655138696
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2170537861
Short name T714
Test name
Test status
Simulation time 72045708 ps
CPU time 1.51 seconds
Started Mar 10 03:30:03 PM PDT 24
Finished Mar 10 03:30:05 PM PDT 24
Peak memory 197128 kb
Host smart-3f72ca8c-0714-41e1-9583-914780aedce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170537861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2170537861
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.798821060
Short name T701
Test name
Test status
Simulation time 66133398 ps
CPU time 1.31 seconds
Started Mar 10 03:30:03 PM PDT 24
Finished Mar 10 03:30:04 PM PDT 24
Peak memory 196896 kb
Host smart-f41e7df4-6ab6-47e2-b2f6-1e8d0d7043d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798821060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup
_pulldown.798821060
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1281862570
Short name T489
Test name
Test status
Simulation time 1036386771 ps
CPU time 1.32 seconds
Started Mar 10 03:30:05 PM PDT 24
Finished Mar 10 03:30:06 PM PDT 24
Peak memory 198180 kb
Host smart-228e03d1-6bdf-4bb4-ae7f-8e8998671626
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281862570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1281862570
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2902616076
Short name T145
Test name
Test status
Simulation time 47093677 ps
CPU time 1.34 seconds
Started Mar 10 03:29:59 PM PDT 24
Finished Mar 10 03:30:01 PM PDT 24
Peak memory 196424 kb
Host smart-564d0ee2-e110-49fa-a2a1-5c21de789b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902616076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2902616076
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.997771757
Short name T316
Test name
Test status
Simulation time 71229213 ps
CPU time 1.26 seconds
Started Mar 10 03:30:00 PM PDT 24
Finished Mar 10 03:30:02 PM PDT 24
Peak memory 196632 kb
Host smart-dea3ff9c-a45a-4c93-9c5b-29564e637c01
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997771757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.997771757
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.584528355
Short name T243
Test name
Test status
Simulation time 25701268782 ps
CPU time 100.08 seconds
Started Mar 10 03:30:04 PM PDT 24
Finished Mar 10 03:31:44 PM PDT 24
Peak memory 198352 kb
Host smart-5dde9d93-e92f-4a96-8aed-b45be6cf06d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584528355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.584528355
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.216945720
Short name T57
Test name
Test status
Simulation time 43555657615 ps
CPU time 531.04 seconds
Started Mar 10 03:30:10 PM PDT 24
Finished Mar 10 03:39:02 PM PDT 24
Peak memory 198468 kb
Host smart-5213d8b9-2417-4129-9223-a956bd19c10e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=216945720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.216945720
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3375518006
Short name T572
Test name
Test status
Simulation time 49557648 ps
CPU time 0.55 seconds
Started Mar 10 03:30:10 PM PDT 24
Finished Mar 10 03:30:10 PM PDT 24
Peak memory 195044 kb
Host smart-db142928-0544-4ff9-9144-f265dfd3d2c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375518006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3375518006
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1325489168
Short name T143
Test name
Test status
Simulation time 23641678 ps
CPU time 0.79 seconds
Started Mar 10 03:30:06 PM PDT 24
Finished Mar 10 03:30:07 PM PDT 24
Peak memory 195288 kb
Host smart-83455cec-bbfd-41ef-adbf-cb40c30095ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325489168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1325489168
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3255875879
Short name T539
Test name
Test status
Simulation time 144496518 ps
CPU time 6.52 seconds
Started Mar 10 03:30:09 PM PDT 24
Finished Mar 10 03:30:16 PM PDT 24
Peak memory 196940 kb
Host smart-f1c9863a-12c2-448c-a647-f2bf5960f202
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255875879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3255875879
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1989749438
Short name T353
Test name
Test status
Simulation time 330248316 ps
CPU time 1.22 seconds
Started Mar 10 03:30:10 PM PDT 24
Finished Mar 10 03:30:12 PM PDT 24
Peak memory 198088 kb
Host smart-5e24140b-32fc-4a78-ab7b-7a0540bef254
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989749438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1989749438
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.312851639
Short name T341
Test name
Test status
Simulation time 372422092 ps
CPU time 1.58 seconds
Started Mar 10 03:30:06 PM PDT 24
Finished Mar 10 03:30:08 PM PDT 24
Peak memory 197304 kb
Host smart-6c97144e-6fbd-4845-843a-2c8ed5c23249
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312851639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.312851639
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.741486610
Short name T257
Test name
Test status
Simulation time 75513960 ps
CPU time 1.05 seconds
Started Mar 10 03:30:09 PM PDT 24
Finished Mar 10 03:30:11 PM PDT 24
Peak memory 197968 kb
Host smart-124396e9-054a-46a4-9a1a-ad450b067bf9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741486610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.741486610
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.220194707
Short name T352
Test name
Test status
Simulation time 35277490 ps
CPU time 1 seconds
Started Mar 10 03:30:10 PM PDT 24
Finished Mar 10 03:30:12 PM PDT 24
Peak memory 195620 kb
Host smart-48d41540-6cc8-44c7-937b-6026fbd65f3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220194707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
220194707
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1390715393
Short name T342
Test name
Test status
Simulation time 106234168 ps
CPU time 0.94 seconds
Started Mar 10 03:30:08 PM PDT 24
Finished Mar 10 03:30:10 PM PDT 24
Peak memory 196724 kb
Host smart-e0e25ebc-333b-4570-9041-9ddccc61df78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390715393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1390715393
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.1473627278
Short name T371
Test name
Test status
Simulation time 63992721 ps
CPU time 1.36 seconds
Started Mar 10 03:30:08 PM PDT 24
Finished Mar 10 03:30:10 PM PDT 24
Peak memory 198228 kb
Host smart-4603ca60-b115-4fc1-a22c-4f9f163f1230
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473627278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.1473627278
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_smoke.665578680
Short name T517
Test name
Test status
Simulation time 61785382 ps
CPU time 1.25 seconds
Started Mar 10 03:30:06 PM PDT 24
Finished Mar 10 03:30:08 PM PDT 24
Peak memory 195888 kb
Host smart-e0c66eb3-9e62-4e41-b45a-759071a5aa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665578680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.665578680
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.995578895
Short name T363
Test name
Test status
Simulation time 1071754468 ps
CPU time 1.33 seconds
Started Mar 10 03:30:07 PM PDT 24
Finished Mar 10 03:30:08 PM PDT 24
Peak memory 196932 kb
Host smart-8069a493-e904-407a-91a7-47e9930c45d8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995578895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.995578895
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2109417986
Short name T690
Test name
Test status
Simulation time 5974353327 ps
CPU time 50.3 seconds
Started Mar 10 03:30:08 PM PDT 24
Finished Mar 10 03:30:59 PM PDT 24
Peak memory 198380 kb
Host smart-30066256-e8fc-45d4-a6b1-cef40817751f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109417986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2109417986
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.929569874
Short name T13
Test name
Test status
Simulation time 39335597 ps
CPU time 0.61 seconds
Started Mar 10 03:25:31 PM PDT 24
Finished Mar 10 03:25:32 PM PDT 24
Peak memory 194824 kb
Host smart-ae75660a-b3b6-40fd-beae-18e95c56b61b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929569874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.929569874
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1692427447
Short name T443
Test name
Test status
Simulation time 50633218 ps
CPU time 0.88 seconds
Started Mar 10 03:25:36 PM PDT 24
Finished Mar 10 03:25:37 PM PDT 24
Peak memory 196668 kb
Host smart-d167ddc7-4334-491e-951f-22b448b59a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692427447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1692427447
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3444126448
Short name T718
Test name
Test status
Simulation time 618127333 ps
CPU time 20.34 seconds
Started Mar 10 03:25:30 PM PDT 24
Finished Mar 10 03:25:50 PM PDT 24
Peak memory 196692 kb
Host smart-52a23a46-5f4a-4eda-b2c5-e3025ce5e54a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444126448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3444126448
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1451382326
Short name T708
Test name
Test status
Simulation time 36960434 ps
CPU time 0.9 seconds
Started Mar 10 03:25:36 PM PDT 24
Finished Mar 10 03:25:38 PM PDT 24
Peak memory 196088 kb
Host smart-c33ae35a-c1b6-482e-97a9-7f4b9364f2bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451382326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1451382326
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.1999084099
Short name T621
Test name
Test status
Simulation time 57322400 ps
CPU time 1.08 seconds
Started Mar 10 03:25:25 PM PDT 24
Finished Mar 10 03:25:27 PM PDT 24
Peak memory 196188 kb
Host smart-ea7de85f-5e66-48ae-beab-0d70d183e50d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999084099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.1999084099
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.270752802
Short name T365
Test name
Test status
Simulation time 40251760 ps
CPU time 1.71 seconds
Started Mar 10 03:25:35 PM PDT 24
Finished Mar 10 03:25:37 PM PDT 24
Peak memory 198212 kb
Host smart-3aed7c29-22b2-4098-8607-661bc45dda82
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270752802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.270752802
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.1662492917
Short name T123
Test name
Test status
Simulation time 102453869 ps
CPU time 2.45 seconds
Started Mar 10 03:25:27 PM PDT 24
Finished Mar 10 03:25:30 PM PDT 24
Peak memory 196008 kb
Host smart-de2ea4c1-52fd-452f-a033-086a0fb69c69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662492917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
1662492917
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3907789330
Short name T154
Test name
Test status
Simulation time 24572089 ps
CPU time 0.83 seconds
Started Mar 10 03:25:26 PM PDT 24
Finished Mar 10 03:25:27 PM PDT 24
Peak memory 196208 kb
Host smart-6ec79b2c-9ce0-4494-aa34-4a1033d0dbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907789330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3907789330
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2368436250
Short name T317
Test name
Test status
Simulation time 20918485 ps
CPU time 0.84 seconds
Started Mar 10 03:25:36 PM PDT 24
Finished Mar 10 03:25:38 PM PDT 24
Peak memory 196544 kb
Host smart-08eb815f-d1a9-46fd-a83f-6e3e3bb22d5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368436250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2368436250
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.885812097
Short name T155
Test name
Test status
Simulation time 976852673 ps
CPU time 4.2 seconds
Started Mar 10 03:25:30 PM PDT 24
Finished Mar 10 03:25:34 PM PDT 24
Peak memory 198112 kb
Host smart-df687092-52d7-4b12-a9b4-e223a91ab60a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885812097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand
om_long_reg_writes_reg_reads.885812097
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.29995339
Short name T30
Test name
Test status
Simulation time 223600576 ps
CPU time 0.97 seconds
Started Mar 10 03:25:45 PM PDT 24
Finished Mar 10 03:25:46 PM PDT 24
Peak memory 213788 kb
Host smart-5fd37f07-6fc1-4c13-887a-c4e88f56efff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29995339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.29995339
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.165864930
Short name T387
Test name
Test status
Simulation time 46881907 ps
CPU time 0.98 seconds
Started Mar 10 03:25:36 PM PDT 24
Finished Mar 10 03:25:38 PM PDT 24
Peak memory 195936 kb
Host smart-b132d85f-2d7e-4949-ae74-cbfad6768d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165864930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.165864930
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3028385701
Short name T46
Test name
Test status
Simulation time 89308489 ps
CPU time 1.22 seconds
Started Mar 10 03:25:25 PM PDT 24
Finished Mar 10 03:25:26 PM PDT 24
Peak memory 195720 kb
Host smart-4e2f8dfe-5141-4528-a224-bb69d8281d65
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028385701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3028385701
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2417707765
Short name T456
Test name
Test status
Simulation time 18848010123 ps
CPU time 74.48 seconds
Started Mar 10 03:25:30 PM PDT 24
Finished Mar 10 03:26:44 PM PDT 24
Peak memory 198336 kb
Host smart-1b3d66c6-3835-4c0f-832d-c0e6c279cf8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417707765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2417707765
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1243472840
Short name T308
Test name
Test status
Simulation time 103142495 ps
CPU time 0.6 seconds
Started Mar 10 03:30:17 PM PDT 24
Finished Mar 10 03:30:18 PM PDT 24
Peak memory 194824 kb
Host smart-62603c88-f80f-4724-b1c3-c48db1a159b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243472840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1243472840
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2684175391
Short name T240
Test name
Test status
Simulation time 38329857 ps
CPU time 0.76 seconds
Started Mar 10 03:30:10 PM PDT 24
Finished Mar 10 03:30:11 PM PDT 24
Peak memory 194280 kb
Host smart-147c28bf-689c-4830-997f-c159901ab53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684175391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2684175391
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.911807141
Short name T511
Test name
Test status
Simulation time 706374213 ps
CPU time 20.41 seconds
Started Mar 10 03:30:18 PM PDT 24
Finished Mar 10 03:30:38 PM PDT 24
Peak memory 197136 kb
Host smart-8aee5874-14f2-4123-ae08-b255f07f9e72
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911807141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.911807141
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.4282041476
Short name T210
Test name
Test status
Simulation time 70794714 ps
CPU time 1.04 seconds
Started Mar 10 03:30:18 PM PDT 24
Finished Mar 10 03:30:20 PM PDT 24
Peak memory 196736 kb
Host smart-b9e6d600-7e75-4055-bb9b-43f63c5c1685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282041476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.4282041476
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1752354270
Short name T628
Test name
Test status
Simulation time 187315522 ps
CPU time 0.8 seconds
Started Mar 10 03:30:11 PM PDT 24
Finished Mar 10 03:30:12 PM PDT 24
Peak memory 195544 kb
Host smart-6d0dbb69-ec08-43f3-a4dd-fa15f2be2ba9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752354270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1752354270
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.373849943
Short name T624
Test name
Test status
Simulation time 325251427 ps
CPU time 3.71 seconds
Started Mar 10 03:30:16 PM PDT 24
Finished Mar 10 03:30:20 PM PDT 24
Peak memory 198228 kb
Host smart-839afd83-8917-4f5e-89f3-8aba844194e4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373849943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.373849943
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3850288323
Short name T707
Test name
Test status
Simulation time 177321368 ps
CPU time 1.28 seconds
Started Mar 10 03:30:13 PM PDT 24
Finished Mar 10 03:30:15 PM PDT 24
Peak memory 196304 kb
Host smart-bb09581c-6178-43d6-bf51-e9fff5e889f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850288323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3850288323
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.2750847733
Short name T345
Test name
Test status
Simulation time 23688774 ps
CPU time 0.78 seconds
Started Mar 10 03:30:13 PM PDT 24
Finished Mar 10 03:30:14 PM PDT 24
Peak memory 195504 kb
Host smart-2d849522-abb2-456c-9e72-03b3c0ba92d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750847733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.2750847733
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3757789962
Short name T276
Test name
Test status
Simulation time 114159784 ps
CPU time 0.81 seconds
Started Mar 10 03:30:11 PM PDT 24
Finished Mar 10 03:30:13 PM PDT 24
Peak memory 196216 kb
Host smart-02fd1fbf-df0f-446c-a770-c5d18309c4d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757789962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3757789962
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.483228967
Short name T514
Test name
Test status
Simulation time 301521887 ps
CPU time 5.57 seconds
Started Mar 10 03:30:16 PM PDT 24
Finished Mar 10 03:30:22 PM PDT 24
Peak memory 198176 kb
Host smart-e36e3533-8d63-4e83-82ce-11a2264d0a1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483228967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.483228967
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1319215921
Short name T598
Test name
Test status
Simulation time 52553136 ps
CPU time 0.9 seconds
Started Mar 10 03:30:08 PM PDT 24
Finished Mar 10 03:30:10 PM PDT 24
Peak memory 196224 kb
Host smart-bfbd6f8c-aeb1-4cbf-bd37-ac80a439f949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319215921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1319215921
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2240482353
Short name T16
Test name
Test status
Simulation time 46603455 ps
CPU time 1.32 seconds
Started Mar 10 03:30:12 PM PDT 24
Finished Mar 10 03:30:13 PM PDT 24
Peak memory 195696 kb
Host smart-9cc0acd6-7eef-4ad1-acda-2881c6ba3636
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240482353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2240482353
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.184998960
Short name T722
Test name
Test status
Simulation time 3422074250 ps
CPU time 92.86 seconds
Started Mar 10 03:30:17 PM PDT 24
Finished Mar 10 03:31:50 PM PDT 24
Peak memory 198348 kb
Host smart-acf7a0f9-c3b8-4170-bd2b-5a7d0c76cc5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184998960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.184998960
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.2142415776
Short name T492
Test name
Test status
Simulation time 22430776 ps
CPU time 0.59 seconds
Started Mar 10 03:30:21 PM PDT 24
Finished Mar 10 03:30:22 PM PDT 24
Peak memory 194088 kb
Host smart-ae19df34-5afb-41cb-be48-86820d2dc8e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142415776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.2142415776
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2767428005
Short name T285
Test name
Test status
Simulation time 49464465 ps
CPU time 0.74 seconds
Started Mar 10 03:30:20 PM PDT 24
Finished Mar 10 03:30:21 PM PDT 24
Peak memory 195028 kb
Host smart-8cfc8825-91f8-4d92-9885-c2c29b4f9ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767428005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2767428005
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.759511672
Short name T655
Test name
Test status
Simulation time 316501524 ps
CPU time 16.83 seconds
Started Mar 10 03:30:21 PM PDT 24
Finished Mar 10 03:30:38 PM PDT 24
Peak memory 198152 kb
Host smart-495e0190-373c-4d8a-b5a6-6e8e14ecc888
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759511672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.759511672
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.845761642
Short name T508
Test name
Test status
Simulation time 188662042 ps
CPU time 0.88 seconds
Started Mar 10 03:30:23 PM PDT 24
Finished Mar 10 03:30:25 PM PDT 24
Peak memory 196196 kb
Host smart-b0d2376f-d323-49ad-8e1d-bc1fbc233371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845761642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.845761642
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1750474742
Short name T386
Test name
Test status
Simulation time 1459320905 ps
CPU time 1.46 seconds
Started Mar 10 03:30:22 PM PDT 24
Finished Mar 10 03:30:24 PM PDT 24
Peak memory 197408 kb
Host smart-de13de7b-a105-4f94-bf12-faa230bf238e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750474742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1750474742
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3496937612
Short name T677
Test name
Test status
Simulation time 358603167 ps
CPU time 1.01 seconds
Started Mar 10 03:30:23 PM PDT 24
Finished Mar 10 03:30:25 PM PDT 24
Peak memory 196984 kb
Host smart-1c996bfc-7b22-445b-9021-2628644aae77
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496937612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3496937612
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.569571797
Short name T681
Test name
Test status
Simulation time 477626121 ps
CPU time 2.95 seconds
Started Mar 10 03:30:21 PM PDT 24
Finished Mar 10 03:30:25 PM PDT 24
Peak memory 196008 kb
Host smart-946c6ca5-240a-4103-bd69-b60f3a6fc43e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569571797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
569571797
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.2278978178
Short name T377
Test name
Test status
Simulation time 41905604 ps
CPU time 0.92 seconds
Started Mar 10 03:30:22 PM PDT 24
Finished Mar 10 03:30:23 PM PDT 24
Peak memory 197320 kb
Host smart-b0e8d778-c4f8-4a30-8cac-921330725d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278978178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.2278978178
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2664541638
Short name T381
Test name
Test status
Simulation time 279279382 ps
CPU time 1.52 seconds
Started Mar 10 03:30:22 PM PDT 24
Finished Mar 10 03:30:24 PM PDT 24
Peak memory 197072 kb
Host smart-1b105bb6-15dd-488e-ac74-26c5dee3c419
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664541638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2664541638
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3718252928
Short name T259
Test name
Test status
Simulation time 210122742 ps
CPU time 3.69 seconds
Started Mar 10 03:30:20 PM PDT 24
Finished Mar 10 03:30:24 PM PDT 24
Peak memory 198096 kb
Host smart-66623503-2faa-4156-b207-64d0895c368e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718252928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3718252928
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3074079350
Short name T312
Test name
Test status
Simulation time 191954294 ps
CPU time 1.14 seconds
Started Mar 10 03:30:17 PM PDT 24
Finished Mar 10 03:30:19 PM PDT 24
Peak memory 195652 kb
Host smart-04c499f9-f513-45e2-b676-fd3e8e8c716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074079350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3074079350
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3651124898
Short name T470
Test name
Test status
Simulation time 121549421 ps
CPU time 1.17 seconds
Started Mar 10 03:30:15 PM PDT 24
Finished Mar 10 03:30:17 PM PDT 24
Peak memory 195988 kb
Host smart-5fd4a6b4-431f-4790-aeb7-8612f33487ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651124898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3651124898
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.3826817368
Short name T6
Test name
Test status
Simulation time 8374570147 ps
CPU time 97.84 seconds
Started Mar 10 03:30:22 PM PDT 24
Finished Mar 10 03:32:00 PM PDT 24
Peak memory 198240 kb
Host smart-1ba1fad6-cbe9-41b6-87ca-83024c2c4181
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826817368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.3826817368
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.688914853
Short name T675
Test name
Test status
Simulation time 23268792 ps
CPU time 0.6 seconds
Started Mar 10 03:30:25 PM PDT 24
Finished Mar 10 03:30:26 PM PDT 24
Peak memory 194080 kb
Host smart-1f9c5640-59f6-4e17-be6e-10b9e3831a53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688914853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.688914853
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3476212756
Short name T274
Test name
Test status
Simulation time 118736124 ps
CPU time 0.98 seconds
Started Mar 10 03:30:27 PM PDT 24
Finished Mar 10 03:30:28 PM PDT 24
Peak memory 197128 kb
Host smart-8660861d-c3de-4ecf-a8e5-0c65587a35a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476212756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3476212756
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2619033917
Short name T706
Test name
Test status
Simulation time 2394114125 ps
CPU time 22.44 seconds
Started Mar 10 03:30:26 PM PDT 24
Finished Mar 10 03:30:49 PM PDT 24
Peak memory 198276 kb
Host smart-1e24c9bd-0313-4bff-ad8d-ef8deb80b547
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619033917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2619033917
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2576634542
Short name T2
Test name
Test status
Simulation time 90930602 ps
CPU time 1.08 seconds
Started Mar 10 03:30:26 PM PDT 24
Finished Mar 10 03:30:27 PM PDT 24
Peak memory 196828 kb
Host smart-f42373b1-4c85-418c-b9eb-f4997d7ebbd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576634542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2576634542
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3600891763
Short name T303
Test name
Test status
Simulation time 62586732 ps
CPU time 0.82 seconds
Started Mar 10 03:30:25 PM PDT 24
Finished Mar 10 03:30:26 PM PDT 24
Peak memory 195536 kb
Host smart-9971901a-936c-4059-a660-e942eef39d34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600891763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3600891763
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.2078201132
Short name T516
Test name
Test status
Simulation time 83565996 ps
CPU time 1.11 seconds
Started Mar 10 03:30:25 PM PDT 24
Finished Mar 10 03:30:26 PM PDT 24
Peak memory 196380 kb
Host smart-29895e27-a785-4942-9f7a-6eae7c4e49ac
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078201132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.2078201132
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.2360838980
Short name T138
Test name
Test status
Simulation time 140188532 ps
CPU time 1.19 seconds
Started Mar 10 03:30:25 PM PDT 24
Finished Mar 10 03:30:27 PM PDT 24
Peak memory 195684 kb
Host smart-c71c8171-c93f-4173-b2aa-f43e9b62fe00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360838980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.2360838980
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.1121438454
Short name T698
Test name
Test status
Simulation time 211462950 ps
CPU time 1.2 seconds
Started Mar 10 03:30:25 PM PDT 24
Finished Mar 10 03:30:26 PM PDT 24
Peak memory 196744 kb
Host smart-31bfeff9-a3f0-4c83-9740-367d5e3a9345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121438454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.1121438454
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3568578587
Short name T636
Test name
Test status
Simulation time 199920828 ps
CPU time 1.24 seconds
Started Mar 10 03:30:26 PM PDT 24
Finished Mar 10 03:30:27 PM PDT 24
Peak memory 196188 kb
Host smart-e6c35a82-8c1d-4a06-9d5d-78bee2f99024
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568578587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3568578587
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.824824412
Short name T411
Test name
Test status
Simulation time 149151132 ps
CPU time 2.15 seconds
Started Mar 10 03:30:25 PM PDT 24
Finished Mar 10 03:30:27 PM PDT 24
Peak memory 198132 kb
Host smart-0f48ca45-2eee-4f2b-984e-e6419ca85e7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824824412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.824824412
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2104227802
Short name T564
Test name
Test status
Simulation time 152282785 ps
CPU time 0.85 seconds
Started Mar 10 03:30:22 PM PDT 24
Finished Mar 10 03:30:23 PM PDT 24
Peak memory 195416 kb
Host smart-63d51286-c5af-4dae-91ef-7d5e59d62b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104227802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2104227802
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1751389953
Short name T521
Test name
Test status
Simulation time 125897196 ps
CPU time 1.22 seconds
Started Mar 10 03:30:24 PM PDT 24
Finished Mar 10 03:30:25 PM PDT 24
Peak memory 195944 kb
Host smart-4329690d-44a6-46a0-8eb8-2a4fc137c20b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751389953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1751389953
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.778834324
Short name T590
Test name
Test status
Simulation time 28488273786 ps
CPU time 166.93 seconds
Started Mar 10 03:30:25 PM PDT 24
Finished Mar 10 03:33:12 PM PDT 24
Peak memory 198316 kb
Host smart-78862eff-8b1c-4152-b223-b0d077127c8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778834324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.778834324
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1648964511
Short name T241
Test name
Test status
Simulation time 38727072 ps
CPU time 0.61 seconds
Started Mar 10 03:30:33 PM PDT 24
Finished Mar 10 03:30:34 PM PDT 24
Peak memory 194092 kb
Host smart-79de861e-8694-40ef-99a3-f2737396e51e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648964511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1648964511
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3834470782
Short name T337
Test name
Test status
Simulation time 27540077 ps
CPU time 0.81 seconds
Started Mar 10 03:30:31 PM PDT 24
Finished Mar 10 03:30:32 PM PDT 24
Peak memory 195384 kb
Host smart-14fab856-7c0e-4db2-a0e0-4af8c74e24a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834470782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3834470782
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.395687019
Short name T270
Test name
Test status
Simulation time 2066389367 ps
CPU time 20.85 seconds
Started Mar 10 03:30:34 PM PDT 24
Finished Mar 10 03:30:55 PM PDT 24
Peak memory 198176 kb
Host smart-07567350-7719-49f3-86fa-54cd6eb9f661
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395687019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stres
s.395687019
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.2715681564
Short name T321
Test name
Test status
Simulation time 25416161 ps
CPU time 0.75 seconds
Started Mar 10 03:30:28 PM PDT 24
Finished Mar 10 03:30:29 PM PDT 24
Peak memory 194752 kb
Host smart-f99e94ce-378d-4e76-a4ff-d62fc72efcb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715681564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.2715681564
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1372370048
Short name T554
Test name
Test status
Simulation time 53614901 ps
CPU time 1.44 seconds
Started Mar 10 03:30:30 PM PDT 24
Finished Mar 10 03:30:32 PM PDT 24
Peak memory 197076 kb
Host smart-659ecffd-c82c-451e-8b67-27a3cc00e827
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372370048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1372370048
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.4066694110
Short name T181
Test name
Test status
Simulation time 252364792 ps
CPU time 1.81 seconds
Started Mar 10 03:30:33 PM PDT 24
Finished Mar 10 03:30:35 PM PDT 24
Peak memory 196720 kb
Host smart-921ab759-c380-4081-a3e9-7d484f0e0617
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066694110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.4066694110
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2410426641
Short name T180
Test name
Test status
Simulation time 266956701 ps
CPU time 1.55 seconds
Started Mar 10 03:30:30 PM PDT 24
Finished Mar 10 03:30:32 PM PDT 24
Peak memory 196252 kb
Host smart-9f829d35-8816-46e2-aac7-4969b3817c91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410426641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2410426641
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.4024984563
Short name T203
Test name
Test status
Simulation time 103877010 ps
CPU time 1.18 seconds
Started Mar 10 03:30:30 PM PDT 24
Finished Mar 10 03:30:32 PM PDT 24
Peak memory 196172 kb
Host smart-3bf07114-d978-4981-8627-5bab647000ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024984563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.4024984563
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.516735360
Short name T116
Test name
Test status
Simulation time 50371691 ps
CPU time 1.23 seconds
Started Mar 10 03:30:29 PM PDT 24
Finished Mar 10 03:30:30 PM PDT 24
Peak memory 197100 kb
Host smart-5c145460-5167-4029-993d-71de2caca682
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516735360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup
_pulldown.516735360
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.297308222
Short name T17
Test name
Test status
Simulation time 99523579 ps
CPU time 4.66 seconds
Started Mar 10 03:30:31 PM PDT 24
Finished Mar 10 03:30:36 PM PDT 24
Peak memory 198116 kb
Host smart-251f3079-961e-4adf-9d89-6a3cfa30320a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297308222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.297308222
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.2860075516
Short name T264
Test name
Test status
Simulation time 187062534 ps
CPU time 1.27 seconds
Started Mar 10 03:30:34 PM PDT 24
Finished Mar 10 03:30:35 PM PDT 24
Peak memory 196856 kb
Host smart-79fb80c2-55f4-41cd-ac17-477ff054410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860075516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.2860075516
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1607023727
Short name T347
Test name
Test status
Simulation time 147703420 ps
CPU time 1.38 seconds
Started Mar 10 03:30:33 PM PDT 24
Finished Mar 10 03:30:35 PM PDT 24
Peak memory 196880 kb
Host smart-31cbd0ae-7b06-45fc-92cb-032c9297597b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607023727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1607023727
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1387801863
Short name T110
Test name
Test status
Simulation time 6493521197 ps
CPU time 95.43 seconds
Started Mar 10 03:30:28 PM PDT 24
Finished Mar 10 03:32:04 PM PDT 24
Peak memory 198348 kb
Host smart-b1e66300-15f8-48ec-9b2b-a6d852c19972
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387801863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1387801863
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2702518056
Short name T52
Test name
Test status
Simulation time 78004344114 ps
CPU time 890.57 seconds
Started Mar 10 03:30:29 PM PDT 24
Finished Mar 10 03:45:20 PM PDT 24
Peak memory 198504 kb
Host smart-0d9663b8-9a54-4887-8f49-2970cc939674
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2702518056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2702518056
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3943472524
Short name T566
Test name
Test status
Simulation time 16033221 ps
CPU time 0.6 seconds
Started Mar 10 03:30:38 PM PDT 24
Finished Mar 10 03:30:39 PM PDT 24
Peak memory 195148 kb
Host smart-df7e9de6-c29d-4552-849b-c9dcd95af0b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943472524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3943472524
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1419160618
Short name T390
Test name
Test status
Simulation time 29121340 ps
CPU time 0.87 seconds
Started Mar 10 03:30:34 PM PDT 24
Finished Mar 10 03:30:35 PM PDT 24
Peak memory 195492 kb
Host smart-86a98bee-6cef-4c6c-a79e-cbbb138007bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419160618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1419160618
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.4135508845
Short name T104
Test name
Test status
Simulation time 1198334510 ps
CPU time 20.42 seconds
Started Mar 10 03:30:39 PM PDT 24
Finished Mar 10 03:30:59 PM PDT 24
Peak memory 196920 kb
Host smart-88d4553f-b0a2-471e-ad37-808242bdf6e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135508845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.4135508845
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3119127946
Short name T637
Test name
Test status
Simulation time 37534713 ps
CPU time 0.77 seconds
Started Mar 10 03:30:40 PM PDT 24
Finished Mar 10 03:30:41 PM PDT 24
Peak memory 196644 kb
Host smart-a5b30e74-7246-4bb2-b56d-624e26db01c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119127946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3119127946
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1931441115
Short name T425
Test name
Test status
Simulation time 47667774 ps
CPU time 0.7 seconds
Started Mar 10 03:30:33 PM PDT 24
Finished Mar 10 03:30:34 PM PDT 24
Peak memory 194492 kb
Host smart-60d26df4-162e-4097-8280-1252c078360c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931441115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1931441115
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3010151344
Short name T260
Test name
Test status
Simulation time 151042842 ps
CPU time 1.96 seconds
Started Mar 10 03:30:34 PM PDT 24
Finished Mar 10 03:30:36 PM PDT 24
Peak memory 198276 kb
Host smart-cffedaee-469d-49a7-a21e-e5cd6b4cf02c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010151344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3010151344
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.4146615664
Short name T151
Test name
Test status
Simulation time 169766644 ps
CPU time 3.1 seconds
Started Mar 10 03:30:36 PM PDT 24
Finished Mar 10 03:30:40 PM PDT 24
Peak memory 196680 kb
Host smart-f0214f31-c6c3-401f-b991-9206d5cd8d21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146615664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.4146615664
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.1824950305
Short name T338
Test name
Test status
Simulation time 235251656 ps
CPU time 1.34 seconds
Started Mar 10 03:30:34 PM PDT 24
Finished Mar 10 03:30:35 PM PDT 24
Peak memory 196256 kb
Host smart-863737e0-79e9-412d-beec-30237d13c57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824950305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.1824950305
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3647679915
Short name T418
Test name
Test status
Simulation time 45096036 ps
CPU time 0.88 seconds
Started Mar 10 03:30:33 PM PDT 24
Finished Mar 10 03:30:34 PM PDT 24
Peak memory 195936 kb
Host smart-38dc257e-38d4-4e5c-869f-5a16c03bf66e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647679915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3647679915
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3971796875
Short name T200
Test name
Test status
Simulation time 232735274 ps
CPU time 5.73 seconds
Started Mar 10 03:30:40 PM PDT 24
Finished Mar 10 03:30:46 PM PDT 24
Peak memory 198144 kb
Host smart-2d65714b-8174-462e-a902-c7ad360d4052
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971796875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3971796875
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1942262718
Short name T328
Test name
Test status
Simulation time 21968374 ps
CPU time 0.8 seconds
Started Mar 10 03:30:34 PM PDT 24
Finished Mar 10 03:30:35 PM PDT 24
Peak memory 195244 kb
Host smart-9bb324cb-d9d4-447e-938f-5a790a7b5b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942262718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1942262718
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1995149335
Short name T178
Test name
Test status
Simulation time 65234052 ps
CPU time 0.8 seconds
Started Mar 10 03:30:34 PM PDT 24
Finished Mar 10 03:30:35 PM PDT 24
Peak memory 194320 kb
Host smart-1e31e0d0-90de-4450-b9b5-cd5bee92b3c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995149335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1995149335
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.397413916
Short name T519
Test name
Test status
Simulation time 31011080042 ps
CPU time 205.58 seconds
Started Mar 10 03:30:38 PM PDT 24
Finished Mar 10 03:34:04 PM PDT 24
Peak memory 198300 kb
Host smart-5ba32d7d-1572-48cc-bffc-2e0ab187346a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397413916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.397413916
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3084755914
Short name T483
Test name
Test status
Simulation time 73636677976 ps
CPU time 824.82 seconds
Started Mar 10 03:30:39 PM PDT 24
Finished Mar 10 03:44:24 PM PDT 24
Peak memory 198452 kb
Host smart-cc6ced60-05f5-4f8c-b8b7-c1edd70d6c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3084755914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3084755914
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.1311018459
Short name T448
Test name
Test status
Simulation time 38369785 ps
CPU time 0.59 seconds
Started Mar 10 03:30:45 PM PDT 24
Finished Mar 10 03:30:45 PM PDT 24
Peak memory 194808 kb
Host smart-c8fccf8f-9a3e-42ac-a5d6-b1a36d21a6e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311018459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.1311018459
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.2610561889
Short name T218
Test name
Test status
Simulation time 17524656 ps
CPU time 0.67 seconds
Started Mar 10 03:30:39 PM PDT 24
Finished Mar 10 03:30:40 PM PDT 24
Peak memory 194128 kb
Host smart-07790b15-cef8-4cfa-b8be-f88b54d3255c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610561889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.2610561889
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1047929289
Short name T612
Test name
Test status
Simulation time 741470519 ps
CPU time 13.57 seconds
Started Mar 10 03:30:41 PM PDT 24
Finished Mar 10 03:30:55 PM PDT 24
Peak memory 197176 kb
Host smart-94c5f8ca-0f50-4a07-be34-43a9123f55bd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047929289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1047929289
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1916300507
Short name T606
Test name
Test status
Simulation time 83393698 ps
CPU time 0.99 seconds
Started Mar 10 03:30:43 PM PDT 24
Finished Mar 10 03:30:44 PM PDT 24
Peak memory 196188 kb
Host smart-cb933665-62a2-42df-92a2-12040e4eb7e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916300507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1916300507
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1252890248
Short name T256
Test name
Test status
Simulation time 353275307 ps
CPU time 1.51 seconds
Started Mar 10 03:30:42 PM PDT 24
Finished Mar 10 03:30:43 PM PDT 24
Peak memory 196744 kb
Host smart-a26b7065-844c-4262-91ff-f527aa583ef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252890248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1252890248
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3970750833
Short name T712
Test name
Test status
Simulation time 40086942 ps
CPU time 1.08 seconds
Started Mar 10 03:30:43 PM PDT 24
Finished Mar 10 03:30:44 PM PDT 24
Peak memory 196252 kb
Host smart-9a7b41d5-b8ef-4267-9747-947a7713d2ee
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970750833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3970750833
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3394274385
Short name T275
Test name
Test status
Simulation time 143315672 ps
CPU time 3.53 seconds
Started Mar 10 03:30:37 PM PDT 24
Finished Mar 10 03:30:41 PM PDT 24
Peak memory 196676 kb
Host smart-34ef93b4-1df6-4c97-9bd9-169be9e1f9c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394274385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3394274385
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.4035531773
Short name T487
Test name
Test status
Simulation time 114092373 ps
CPU time 1.25 seconds
Started Mar 10 03:30:37 PM PDT 24
Finished Mar 10 03:30:38 PM PDT 24
Peak memory 196744 kb
Host smart-1baf07da-d8de-4923-8d1d-02dbba3b9a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035531773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.4035531773
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3056086568
Short name T311
Test name
Test status
Simulation time 30136169 ps
CPU time 1.14 seconds
Started Mar 10 03:30:38 PM PDT 24
Finished Mar 10 03:30:39 PM PDT 24
Peak memory 195948 kb
Host smart-63dcbf33-3c46-4e89-84a5-75ccfa9c949d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056086568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3056086568
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2520377257
Short name T213
Test name
Test status
Simulation time 4566585342 ps
CPU time 5.51 seconds
Started Mar 10 03:30:42 PM PDT 24
Finished Mar 10 03:30:48 PM PDT 24
Peak memory 198248 kb
Host smart-43b87829-80db-4e96-bd10-bed398f67e8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520377257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2520377257
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.236109418
Short name T223
Test name
Test status
Simulation time 172956495 ps
CPU time 1.51 seconds
Started Mar 10 03:30:39 PM PDT 24
Finished Mar 10 03:30:41 PM PDT 24
Peak memory 196796 kb
Host smart-62020eee-b57a-4ca6-a3d0-42ad5ae96d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236109418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.236109418
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3833810896
Short name T535
Test name
Test status
Simulation time 160659748 ps
CPU time 1.65 seconds
Started Mar 10 03:30:39 PM PDT 24
Finished Mar 10 03:30:41 PM PDT 24
Peak memory 196760 kb
Host smart-c56ed926-20ec-4c28-bee5-b4379e931a5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833810896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3833810896
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.800398826
Short name T147
Test name
Test status
Simulation time 4554445473 ps
CPU time 121.7 seconds
Started Mar 10 03:30:41 PM PDT 24
Finished Mar 10 03:32:43 PM PDT 24
Peak memory 198340 kb
Host smart-638ed4e4-140f-43a7-b865-091a34444f67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800398826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.800398826
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2964188776
Short name T671
Test name
Test status
Simulation time 706443502747 ps
CPU time 2398.72 seconds
Started Mar 10 03:30:41 PM PDT 24
Finished Mar 10 04:10:40 PM PDT 24
Peak memory 198436 kb
Host smart-ca6372ec-f6ca-40a9-9595-4b72349b9e07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2964188776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2964188776
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1397460329
Short name T204
Test name
Test status
Simulation time 15220368 ps
CPU time 0.61 seconds
Started Mar 10 03:30:50 PM PDT 24
Finished Mar 10 03:30:51 PM PDT 24
Peak memory 194072 kb
Host smart-65cfec4c-89f3-4706-b2a0-ad1489f2b286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397460329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1397460329
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.579631791
Short name T490
Test name
Test status
Simulation time 27461655 ps
CPU time 0.87 seconds
Started Mar 10 03:30:42 PM PDT 24
Finished Mar 10 03:30:43 PM PDT 24
Peak memory 197372 kb
Host smart-7ba1d179-0465-4895-a66d-d8044c86cc8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579631791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.579631791
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3708824819
Short name T494
Test name
Test status
Simulation time 4852552495 ps
CPU time 29.26 seconds
Started Mar 10 03:30:47 PM PDT 24
Finished Mar 10 03:31:17 PM PDT 24
Peak memory 197216 kb
Host smart-a1662535-de35-42f2-b13b-9ee3e89a7da2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708824819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3708824819
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3011644015
Short name T265
Test name
Test status
Simulation time 175160476 ps
CPU time 1.19 seconds
Started Mar 10 03:30:47 PM PDT 24
Finished Mar 10 03:30:48 PM PDT 24
Peak memory 196912 kb
Host smart-fb76abf3-2eaf-47e2-93ea-667e8c749c3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011644015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3011644015
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2541991632
Short name T461
Test name
Test status
Simulation time 442188841 ps
CPU time 1.44 seconds
Started Mar 10 03:30:42 PM PDT 24
Finished Mar 10 03:30:43 PM PDT 24
Peak memory 196708 kb
Host smart-04c197f9-352a-4bdb-a7fc-200c9aa1163e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541991632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2541991632
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2829159040
Short name T570
Test name
Test status
Simulation time 75727926 ps
CPU time 3.34 seconds
Started Mar 10 03:30:42 PM PDT 24
Finished Mar 10 03:30:46 PM PDT 24
Peak memory 198188 kb
Host smart-da8ed816-353b-44aa-83ed-3916974ac800
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829159040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2829159040
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.3404212145
Short name T362
Test name
Test status
Simulation time 161916949 ps
CPU time 3.62 seconds
Started Mar 10 03:30:46 PM PDT 24
Finished Mar 10 03:30:50 PM PDT 24
Peak memory 197188 kb
Host smart-50c587d0-719c-4a79-bedb-f51d6e7fc4ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404212145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.3404212145
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.1958390969
Short name T679
Test name
Test status
Simulation time 140906579 ps
CPU time 1.01 seconds
Started Mar 10 03:30:45 PM PDT 24
Finished Mar 10 03:30:46 PM PDT 24
Peak memory 196956 kb
Host smart-f8039700-fd75-40e1-9a9f-3bc7bcadcfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958390969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.1958390969
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3438633366
Short name T656
Test name
Test status
Simulation time 18799717 ps
CPU time 0.78 seconds
Started Mar 10 03:30:42 PM PDT 24
Finished Mar 10 03:30:43 PM PDT 24
Peak memory 195504 kb
Host smart-2d778b17-a5ce-4c56-9c2a-d12500b1055f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438633366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3438633366
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2228225267
Short name T614
Test name
Test status
Simulation time 444554303 ps
CPU time 4.52 seconds
Started Mar 10 03:30:54 PM PDT 24
Finished Mar 10 03:30:59 PM PDT 24
Peak memory 198028 kb
Host smart-f820edfe-0d88-4001-8f05-bf50c8549607
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228225267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2228225267
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.727627383
Short name T504
Test name
Test status
Simulation time 252325554 ps
CPU time 1.24 seconds
Started Mar 10 03:30:43 PM PDT 24
Finished Mar 10 03:30:44 PM PDT 24
Peak memory 196700 kb
Host smart-ddb9b0a9-beb7-47ce-a092-cdd620d475fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727627383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.727627383
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.2991176452
Short name T361
Test name
Test status
Simulation time 141874176 ps
CPU time 1.28 seconds
Started Mar 10 03:30:43 PM PDT 24
Finished Mar 10 03:30:44 PM PDT 24
Peak memory 195716 kb
Host smart-488f6ae3-f507-4ca0-abec-d13fb59964de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991176452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.2991176452
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1889475370
Short name T645
Test name
Test status
Simulation time 55068429618 ps
CPU time 218.52 seconds
Started Mar 10 03:30:48 PM PDT 24
Finished Mar 10 03:34:27 PM PDT 24
Peak memory 198328 kb
Host smart-d90ce6f6-cbe4-4391-8c9e-42e3267df7e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889475370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1889475370
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1544632307
Short name T201
Test name
Test status
Simulation time 80678097 ps
CPU time 0.59 seconds
Started Mar 10 03:30:53 PM PDT 24
Finished Mar 10 03:30:53 PM PDT 24
Peak memory 194100 kb
Host smart-7efd5c49-d113-40cb-a2a8-fccf173d04e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544632307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1544632307
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2581388003
Short name T610
Test name
Test status
Simulation time 43501331 ps
CPU time 0.78 seconds
Started Mar 10 03:30:49 PM PDT 24
Finished Mar 10 03:30:50 PM PDT 24
Peak memory 195488 kb
Host smart-ff3b6692-4d6e-4a5d-b8ff-15241870bc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581388003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2581388003
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.251337489
Short name T277
Test name
Test status
Simulation time 769106366 ps
CPU time 23.37 seconds
Started Mar 10 03:30:47 PM PDT 24
Finished Mar 10 03:31:10 PM PDT 24
Peak memory 196944 kb
Host smart-dfd5f071-dc77-4f5d-9a54-bc474570a716
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251337489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.251337489
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.1737411199
Short name T529
Test name
Test status
Simulation time 653550053 ps
CPU time 0.97 seconds
Started Mar 10 03:30:53 PM PDT 24
Finished Mar 10 03:30:54 PM PDT 24
Peak memory 197972 kb
Host smart-1e855ccf-c20c-47b9-8ecb-9cb61dd347fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737411199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.1737411199
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2189295162
Short name T340
Test name
Test status
Simulation time 39598753 ps
CPU time 1.22 seconds
Started Mar 10 03:30:48 PM PDT 24
Finished Mar 10 03:30:49 PM PDT 24
Peak memory 196256 kb
Host smart-265aeb46-32cb-465d-b7e8-9d048c248a39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189295162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2189295162
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.195367961
Short name T286
Test name
Test status
Simulation time 375521494 ps
CPU time 4.06 seconds
Started Mar 10 03:30:47 PM PDT 24
Finished Mar 10 03:30:51 PM PDT 24
Peak memory 198212 kb
Host smart-03f82792-056a-4c3a-83c5-d801f5c7c2de
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195367961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.gpio_intr_with_filter_rand_intr_event.195367961
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2109561410
Short name T375
Test name
Test status
Simulation time 223246416 ps
CPU time 3.54 seconds
Started Mar 10 03:30:48 PM PDT 24
Finished Mar 10 03:30:52 PM PDT 24
Peak memory 197220 kb
Host smart-58686b5b-fc6d-4329-896a-10596f0276c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109561410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2109561410
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3825254934
Short name T61
Test name
Test status
Simulation time 50275303 ps
CPU time 1.29 seconds
Started Mar 10 03:30:48 PM PDT 24
Finished Mar 10 03:30:49 PM PDT 24
Peak memory 196180 kb
Host smart-2b8d3a3b-b05e-45b8-8c72-d2b4a8e90f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825254934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3825254934
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.791585054
Short name T272
Test name
Test status
Simulation time 29301601 ps
CPU time 1.12 seconds
Started Mar 10 03:30:47 PM PDT 24
Finished Mar 10 03:30:49 PM PDT 24
Peak memory 196200 kb
Host smart-ac9df2ba-582d-4b61-a3be-50113518ecf0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791585054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.791585054
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2082573994
Short name T453
Test name
Test status
Simulation time 72974788 ps
CPU time 1.4 seconds
Started Mar 10 03:30:48 PM PDT 24
Finished Mar 10 03:30:50 PM PDT 24
Peak memory 198180 kb
Host smart-d5443ab2-2219-4ff9-b69d-5e93bdd849f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082573994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2082573994
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.977528435
Short name T493
Test name
Test status
Simulation time 32357078 ps
CPU time 1.09 seconds
Started Mar 10 03:30:47 PM PDT 24
Finished Mar 10 03:30:48 PM PDT 24
Peak memory 195880 kb
Host smart-03dc2ba6-83ce-4d9e-9eaf-9673d3a120f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977528435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.977528435
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.154079195
Short name T111
Test name
Test status
Simulation time 116173210 ps
CPU time 1.27 seconds
Started Mar 10 03:30:48 PM PDT 24
Finished Mar 10 03:30:49 PM PDT 24
Peak memory 197056 kb
Host smart-13b47fe3-4a39-4f4e-af83-80e9eb1b8af2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154079195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.154079195
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.491409832
Short name T619
Test name
Test status
Simulation time 12557939401 ps
CPU time 88.25 seconds
Started Mar 10 03:30:52 PM PDT 24
Finished Mar 10 03:32:21 PM PDT 24
Peak memory 198368 kb
Host smart-f233bd9f-89e1-4d8d-9345-aa60a6db6f01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491409832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.491409832
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1831723350
Short name T659
Test name
Test status
Simulation time 87297717466 ps
CPU time 1987.79 seconds
Started Mar 10 03:30:52 PM PDT 24
Finished Mar 10 04:04:01 PM PDT 24
Peak memory 198456 kb
Host smart-a50527d0-a101-4a9f-bb24-14a6b8db29df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1831723350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1831723350
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.4173704558
Short name T380
Test name
Test status
Simulation time 39642643 ps
CPU time 0.56 seconds
Started Mar 10 03:30:56 PM PDT 24
Finished Mar 10 03:30:57 PM PDT 24
Peak memory 194820 kb
Host smart-9f2dc43e-f6c6-431a-9704-2681a8ae82d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173704558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.4173704558
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1886664984
Short name T300
Test name
Test status
Simulation time 29208477 ps
CPU time 0.88 seconds
Started Mar 10 03:30:53 PM PDT 24
Finished Mar 10 03:30:54 PM PDT 24
Peak memory 195368 kb
Host smart-67fbc232-1720-4439-ad3a-6fd05dd73add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886664984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1886664984
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1125178639
Short name T310
Test name
Test status
Simulation time 163125955 ps
CPU time 8.34 seconds
Started Mar 10 03:30:56 PM PDT 24
Finished Mar 10 03:31:05 PM PDT 24
Peak memory 195712 kb
Host smart-7252f788-b6fc-4b8d-8ed0-b43955d9167f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125178639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1125178639
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3799474061
Short name T198
Test name
Test status
Simulation time 83248567 ps
CPU time 1.2 seconds
Started Mar 10 03:30:58 PM PDT 24
Finished Mar 10 03:31:00 PM PDT 24
Peak memory 198124 kb
Host smart-5705a0f6-3992-473e-bcec-47e7e39a00a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799474061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3799474061
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.3572844316
Short name T634
Test name
Test status
Simulation time 44203212 ps
CPU time 1.67 seconds
Started Mar 10 03:31:14 PM PDT 24
Finished Mar 10 03:31:16 PM PDT 24
Peak memory 196684 kb
Host smart-30f10fb5-6c92-445a-8857-df2760bd7365
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572844316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.3572844316
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.2078996110
Short name T485
Test name
Test status
Simulation time 515033181 ps
CPU time 1.74 seconds
Started Mar 10 03:30:57 PM PDT 24
Finished Mar 10 03:30:59 PM PDT 24
Peak memory 197036 kb
Host smart-44458bcf-7d1a-4e50-89df-47293b270aeb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078996110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.2078996110
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2567447022
Short name T214
Test name
Test status
Simulation time 238020687 ps
CPU time 1.06 seconds
Started Mar 10 03:30:56 PM PDT 24
Finished Mar 10 03:30:58 PM PDT 24
Peak memory 196304 kb
Host smart-1cda6a8c-e0d8-4337-8e9d-168fffc0c8e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567447022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2567447022
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1838444646
Short name T346
Test name
Test status
Simulation time 90573613 ps
CPU time 0.78 seconds
Started Mar 10 03:30:51 PM PDT 24
Finished Mar 10 03:30:52 PM PDT 24
Peak memory 196352 kb
Host smart-a7d4e52e-66e0-4e7b-b257-fd386beb5feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838444646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1838444646
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.4036002460
Short name T202
Test name
Test status
Simulation time 223004392 ps
CPU time 1.25 seconds
Started Mar 10 03:30:53 PM PDT 24
Finished Mar 10 03:30:54 PM PDT 24
Peak memory 196332 kb
Host smart-6487595f-02a9-4a9b-953c-609e2541e308
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036002460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.4036002460
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1957316197
Short name T48
Test name
Test status
Simulation time 803105712 ps
CPU time 4.15 seconds
Started Mar 10 03:30:58 PM PDT 24
Finished Mar 10 03:31:02 PM PDT 24
Peak memory 198108 kb
Host smart-9ccfa62e-c32f-4318-8583-f1c904e4802b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957316197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1957316197
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1692057624
Short name T595
Test name
Test status
Simulation time 385515982 ps
CPU time 1.24 seconds
Started Mar 10 03:30:54 PM PDT 24
Finished Mar 10 03:30:55 PM PDT 24
Peak memory 196700 kb
Host smart-42646bf9-d4cb-4e1a-8165-ddf0aa18afaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692057624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1692057624
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.3450407264
Short name T445
Test name
Test status
Simulation time 48280063 ps
CPU time 1.29 seconds
Started Mar 10 03:30:52 PM PDT 24
Finished Mar 10 03:30:54 PM PDT 24
Peak memory 196772 kb
Host smart-c9cfddf1-42f0-40b1-a778-d7c6fae90040
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450407264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.3450407264
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2806174415
Short name T663
Test name
Test status
Simulation time 1467838942 ps
CPU time 37.64 seconds
Started Mar 10 03:30:57 PM PDT 24
Finished Mar 10 03:31:35 PM PDT 24
Peak memory 198136 kb
Host smart-0d8848c6-f6d4-4a43-b4d4-3336c4d6c9a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806174415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2806174415
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2499198222
Short name T429
Test name
Test status
Simulation time 172705957783 ps
CPU time 876.31 seconds
Started Mar 10 03:30:56 PM PDT 24
Finished Mar 10 03:45:33 PM PDT 24
Peak memory 198520 kb
Host smart-5db3bfbb-1578-4e54-aed3-6acdbad6fd0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2499198222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2499198222
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.2261004550
Short name T716
Test name
Test status
Simulation time 14715609 ps
CPU time 0.61 seconds
Started Mar 10 03:31:06 PM PDT 24
Finished Mar 10 03:31:07 PM PDT 24
Peak memory 194372 kb
Host smart-513adda6-c7de-4b16-add9-f4bd6d37ca07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261004550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.2261004550
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2469783549
Short name T433
Test name
Test status
Simulation time 80743884 ps
CPU time 1.02 seconds
Started Mar 10 03:31:01 PM PDT 24
Finished Mar 10 03:31:02 PM PDT 24
Peak memory 196788 kb
Host smart-596f653a-69a9-41d6-b7a4-6265f86b6b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469783549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2469783549
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.423260944
Short name T704
Test name
Test status
Simulation time 1711334851 ps
CPU time 23.88 seconds
Started Mar 10 03:31:01 PM PDT 24
Finished Mar 10 03:31:25 PM PDT 24
Peak memory 197048 kb
Host smart-d9415929-015d-4708-b059-d63c03cd43f2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423260944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.423260944
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1667152092
Short name T670
Test name
Test status
Simulation time 29152324 ps
CPU time 0.76 seconds
Started Mar 10 03:31:02 PM PDT 24
Finished Mar 10 03:31:03 PM PDT 24
Peak memory 194832 kb
Host smart-403227ae-b357-46d6-9b12-ad928b9c37da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667152092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1667152092
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1063797484
Short name T187
Test name
Test status
Simulation time 29572745 ps
CPU time 0.87 seconds
Started Mar 10 03:31:01 PM PDT 24
Finished Mar 10 03:31:02 PM PDT 24
Peak memory 195652 kb
Host smart-973858fc-4bbc-4b97-bd73-ff66503eaf2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063797484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1063797484
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.884965683
Short name T512
Test name
Test status
Simulation time 111099003 ps
CPU time 1.5 seconds
Started Mar 10 03:31:12 PM PDT 24
Finished Mar 10 03:31:14 PM PDT 24
Peak memory 196564 kb
Host smart-1ec9531f-c3fe-434f-b541-f473f7de838b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884965683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.884965683
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.526456792
Short name T486
Test name
Test status
Simulation time 261878629 ps
CPU time 3.06 seconds
Started Mar 10 03:31:04 PM PDT 24
Finished Mar 10 03:31:07 PM PDT 24
Peak memory 197396 kb
Host smart-fb9466a1-8362-40f4-8890-040ae2fe0219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526456792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
526456792
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.1032370564
Short name T197
Test name
Test status
Simulation time 120734093 ps
CPU time 0.99 seconds
Started Mar 10 03:31:02 PM PDT 24
Finished Mar 10 03:31:03 PM PDT 24
Peak memory 196152 kb
Host smart-e8465a12-ec98-44e2-b0ff-fc66d38ef786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032370564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.1032370564
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2467828725
Short name T163
Test name
Test status
Simulation time 25599630 ps
CPU time 0.98 seconds
Started Mar 10 03:31:02 PM PDT 24
Finished Mar 10 03:31:03 PM PDT 24
Peak memory 196212 kb
Host smart-1d2f0ae1-32d7-4b86-a878-c0a6a67fde83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467828725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2467828725
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3737498793
Short name T176
Test name
Test status
Simulation time 482249917 ps
CPU time 4.48 seconds
Started Mar 10 03:31:03 PM PDT 24
Finished Mar 10 03:31:07 PM PDT 24
Peak memory 198132 kb
Host smart-3d82d1a1-ea3f-4ed6-8a7e-b3e29751f2be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737498793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3737498793
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.1998543372
Short name T68
Test name
Test status
Simulation time 148202912 ps
CPU time 0.97 seconds
Started Mar 10 03:31:02 PM PDT 24
Finished Mar 10 03:31:03 PM PDT 24
Peak memory 196432 kb
Host smart-ddb1b6f3-1caa-4711-a5c2-3767115be283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998543372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.1998543372
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.777082164
Short name T244
Test name
Test status
Simulation time 51659527 ps
CPU time 1.19 seconds
Started Mar 10 03:31:02 PM PDT 24
Finished Mar 10 03:31:03 PM PDT 24
Peak memory 195912 kb
Host smart-3656f12d-95fb-4e25-895d-ee11c548570c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777082164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.777082164
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3496095776
Short name T5
Test name
Test status
Simulation time 15169061030 ps
CPU time 184.86 seconds
Started Mar 10 03:31:03 PM PDT 24
Finished Mar 10 03:34:08 PM PDT 24
Peak memory 198324 kb
Host smart-698bfb46-9ce2-4701-b0b2-9b94c29d3426
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496095776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3496095776
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.491308831
Short name T660
Test name
Test status
Simulation time 89211227817 ps
CPU time 628.47 seconds
Started Mar 10 03:31:04 PM PDT 24
Finished Mar 10 03:41:32 PM PDT 24
Peak memory 198508 kb
Host smart-d65cd6d7-4e8e-4a8f-a64c-0c8eb92a0148
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=491308831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.491308831
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.2244930803
Short name T49
Test name
Test status
Simulation time 21990655 ps
CPU time 0.57 seconds
Started Mar 10 03:25:44 PM PDT 24
Finished Mar 10 03:25:45 PM PDT 24
Peak memory 194032 kb
Host smart-de382cbd-223b-45ec-bd4b-1914a8eebef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244930803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.2244930803
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3493304303
Short name T205
Test name
Test status
Simulation time 13410637 ps
CPU time 0.66 seconds
Started Mar 10 03:25:33 PM PDT 24
Finished Mar 10 03:25:34 PM PDT 24
Peak memory 194004 kb
Host smart-f31d3a14-2b49-4e0e-bf86-cc76805b67ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493304303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3493304303
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2202104856
Short name T379
Test name
Test status
Simulation time 168844216 ps
CPU time 9.76 seconds
Started Mar 10 03:25:40 PM PDT 24
Finished Mar 10 03:25:50 PM PDT 24
Peak memory 196960 kb
Host smart-b000bda0-8f08-4462-a267-2d385476be25
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202104856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2202104856
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1832252742
Short name T161
Test name
Test status
Simulation time 58401249 ps
CPU time 1.06 seconds
Started Mar 10 03:25:42 PM PDT 24
Finished Mar 10 03:25:44 PM PDT 24
Peak memory 197228 kb
Host smart-704dda2f-c56a-49ef-9703-4fce7339bd71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832252742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1832252742
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.4040072450
Short name T642
Test name
Test status
Simulation time 123023959 ps
CPU time 0.9 seconds
Started Mar 10 03:25:37 PM PDT 24
Finished Mar 10 03:25:39 PM PDT 24
Peak memory 196336 kb
Host smart-6ee38783-7d28-4e39-92dd-04b3fb822c35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040072450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.4040072450
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2670280564
Short name T582
Test name
Test status
Simulation time 355132405 ps
CPU time 2.5 seconds
Started Mar 10 03:25:34 PM PDT 24
Finished Mar 10 03:25:37 PM PDT 24
Peak memory 197288 kb
Host smart-46a740b8-e5c5-49f0-ad1c-32838f311107
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670280564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2670280564
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3226094542
Short name T520
Test name
Test status
Simulation time 24833045 ps
CPU time 1.06 seconds
Started Mar 10 03:25:48 PM PDT 24
Finished Mar 10 03:25:50 PM PDT 24
Peak memory 196820 kb
Host smart-68584b18-4161-4d00-925e-0d79201c5d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226094542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3226094542
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1438508788
Short name T567
Test name
Test status
Simulation time 27674486 ps
CPU time 0.83 seconds
Started Mar 10 03:25:35 PM PDT 24
Finished Mar 10 03:25:36 PM PDT 24
Peak memory 195560 kb
Host smart-8b7a0ebd-6a87-4648-bac9-68107b7c8987
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438508788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1438508788
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3222238439
Short name T699
Test name
Test status
Simulation time 198179300 ps
CPU time 3.12 seconds
Started Mar 10 03:25:41 PM PDT 24
Finished Mar 10 03:25:44 PM PDT 24
Peak memory 198160 kb
Host smart-732f91e2-892a-4fd1-8bda-ab008e9e8212
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222238439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3222238439
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2634943638
Short name T661
Test name
Test status
Simulation time 82976460 ps
CPU time 1.02 seconds
Started Mar 10 03:25:34 PM PDT 24
Finished Mar 10 03:25:36 PM PDT 24
Peak memory 196324 kb
Host smart-291cfd29-9935-4fe7-b287-920291c0ff2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634943638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2634943638
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1521324995
Short name T189
Test name
Test status
Simulation time 159123732 ps
CPU time 1.11 seconds
Started Mar 10 03:25:33 PM PDT 24
Finished Mar 10 03:25:34 PM PDT 24
Peak memory 196596 kb
Host smart-9b7d6fc0-1c81-4b6b-a458-0bdf3c2aad3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521324995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1521324995
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3931532345
Short name T499
Test name
Test status
Simulation time 1916776932 ps
CPU time 27.42 seconds
Started Mar 10 03:25:40 PM PDT 24
Finished Mar 10 03:26:08 PM PDT 24
Peak memory 197892 kb
Host smart-9479cdcc-989e-474f-b396-dcbc10652bf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931532345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3931532345
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.962397558
Short name T600
Test name
Test status
Simulation time 1179651279294 ps
CPU time 2913.46 seconds
Started Mar 10 03:25:40 PM PDT 24
Finished Mar 10 04:14:14 PM PDT 24
Peak memory 198548 kb
Host smart-2ebd3ee6-5747-4445-8667-b484ca87f5d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=962397558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.962397558
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2455321380
Short name T174
Test name
Test status
Simulation time 33938339 ps
CPU time 0.6 seconds
Started Mar 10 03:26:24 PM PDT 24
Finished Mar 10 03:26:25 PM PDT 24
Peak memory 194108 kb
Host smart-04c22731-bda9-4c4c-ae08-47ddb47de591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455321380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2455321380
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.1288771348
Short name T579
Test name
Test status
Simulation time 44768968 ps
CPU time 0.8 seconds
Started Mar 10 03:26:13 PM PDT 24
Finished Mar 10 03:26:14 PM PDT 24
Peak memory 195376 kb
Host smart-3f6e723d-e3ed-4c80-b608-8cb1d3bd62d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288771348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.1288771348
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2418357415
Short name T426
Test name
Test status
Simulation time 505243956 ps
CPU time 16.06 seconds
Started Mar 10 03:26:18 PM PDT 24
Finished Mar 10 03:26:34 PM PDT 24
Peak memory 195728 kb
Host smart-515c0f42-7539-4353-94d9-1158a6f5efdf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418357415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2418357415
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.243977825
Short name T686
Test name
Test status
Simulation time 147109320 ps
CPU time 1.07 seconds
Started Mar 10 03:26:18 PM PDT 24
Finished Mar 10 03:26:20 PM PDT 24
Peak memory 196736 kb
Host smart-47cb6447-c307-4022-8e77-3316cf474875
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243977825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.243977825
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3146738159
Short name T222
Test name
Test status
Simulation time 78310970 ps
CPU time 1.54 seconds
Started Mar 10 03:26:17 PM PDT 24
Finished Mar 10 03:26:19 PM PDT 24
Peak memory 197024 kb
Host smart-825bd92b-f7b1-4734-8d33-cd65a84d0b94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146738159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3146738159
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1554711015
Short name T613
Test name
Test status
Simulation time 47356372 ps
CPU time 1.35 seconds
Started Mar 10 03:25:54 PM PDT 24
Finished Mar 10 03:25:56 PM PDT 24
Peak memory 198016 kb
Host smart-fea3fda2-1476-4bf3-aa16-ee76d5d14383
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554711015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1554711015
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1491841506
Short name T269
Test name
Test status
Simulation time 71785282 ps
CPU time 1.4 seconds
Started Mar 10 03:26:12 PM PDT 24
Finished Mar 10 03:26:13 PM PDT 24
Peak memory 196344 kb
Host smart-87a08289-4f5a-449c-9999-153c4b83c48d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491841506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1491841506
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.1914408535
Short name T409
Test name
Test status
Simulation time 33822026 ps
CPU time 1.28 seconds
Started Mar 10 03:25:46 PM PDT 24
Finished Mar 10 03:25:47 PM PDT 24
Peak memory 198164 kb
Host smart-6e0584be-2aaf-4107-b024-a59b1d7be986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914408535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.1914408535
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.707930915
Short name T484
Test name
Test status
Simulation time 56600398 ps
CPU time 1.1 seconds
Started Mar 10 03:25:48 PM PDT 24
Finished Mar 10 03:25:49 PM PDT 24
Peak memory 196184 kb
Host smart-d5edf903-5153-47c4-8f98-e9aac5e47fca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707930915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.707930915
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.55704485
Short name T591
Test name
Test status
Simulation time 131337092 ps
CPU time 4.34 seconds
Started Mar 10 03:26:19 PM PDT 24
Finished Mar 10 03:26:24 PM PDT 24
Peak memory 198140 kb
Host smart-693f7e64-abec-4c4e-8de6-f264c551696a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55704485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rando
m_long_reg_writes_reg_reads.55704485
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2630111996
Short name T160
Test name
Test status
Simulation time 36036842 ps
CPU time 1.14 seconds
Started Mar 10 03:25:44 PM PDT 24
Finished Mar 10 03:25:45 PM PDT 24
Peak memory 195716 kb
Host smart-9d277ee6-77af-46fb-bb51-361a56413894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630111996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2630111996
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.2380856181
Short name T401
Test name
Test status
Simulation time 46450529 ps
CPU time 1.4 seconds
Started Mar 10 03:25:46 PM PDT 24
Finished Mar 10 03:25:47 PM PDT 24
Peak memory 196884 kb
Host smart-5d6db909-84cd-4710-af87-23378e2f68b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380856181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.2380856181
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1697664027
Short name T674
Test name
Test status
Simulation time 66415572458 ps
CPU time 174.02 seconds
Started Mar 10 03:26:18 PM PDT 24
Finished Mar 10 03:29:12 PM PDT 24
Peak memory 198404 kb
Host smart-4974663d-1b2b-4573-b835-3161c05b1857
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697664027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1697664027
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1267292602
Short name T583
Test name
Test status
Simulation time 30980720 ps
CPU time 0.61 seconds
Started Mar 10 03:26:29 PM PDT 24
Finished Mar 10 03:26:30 PM PDT 24
Peak memory 194128 kb
Host smart-5b2e204a-b944-4acd-acef-019ebac91062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267292602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1267292602
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1814064974
Short name T538
Test name
Test status
Simulation time 35539762 ps
CPU time 0.94 seconds
Started Mar 10 03:26:28 PM PDT 24
Finished Mar 10 03:26:29 PM PDT 24
Peak memory 196096 kb
Host smart-a49f18a2-8e02-4d2d-81b5-3f0b067cf0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814064974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1814064974
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1975505504
Short name T372
Test name
Test status
Simulation time 1839843219 ps
CPU time 10.04 seconds
Started Mar 10 03:27:04 PM PDT 24
Finished Mar 10 03:27:14 PM PDT 24
Peak memory 196564 kb
Host smart-8f335766-d0ec-48c4-9116-2976cf34fac8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975505504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1975505504
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.997845491
Short name T141
Test name
Test status
Simulation time 128520064 ps
CPU time 1.02 seconds
Started Mar 10 03:26:29 PM PDT 24
Finished Mar 10 03:26:30 PM PDT 24
Peak memory 198016 kb
Host smart-2fa54d93-69fa-401a-9010-a1aa191c9aaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997845491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.997845491
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4238352046
Short name T419
Test name
Test status
Simulation time 51108662 ps
CPU time 1.69 seconds
Started Mar 10 03:27:04 PM PDT 24
Finished Mar 10 03:27:06 PM PDT 24
Peak memory 197084 kb
Host smart-0c8b6bec-fdf9-4ca1-ad5c-eee5d2d6066b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238352046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4238352046
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3309789217
Short name T255
Test name
Test status
Simulation time 46503254 ps
CPU time 1.34 seconds
Started Mar 10 03:26:19 PM PDT 24
Finished Mar 10 03:26:20 PM PDT 24
Peak memory 197608 kb
Host smart-d8c89cc9-da9c-46d4-9ddf-7b913de0f639
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309789217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3309789217
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.3575895400
Short name T633
Test name
Test status
Simulation time 34343883 ps
CPU time 1.1 seconds
Started Mar 10 03:26:18 PM PDT 24
Finished Mar 10 03:26:20 PM PDT 24
Peak memory 195552 kb
Host smart-12dfa9a6-3d6a-4f39-b6cb-33c87e49c51c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575895400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
3575895400
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3019247507
Short name T593
Test name
Test status
Simulation time 38229622 ps
CPU time 1.02 seconds
Started Mar 10 03:26:23 PM PDT 24
Finished Mar 10 03:26:24 PM PDT 24
Peak memory 196156 kb
Host smart-bfd1905f-c55f-4509-9b5a-9ab728c2aa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019247507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3019247507
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1191708903
Short name T475
Test name
Test status
Simulation time 140018663 ps
CPU time 1.12 seconds
Started Mar 10 03:26:19 PM PDT 24
Finished Mar 10 03:26:20 PM PDT 24
Peak memory 196216 kb
Host smart-c1385304-ebd2-41fc-983a-f9b3502d1685
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191708903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1191708903
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3319283245
Short name T581
Test name
Test status
Simulation time 1368821570 ps
CPU time 6.08 seconds
Started Mar 10 03:26:22 PM PDT 24
Finished Mar 10 03:26:28 PM PDT 24
Peak memory 198096 kb
Host smart-cf2cc7a3-cacf-49f2-b912-1005465beaa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319283245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3319283245
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3701949454
Short name T543
Test name
Test status
Simulation time 125468046 ps
CPU time 1.02 seconds
Started Mar 10 03:26:23 PM PDT 24
Finished Mar 10 03:26:25 PM PDT 24
Peak memory 195916 kb
Host smart-0c8a21b3-5c9b-430a-bbe9-e198b4f53f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701949454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3701949454
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3530894279
Short name T374
Test name
Test status
Simulation time 95760699 ps
CPU time 1.53 seconds
Started Mar 10 03:26:21 PM PDT 24
Finished Mar 10 03:26:22 PM PDT 24
Peak memory 196788 kb
Host smart-c81df4b7-18ed-46f1-a36f-fac62d331b54
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530894279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3530894279
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.3245097022
Short name T41
Test name
Test status
Simulation time 7407051532 ps
CPU time 28.73 seconds
Started Mar 10 03:26:27 PM PDT 24
Finished Mar 10 03:26:56 PM PDT 24
Peak memory 198388 kb
Host smart-9caf2a46-2483-47fc-9448-6553712bfc8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245097022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.3245097022
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.1358774943
Short name T480
Test name
Test status
Simulation time 108274620170 ps
CPU time 1660.84 seconds
Started Mar 10 03:26:27 PM PDT 24
Finished Mar 10 03:54:08 PM PDT 24
Peak memory 198444 kb
Host smart-e0d33bba-32a0-4028-bf4c-6b783ae72c22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1358774943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.1358774943
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2449969818
Short name T193
Test name
Test status
Simulation time 43159670 ps
CPU time 0.67 seconds
Started Mar 10 03:26:22 PM PDT 24
Finished Mar 10 03:26:23 PM PDT 24
Peak memory 194804 kb
Host smart-759b52fb-17b6-4ee6-aa06-f47df7442b26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449969818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2449969818
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.3309681744
Short name T625
Test name
Test status
Simulation time 221634898 ps
CPU time 1.04 seconds
Started Mar 10 03:26:22 PM PDT 24
Finished Mar 10 03:26:23 PM PDT 24
Peak memory 196036 kb
Host smart-d12905c1-996e-4dc3-a0d4-e6c8a6969496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309681744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.3309681744
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2126667944
Short name T208
Test name
Test status
Simulation time 2900193666 ps
CPU time 26.65 seconds
Started Mar 10 03:26:21 PM PDT 24
Finished Mar 10 03:26:48 PM PDT 24
Peak memory 198256 kb
Host smart-2639d48f-8ecf-4b06-8a5e-6dfce645fdf4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126667944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2126667944
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1605755408
Short name T227
Test name
Test status
Simulation time 107618278 ps
CPU time 0.69 seconds
Started Mar 10 03:26:21 PM PDT 24
Finished Mar 10 03:26:22 PM PDT 24
Peak memory 194752 kb
Host smart-707ea7d3-b544-4c00-a9a4-f9f5554f8328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605755408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1605755408
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.892296398
Short name T150
Test name
Test status
Simulation time 60898982 ps
CPU time 1.14 seconds
Started Mar 10 03:26:40 PM PDT 24
Finished Mar 10 03:26:41 PM PDT 24
Peak memory 195868 kb
Host smart-e5c87e1f-27d1-4190-aa24-88dadb3d47c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892296398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.892296398
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1860969103
Short name T684
Test name
Test status
Simulation time 170732323 ps
CPU time 3.93 seconds
Started Mar 10 03:26:21 PM PDT 24
Finished Mar 10 03:26:25 PM PDT 24
Peak memory 196624 kb
Host smart-6043b6aa-2542-4dfe-9d19-da5fc37bb0f3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860969103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1860969103
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.133655566
Short name T124
Test name
Test status
Simulation time 46466655 ps
CPU time 1.7 seconds
Started Mar 10 03:26:27 PM PDT 24
Finished Mar 10 03:26:29 PM PDT 24
Peak memory 196232 kb
Host smart-7ae3997d-be3a-49ee-97b8-843a19701421
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133655566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.133655566
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.516595301
Short name T106
Test name
Test status
Simulation time 25040616 ps
CPU time 1 seconds
Started Mar 10 03:26:27 PM PDT 24
Finished Mar 10 03:26:28 PM PDT 24
Peak memory 196120 kb
Host smart-bdbd0952-22de-4a4a-a30b-9e4fe2ac2976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516595301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.516595301
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.916934496
Short name T405
Test name
Test status
Simulation time 118366834 ps
CPU time 1.05 seconds
Started Mar 10 03:26:24 PM PDT 24
Finished Mar 10 03:26:25 PM PDT 24
Peak memory 196180 kb
Host smart-cfc7f792-a674-4fe1-b52e-1e57735f29fe
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916934496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.916934496
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3404007844
Short name T715
Test name
Test status
Simulation time 966882234 ps
CPU time 1.63 seconds
Started Mar 10 03:26:22 PM PDT 24
Finished Mar 10 03:26:24 PM PDT 24
Peak memory 198108 kb
Host smart-256fb1ad-91f3-4cf2-87eb-4db5fc9855dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404007844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3404007844
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.3429219334
Short name T711
Test name
Test status
Simulation time 210945141 ps
CPU time 1.24 seconds
Started Mar 10 03:26:21 PM PDT 24
Finished Mar 10 03:26:22 PM PDT 24
Peak memory 195648 kb
Host smart-21c7061a-aa98-46bd-b26c-e3ece311e316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429219334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.3429219334
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3489282724
Short name T466
Test name
Test status
Simulation time 291053155 ps
CPU time 1.28 seconds
Started Mar 10 03:26:21 PM PDT 24
Finished Mar 10 03:26:22 PM PDT 24
Peak memory 195708 kb
Host smart-b5edad14-ba4e-4ba7-b183-267d5503abd7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489282724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3489282724
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3216135770
Short name T279
Test name
Test status
Simulation time 7994909306 ps
CPU time 27.39 seconds
Started Mar 10 03:26:23 PM PDT 24
Finished Mar 10 03:26:51 PM PDT 24
Peak memory 198336 kb
Host smart-890f56d9-322f-470a-9a91-8b38625f0392
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216135770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3216135770
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.2093931326
Short name T121
Test name
Test status
Simulation time 129078547 ps
CPU time 0.61 seconds
Started Mar 10 03:26:26 PM PDT 24
Finished Mar 10 03:26:27 PM PDT 24
Peak memory 194324 kb
Host smart-3bb460c2-7225-4033-974c-f0d041805418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093931326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.2093931326
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3850944945
Short name T313
Test name
Test status
Simulation time 117389172 ps
CPU time 0.73 seconds
Started Mar 10 03:26:30 PM PDT 24
Finished Mar 10 03:26:30 PM PDT 24
Peak memory 194240 kb
Host smart-5f9fcff6-7624-4cb0-8ac9-709200e8decc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850944945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3850944945
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3562684910
Short name T436
Test name
Test status
Simulation time 990316602 ps
CPU time 22.71 seconds
Started Mar 10 03:26:31 PM PDT 24
Finished Mar 10 03:26:54 PM PDT 24
Peak memory 196872 kb
Host smart-451ed4f7-e3a5-4db2-b001-96fea5c6e79d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562684910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3562684910
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3053647955
Short name T682
Test name
Test status
Simulation time 187734275 ps
CPU time 1.16 seconds
Started Mar 10 03:26:25 PM PDT 24
Finished Mar 10 03:26:26 PM PDT 24
Peak memory 196512 kb
Host smart-7965488c-2b57-419e-a34b-8c186fbbe001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053647955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3053647955
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1949572992
Short name T221
Test name
Test status
Simulation time 179743062 ps
CPU time 1.57 seconds
Started Mar 10 03:26:27 PM PDT 24
Finished Mar 10 03:26:28 PM PDT 24
Peak memory 196760 kb
Host smart-030d7393-3fd6-4323-93f9-959e086a2e58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949572992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1949572992
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.773075809
Short name T603
Test name
Test status
Simulation time 188142736 ps
CPU time 4.05 seconds
Started Mar 10 03:26:31 PM PDT 24
Finished Mar 10 03:26:36 PM PDT 24
Peak memory 198200 kb
Host smart-62296504-e2d1-469b-9207-7195d0c49aae
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773075809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.773075809
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1674097905
Short name T167
Test name
Test status
Simulation time 662045257 ps
CPU time 3.56 seconds
Started Mar 10 03:26:36 PM PDT 24
Finished Mar 10 03:26:40 PM PDT 24
Peak memory 197012 kb
Host smart-af90e2f1-23ac-4f57-b76a-659a0c36396a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674097905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1674097905
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.3343744489
Short name T576
Test name
Test status
Simulation time 118533563 ps
CPU time 0.91 seconds
Started Mar 10 03:26:23 PM PDT 24
Finished Mar 10 03:26:24 PM PDT 24
Peak memory 197220 kb
Host smart-5c3567f9-d2c6-4269-b112-ef80775a271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343744489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.3343744489
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2941193567
Short name T507
Test name
Test status
Simulation time 270224346 ps
CPU time 0.8 seconds
Started Mar 10 03:26:22 PM PDT 24
Finished Mar 10 03:26:23 PM PDT 24
Peak memory 196172 kb
Host smart-6eeaf83d-a59a-45e0-b32b-68468b1c447e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941193567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2941193567
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.1543573322
Short name T601
Test name
Test status
Simulation time 712974659 ps
CPU time 4.97 seconds
Started Mar 10 03:26:27 PM PDT 24
Finished Mar 10 03:26:32 PM PDT 24
Peak memory 198156 kb
Host smart-a07c6ec0-fddc-4262-93c8-e924b0fa7af8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543573322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.1543573322
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.1892367189
Short name T266
Test name
Test status
Simulation time 134844738 ps
CPU time 1.27 seconds
Started Mar 10 03:26:29 PM PDT 24
Finished Mar 10 03:26:31 PM PDT 24
Peak memory 195688 kb
Host smart-97650c3d-8ec7-48ab-a9e3-8547029dfa0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892367189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.1892367189
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3084917733
Short name T469
Test name
Test status
Simulation time 260324020 ps
CPU time 1.46 seconds
Started Mar 10 03:26:25 PM PDT 24
Finished Mar 10 03:26:26 PM PDT 24
Peak memory 196568 kb
Host smart-1160eeac-53a7-4b66-927b-d359fdb0f6bb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084917733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3084917733
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.560105000
Short name T9
Test name
Test status
Simulation time 7803813020 ps
CPU time 101.4 seconds
Started Mar 10 03:26:25 PM PDT 24
Finished Mar 10 03:28:06 PM PDT 24
Peak memory 198344 kb
Host smart-5616bc2a-c832-46d2-8d44-b3f5b6e05e61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560105000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.560105000
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2086037693
Short name T929
Test name
Test status
Simulation time 157675820 ps
CPU time 1.38 seconds
Started Mar 10 01:16:33 PM PDT 24
Finished Mar 10 01:16:34 PM PDT 24
Peak memory 196880 kb
Host smart-7229ead3-a001-49f2-a748-0a0bf92ef171
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2086037693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2086037693
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1720915928
Short name T861
Test name
Test status
Simulation time 63284576 ps
CPU time 1.33 seconds
Started Mar 10 01:16:33 PM PDT 24
Finished Mar 10 01:16:34 PM PDT 24
Peak memory 196700 kb
Host smart-900058a9-c4ad-4947-b189-a7bd24c34488
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720915928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1720915928
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2717715699
Short name T931
Test name
Test status
Simulation time 27910611 ps
CPU time 0.9 seconds
Started Mar 10 01:16:37 PM PDT 24
Finished Mar 10 01:16:38 PM PDT 24
Peak memory 196404 kb
Host smart-dbb71470-961b-417f-9082-78fab6099eef
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2717715699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2717715699
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1179013012
Short name T889
Test name
Test status
Simulation time 154254385 ps
CPU time 1.1 seconds
Started Mar 10 01:16:38 PM PDT 24
Finished Mar 10 01:16:39 PM PDT 24
Peak memory 196908 kb
Host smart-1fdbea3d-e6bc-43b3-8761-9e9721b7b5a3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179013012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1179013012
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.2433576787
Short name T888
Test name
Test status
Simulation time 158981441 ps
CPU time 0.9 seconds
Started Mar 10 01:16:56 PM PDT 24
Finished Mar 10 01:16:58 PM PDT 24
Peak memory 197336 kb
Host smart-84740ebf-6b2a-4626-a5b0-0e58e1b0ff85
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2433576787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.2433576787
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.658085037
Short name T869
Test name
Test status
Simulation time 418912690 ps
CPU time 1.1 seconds
Started Mar 10 01:16:55 PM PDT 24
Finished Mar 10 01:16:57 PM PDT 24
Peak memory 195776 kb
Host smart-ac226f30-9950-46f4-8f39-95b69ccad28a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658085037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.658085037
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2814863655
Short name T851
Test name
Test status
Simulation time 22996216 ps
CPU time 0.75 seconds
Started Mar 10 01:16:56 PM PDT 24
Finished Mar 10 01:16:58 PM PDT 24
Peak memory 195508 kb
Host smart-2932ebe5-f0dd-42b4-ac54-074feb80ef50
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2814863655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2814863655
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2635918932
Short name T878
Test name
Test status
Simulation time 114139840 ps
CPU time 1.18 seconds
Started Mar 10 01:17:01 PM PDT 24
Finished Mar 10 01:17:03 PM PDT 24
Peak memory 196648 kb
Host smart-3fbf8c53-02ee-4f23-a9cf-3bc71994e50b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635918932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2635918932
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3029904931
Short name T856
Test name
Test status
Simulation time 54886622 ps
CPU time 1 seconds
Started Mar 10 01:17:05 PM PDT 24
Finished Mar 10 01:17:06 PM PDT 24
Peak memory 196764 kb
Host smart-dbfc610e-2b9f-46c2-91ac-ad15707747ff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3029904931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3029904931
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2833159212
Short name T947
Test name
Test status
Simulation time 87098505 ps
CPU time 1.3 seconds
Started Mar 10 01:17:06 PM PDT 24
Finished Mar 10 01:17:07 PM PDT 24
Peak memory 196928 kb
Host smart-f161f493-fba2-4998-90ca-40031d66cc10
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833159212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2833159212
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.724251401
Short name T855
Test name
Test status
Simulation time 140766621 ps
CPU time 1.29 seconds
Started Mar 10 01:17:08 PM PDT 24
Finished Mar 10 01:17:10 PM PDT 24
Peak memory 196640 kb
Host smart-41cb42b3-c8de-4b0c-8285-657709c94ff6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=724251401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.724251401
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1844826033
Short name T913
Test name
Test status
Simulation time 151610090 ps
CPU time 0.92 seconds
Started Mar 10 01:17:06 PM PDT 24
Finished Mar 10 01:17:07 PM PDT 24
Peak memory 196488 kb
Host smart-7e944d4a-2975-452d-9f92-6235759d4529
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844826033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1844826033
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.287212733
Short name T922
Test name
Test status
Simulation time 61827530 ps
CPU time 0.69 seconds
Started Mar 10 01:17:08 PM PDT 24
Finished Mar 10 01:17:09 PM PDT 24
Peak memory 194336 kb
Host smart-83d68013-7679-4fa5-b0e4-a1c1cc4228a4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=287212733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.287212733
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3043658198
Short name T942
Test name
Test status
Simulation time 177400950 ps
CPU time 1.3 seconds
Started Mar 10 01:17:07 PM PDT 24
Finished Mar 10 01:17:09 PM PDT 24
Peak memory 197064 kb
Host smart-0a3fe5cd-8753-4dae-b108-feb706791ee5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043658198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3043658198
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.1055666460
Short name T893
Test name
Test status
Simulation time 169389266 ps
CPU time 1.35 seconds
Started Mar 10 01:17:11 PM PDT 24
Finished Mar 10 01:17:13 PM PDT 24
Peak memory 196704 kb
Host smart-2a5e77a3-5bab-45a9-bc07-73ab2ffca6ad
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1055666460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.1055666460
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.26502410
Short name T905
Test name
Test status
Simulation time 720874060 ps
CPU time 1.25 seconds
Started Mar 10 01:17:09 PM PDT 24
Finished Mar 10 01:17:10 PM PDT 24
Peak memory 196724 kb
Host smart-e737227c-f5c3-4ba2-afb0-3ba0602009d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26502410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.26502410
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.4185065057
Short name T943
Test name
Test status
Simulation time 35734537 ps
CPU time 0.9 seconds
Started Mar 10 01:17:09 PM PDT 24
Finished Mar 10 01:17:10 PM PDT 24
Peak memory 197168 kb
Host smart-94e57e74-acfd-42b4-991b-42ac1d867469
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4185065057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.4185065057
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3203072674
Short name T911
Test name
Test status
Simulation time 173840684 ps
CPU time 1.34 seconds
Started Mar 10 01:17:10 PM PDT 24
Finished Mar 10 01:17:12 PM PDT 24
Peak memory 198056 kb
Host smart-ca03a90f-3f7b-4c95-9548-792cbc0d0293
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203072674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3203072674
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.4266820855
Short name T858
Test name
Test status
Simulation time 116366693 ps
CPU time 0.94 seconds
Started Mar 10 01:17:09 PM PDT 24
Finished Mar 10 01:17:10 PM PDT 24
Peak memory 195440 kb
Host smart-c73eab21-d0dd-4f0e-b8c6-607557e64a33
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4266820855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.4266820855
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2040906407
Short name T941
Test name
Test status
Simulation time 47067578 ps
CPU time 0.86 seconds
Started Mar 10 01:17:09 PM PDT 24
Finished Mar 10 01:17:10 PM PDT 24
Peak memory 196184 kb
Host smart-66119be9-804b-4480-bc65-bdc740eb7972
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040906407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2040906407
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2016910990
Short name T934
Test name
Test status
Simulation time 240391890 ps
CPU time 1.16 seconds
Started Mar 10 01:17:08 PM PDT 24
Finished Mar 10 01:17:09 PM PDT 24
Peak memory 196164 kb
Host smart-21b4d29f-529c-4404-89e9-62763f056493
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2016910990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2016910990
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.376167141
Short name T903
Test name
Test status
Simulation time 46724601 ps
CPU time 1.05 seconds
Started Mar 10 01:17:18 PM PDT 24
Finished Mar 10 01:17:19 PM PDT 24
Peak memory 196612 kb
Host smart-7d75d753-ad0e-40fa-88b7-b64ce58566b9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376167141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.376167141
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1968435227
Short name T921
Test name
Test status
Simulation time 645809701 ps
CPU time 1.28 seconds
Started Mar 10 01:17:15 PM PDT 24
Finished Mar 10 01:17:17 PM PDT 24
Peak memory 198128 kb
Host smart-f2ea33fb-4b4b-4d7a-819b-c387a6d36988
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1968435227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1968435227
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2214289286
Short name T896
Test name
Test status
Simulation time 39237169 ps
CPU time 1.06 seconds
Started Mar 10 01:17:14 PM PDT 24
Finished Mar 10 01:17:15 PM PDT 24
Peak memory 196752 kb
Host smart-e99ed57a-3553-4a63-8538-f71722b70e1d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214289286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2214289286
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.707757867
Short name T901
Test name
Test status
Simulation time 37916992 ps
CPU time 0.74 seconds
Started Mar 10 01:16:40 PM PDT 24
Finished Mar 10 01:16:41 PM PDT 24
Peak memory 194380 kb
Host smart-9294bdf6-33c1-415f-9229-18eea1a08ee8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=707757867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.707757867
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3525325975
Short name T945
Test name
Test status
Simulation time 154351148 ps
CPU time 1.29 seconds
Started Mar 10 01:16:42 PM PDT 24
Finished Mar 10 01:16:44 PM PDT 24
Peak memory 196580 kb
Host smart-e83f8a6c-8a45-441b-b281-ff09dbddc33a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525325975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3525325975
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1952830164
Short name T909
Test name
Test status
Simulation time 753274992 ps
CPU time 1.15 seconds
Started Mar 10 01:17:14 PM PDT 24
Finished Mar 10 01:17:16 PM PDT 24
Peak memory 196536 kb
Host smart-4b0b5822-1827-499e-9ef0-6edc73c7d991
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1952830164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1952830164
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3811434325
Short name T862
Test name
Test status
Simulation time 38246741 ps
CPU time 0.88 seconds
Started Mar 10 01:17:13 PM PDT 24
Finished Mar 10 01:17:15 PM PDT 24
Peak memory 195476 kb
Host smart-b880f896-b4f7-41e4-9a5f-7f903def5058
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811434325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3811434325
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3979779434
Short name T866
Test name
Test status
Simulation time 193822355 ps
CPU time 1.31 seconds
Started Mar 10 01:17:13 PM PDT 24
Finished Mar 10 01:17:15 PM PDT 24
Peak memory 196924 kb
Host smart-e85671bc-0628-42ef-b51f-8ccca27e6454
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3979779434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3979779434
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.131109755
Short name T916
Test name
Test status
Simulation time 88935119 ps
CPU time 0.99 seconds
Started Mar 10 01:17:14 PM PDT 24
Finished Mar 10 01:17:15 PM PDT 24
Peak memory 197472 kb
Host smart-2eaddebb-d9ae-40bb-b231-c3b265e70714
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131109755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.131109755
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.827186465
Short name T919
Test name
Test status
Simulation time 144847774 ps
CPU time 1.09 seconds
Started Mar 10 01:17:14 PM PDT 24
Finished Mar 10 01:17:16 PM PDT 24
Peak memory 196032 kb
Host smart-8dd9b3ac-64d2-4f88-bf45-e6a119c3ec52
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=827186465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.827186465
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2694789446
Short name T902
Test name
Test status
Simulation time 940077129 ps
CPU time 1.66 seconds
Started Mar 10 01:17:13 PM PDT 24
Finished Mar 10 01:17:16 PM PDT 24
Peak memory 198096 kb
Host smart-8278d44d-df14-4788-9767-861f61755661
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694789446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2694789446
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1756482508
Short name T882
Test name
Test status
Simulation time 1422651885 ps
CPU time 1.51 seconds
Started Mar 10 01:17:20 PM PDT 24
Finished Mar 10 01:17:21 PM PDT 24
Peak memory 198040 kb
Host smart-6cec05a3-ad30-43f0-9348-c21d1529ebfb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1756482508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1756482508
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.215056604
Short name T907
Test name
Test status
Simulation time 87215286 ps
CPU time 1.25 seconds
Started Mar 10 01:17:20 PM PDT 24
Finished Mar 10 01:17:22 PM PDT 24
Peak memory 197088 kb
Host smart-eaa616c7-f887-4bf5-8de3-ab8aa9cbd5e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215056604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.215056604
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.894687053
Short name T923
Test name
Test status
Simulation time 51940821 ps
CPU time 1.05 seconds
Started Mar 10 01:17:21 PM PDT 24
Finished Mar 10 01:17:22 PM PDT 24
Peak memory 196624 kb
Host smart-047c6549-c239-4400-afac-a0cf7e67c6c3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=894687053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.894687053
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.441075407
Short name T906
Test name
Test status
Simulation time 63068403 ps
CPU time 1.07 seconds
Started Mar 10 01:17:21 PM PDT 24
Finished Mar 10 01:17:23 PM PDT 24
Peak memory 196564 kb
Host smart-48f025e9-5fee-4c42-a4c5-531f8e6f8315
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441075407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.441075407
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3176554247
Short name T859
Test name
Test status
Simulation time 55808722 ps
CPU time 1 seconds
Started Mar 10 01:17:20 PM PDT 24
Finished Mar 10 01:17:21 PM PDT 24
Peak memory 196556 kb
Host smart-bd6e9fef-85e8-4aae-a838-f6eb3e755ae8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3176554247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3176554247
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1919205217
Short name T871
Test name
Test status
Simulation time 81830792 ps
CPU time 1.42 seconds
Started Mar 10 01:17:20 PM PDT 24
Finished Mar 10 01:17:22 PM PDT 24
Peak memory 197164 kb
Host smart-9c97643f-41e7-41ed-89c1-78c221b625f5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919205217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1919205217
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.2755838562
Short name T854
Test name
Test status
Simulation time 24499893 ps
CPU time 0.82 seconds
Started Mar 10 01:17:20 PM PDT 24
Finished Mar 10 01:17:21 PM PDT 24
Peak memory 195248 kb
Host smart-03108d59-6459-45ad-ad35-85342819f867
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2755838562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.2755838562
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1505832669
Short name T860
Test name
Test status
Simulation time 367851273 ps
CPU time 1.22 seconds
Started Mar 10 01:17:18 PM PDT 24
Finished Mar 10 01:17:20 PM PDT 24
Peak memory 195664 kb
Host smart-7ef6854a-483c-4d73-9dd3-8d826afbfa2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505832669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1505832669
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3284812818
Short name T877
Test name
Test status
Simulation time 387159847 ps
CPU time 0.83 seconds
Started Mar 10 01:17:20 PM PDT 24
Finished Mar 10 01:17:21 PM PDT 24
Peak memory 195316 kb
Host smart-531d22c2-48a1-47b7-a58a-54708dae8daa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3284812818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3284812818
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1643308649
Short name T894
Test name
Test status
Simulation time 133963332 ps
CPU time 1.25 seconds
Started Mar 10 01:17:19 PM PDT 24
Finished Mar 10 01:17:21 PM PDT 24
Peak memory 196780 kb
Host smart-e740e563-4f6d-4076-88b3-fef1af9fabb9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643308649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1643308649
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.2938364017
Short name T928
Test name
Test status
Simulation time 195027785 ps
CPU time 0.95 seconds
Started Mar 10 01:17:20 PM PDT 24
Finished Mar 10 01:17:21 PM PDT 24
Peak memory 196624 kb
Host smart-2661a7e6-0d05-4613-9b7a-0b0943743383
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2938364017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.2938364017
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.305787760
Short name T932
Test name
Test status
Simulation time 34790943 ps
CPU time 1.21 seconds
Started Mar 10 01:17:20 PM PDT 24
Finished Mar 10 01:17:22 PM PDT 24
Peak memory 196696 kb
Host smart-f72932df-1468-4fda-88c7-c743b8bdc3f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305787760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.305787760
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3377899036
Short name T898
Test name
Test status
Simulation time 289168399 ps
CPU time 1.16 seconds
Started Mar 10 01:17:24 PM PDT 24
Finished Mar 10 01:17:25 PM PDT 24
Peak memory 196516 kb
Host smart-ed518bcd-fff8-4bfd-adbf-075d7bb1dd70
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3377899036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3377899036
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2336590420
Short name T867
Test name
Test status
Simulation time 92775661 ps
CPU time 1.03 seconds
Started Mar 10 01:17:25 PM PDT 24
Finished Mar 10 01:17:27 PM PDT 24
Peak memory 196460 kb
Host smart-4f826993-ee16-486d-9df4-4a807b03da64
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336590420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2336590420
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2185832858
Short name T915
Test name
Test status
Simulation time 71545153 ps
CPU time 1.26 seconds
Started Mar 10 01:16:42 PM PDT 24
Finished Mar 10 01:16:43 PM PDT 24
Peak memory 198120 kb
Host smart-1cb47ae4-8cd5-447f-b284-7ba0deee94db
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2185832858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2185832858
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3876019492
Short name T930
Test name
Test status
Simulation time 131638530 ps
CPU time 1.11 seconds
Started Mar 10 01:16:40 PM PDT 24
Finished Mar 10 01:16:42 PM PDT 24
Peak memory 196644 kb
Host smart-21335da5-6c68-463a-bf7a-37a84018c786
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876019492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3876019492
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3057906478
Short name T925
Test name
Test status
Simulation time 53252822 ps
CPU time 0.95 seconds
Started Mar 10 01:17:25 PM PDT 24
Finished Mar 10 01:17:26 PM PDT 24
Peak memory 196352 kb
Host smart-6bb99d9c-d008-4f46-9953-cf69c84799d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3057906478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3057906478
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2238526736
Short name T887
Test name
Test status
Simulation time 212552912 ps
CPU time 1.01 seconds
Started Mar 10 01:17:25 PM PDT 24
Finished Mar 10 01:17:26 PM PDT 24
Peak memory 196724 kb
Host smart-ec3b7674-ad65-40b9-8fc5-86b7a8a692eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238526736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2238526736
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3701999832
Short name T936
Test name
Test status
Simulation time 151380085 ps
CPU time 1.3 seconds
Started Mar 10 01:17:25 PM PDT 24
Finished Mar 10 01:17:26 PM PDT 24
Peak memory 196120 kb
Host smart-5f6a7368-47bf-4919-b453-3bf639308e24
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3701999832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3701999832
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3865388254
Short name T926
Test name
Test status
Simulation time 225895782 ps
CPU time 1.26 seconds
Started Mar 10 01:17:25 PM PDT 24
Finished Mar 10 01:17:27 PM PDT 24
Peak memory 198088 kb
Host smart-ba5345f8-b0de-47c0-bf84-5ff8d8f9f6dd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865388254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3865388254
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.4067390703
Short name T912
Test name
Test status
Simulation time 368958049 ps
CPU time 1.43 seconds
Started Mar 10 01:17:26 PM PDT 24
Finished Mar 10 01:17:28 PM PDT 24
Peak memory 196888 kb
Host smart-485f220a-2987-4c63-a68d-f122d20c88b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4067390703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.4067390703
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.512910286
Short name T917
Test name
Test status
Simulation time 105470824 ps
CPU time 0.96 seconds
Started Mar 10 01:17:25 PM PDT 24
Finished Mar 10 01:17:26 PM PDT 24
Peak memory 196024 kb
Host smart-520172a0-c607-4f94-b143-9241b4135ec6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512910286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.512910286
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.632369421
Short name T880
Test name
Test status
Simulation time 210646796 ps
CPU time 1.13 seconds
Started Mar 10 01:17:26 PM PDT 24
Finished Mar 10 01:17:28 PM PDT 24
Peak memory 195980 kb
Host smart-d81ae2e7-454a-41c0-a440-f7284b3cdea4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=632369421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.632369421
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.805939309
Short name T900
Test name
Test status
Simulation time 50252206 ps
CPU time 1.08 seconds
Started Mar 10 01:17:25 PM PDT 24
Finished Mar 10 01:17:26 PM PDT 24
Peak memory 197532 kb
Host smart-613329b0-38a3-48de-8a2b-cd41fd87dea2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805939309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.805939309
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3826084473
Short name T935
Test name
Test status
Simulation time 66622804 ps
CPU time 1 seconds
Started Mar 10 01:17:26 PM PDT 24
Finished Mar 10 01:17:28 PM PDT 24
Peak memory 198012 kb
Host smart-29a01749-f05a-4e20-87da-8269733e7a95
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3826084473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3826084473
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3424319305
Short name T904
Test name
Test status
Simulation time 83805203 ps
CPU time 1.51 seconds
Started Mar 10 01:17:26 PM PDT 24
Finished Mar 10 01:17:28 PM PDT 24
Peak memory 198128 kb
Host smart-34eddb3b-3928-4f6e-9315-9389e2b33bb4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424319305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3424319305
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.3266286472
Short name T868
Test name
Test status
Simulation time 43636431 ps
CPU time 0.78 seconds
Started Mar 10 01:17:24 PM PDT 24
Finished Mar 10 01:17:25 PM PDT 24
Peak memory 195400 kb
Host smart-20cd8972-3e40-4fd7-89b7-4151692097a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3266286472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.3266286472
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4118440302
Short name T879
Test name
Test status
Simulation time 158003753 ps
CPU time 0.87 seconds
Started Mar 10 01:17:26 PM PDT 24
Finished Mar 10 01:17:27 PM PDT 24
Peak memory 196484 kb
Host smart-8f5ace30-2761-4130-8571-766d2947d9d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118440302 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4118440302
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3193248533
Short name T944
Test name
Test status
Simulation time 109386782 ps
CPU time 1.17 seconds
Started Mar 10 01:17:23 PM PDT 24
Finished Mar 10 01:17:24 PM PDT 24
Peak memory 196708 kb
Host smart-fd4189ae-9d0e-47d1-a44a-a359a8a55f6b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3193248533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3193248533
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3308632239
Short name T875
Test name
Test status
Simulation time 68931193 ps
CPU time 1.13 seconds
Started Mar 10 01:17:30 PM PDT 24
Finished Mar 10 01:17:32 PM PDT 24
Peak memory 195808 kb
Host smart-a6e65190-ab97-4666-888c-b875eeaf6bcf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308632239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3308632239
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.448554577
Short name T852
Test name
Test status
Simulation time 77248440 ps
CPU time 1.26 seconds
Started Mar 10 01:17:30 PM PDT 24
Finished Mar 10 01:17:32 PM PDT 24
Peak memory 196656 kb
Host smart-07b618ae-6adb-4063-886d-e2dfb1226ae8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=448554577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.448554577
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3577704391
Short name T937
Test name
Test status
Simulation time 112103522 ps
CPU time 1.19 seconds
Started Mar 10 01:17:34 PM PDT 24
Finished Mar 10 01:17:36 PM PDT 24
Peak memory 195820 kb
Host smart-9e06c1b4-6584-4939-a680-5cb7823359c3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577704391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3577704391
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.105774849
Short name T914
Test name
Test status
Simulation time 133789935 ps
CPU time 1.27 seconds
Started Mar 10 01:17:30 PM PDT 24
Finished Mar 10 01:17:32 PM PDT 24
Peak memory 195748 kb
Host smart-7eb36220-23c8-43a2-a8bc-1c2de9d1f373
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=105774849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.105774849
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.350926006
Short name T886
Test name
Test status
Simulation time 211615525 ps
CPU time 1.19 seconds
Started Mar 10 01:17:31 PM PDT 24
Finished Mar 10 01:17:33 PM PDT 24
Peak memory 198128 kb
Host smart-fc3dd420-155b-437b-bbd1-b4d86e8f77a7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350926006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.350926006
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.3483808197
Short name T872
Test name
Test status
Simulation time 134736148 ps
CPU time 1.13 seconds
Started Mar 10 01:17:31 PM PDT 24
Finished Mar 10 01:17:33 PM PDT 24
Peak memory 196036 kb
Host smart-1bc115d1-7fc2-4413-a93a-9892e739db5b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3483808197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.3483808197
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.720709291
Short name T881
Test name
Test status
Simulation time 48339069 ps
CPU time 0.88 seconds
Started Mar 10 01:17:31 PM PDT 24
Finished Mar 10 01:17:33 PM PDT 24
Peak memory 197332 kb
Host smart-6c004b91-77f6-4b7e-ab79-82182a835e68
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720709291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.720709291
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1627475957
Short name T924
Test name
Test status
Simulation time 57843294 ps
CPU time 1.01 seconds
Started Mar 10 01:16:42 PM PDT 24
Finished Mar 10 01:16:43 PM PDT 24
Peak memory 195800 kb
Host smart-b6cc6410-e157-4adf-a5b7-b4f99392fb73
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1627475957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1627475957
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2512056673
Short name T850
Test name
Test status
Simulation time 40884067 ps
CPU time 0.79 seconds
Started Mar 10 01:16:42 PM PDT 24
Finished Mar 10 01:16:43 PM PDT 24
Peak memory 195988 kb
Host smart-ccd8807b-fd59-406f-8f25-4ebe12f3eb3e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512056673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2512056673
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.770805713
Short name T891
Test name
Test status
Simulation time 73682011 ps
CPU time 1.25 seconds
Started Mar 10 01:17:36 PM PDT 24
Finished Mar 10 01:17:37 PM PDT 24
Peak memory 196564 kb
Host smart-102a852b-b424-4b0b-977f-b133df14f36a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=770805713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.770805713
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4181304499
Short name T895
Test name
Test status
Simulation time 24485102 ps
CPU time 0.75 seconds
Started Mar 10 01:17:35 PM PDT 24
Finished Mar 10 01:17:36 PM PDT 24
Peak memory 196228 kb
Host smart-b413a0a3-e1e6-4d51-869d-2b2e512ed482
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181304499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4181304499
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.55928177
Short name T897
Test name
Test status
Simulation time 37889555 ps
CPU time 1.07 seconds
Started Mar 10 01:17:36 PM PDT 24
Finished Mar 10 01:17:37 PM PDT 24
Peak memory 196832 kb
Host smart-bd37cb76-9c9c-4d9e-9ff3-4bdf00e0d7a8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=55928177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.55928177
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1815693021
Short name T927
Test name
Test status
Simulation time 55616806 ps
CPU time 1.17 seconds
Started Mar 10 01:17:34 PM PDT 24
Finished Mar 10 01:17:36 PM PDT 24
Peak memory 196088 kb
Host smart-f1332b23-2beb-4a7b-80d6-bf2c462064e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815693021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1815693021
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1031998701
Short name T884
Test name
Test status
Simulation time 150899126 ps
CPU time 1.4 seconds
Started Mar 10 01:17:35 PM PDT 24
Finished Mar 10 01:17:37 PM PDT 24
Peak memory 196732 kb
Host smart-a3d0731b-cdaa-4562-bb25-6c97652bab3a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1031998701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1031998701
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4212279814
Short name T910
Test name
Test status
Simulation time 32108122 ps
CPU time 0.86 seconds
Started Mar 10 01:17:34 PM PDT 24
Finished Mar 10 01:17:35 PM PDT 24
Peak memory 195328 kb
Host smart-601a685a-2989-475c-84f1-693421e90e36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212279814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4212279814
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1323309413
Short name T938
Test name
Test status
Simulation time 65716186 ps
CPU time 1.31 seconds
Started Mar 10 01:17:36 PM PDT 24
Finished Mar 10 01:17:38 PM PDT 24
Peak memory 196488 kb
Host smart-bf78bfc4-52f5-48ee-a2d8-26571a28beab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1323309413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1323309413
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.716346906
Short name T857
Test name
Test status
Simulation time 102958163 ps
CPU time 1.21 seconds
Started Mar 10 01:17:35 PM PDT 24
Finished Mar 10 01:17:37 PM PDT 24
Peak memory 196608 kb
Host smart-8660237c-7438-4d20-bf5e-4f93bc4c66f8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716346906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.716346906
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.4157517693
Short name T870
Test name
Test status
Simulation time 273418494 ps
CPU time 1.33 seconds
Started Mar 10 01:17:35 PM PDT 24
Finished Mar 10 01:17:37 PM PDT 24
Peak memory 196744 kb
Host smart-c207e9ef-030b-4476-9189-be5265097173
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4157517693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.4157517693
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2121869021
Short name T899
Test name
Test status
Simulation time 39186893 ps
CPU time 1.13 seconds
Started Mar 10 01:17:35 PM PDT 24
Finished Mar 10 01:17:37 PM PDT 24
Peak memory 196832 kb
Host smart-942585a3-b14f-4b7b-b3b9-d388a6381366
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121869021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2121869021
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.1969523517
Short name T853
Test name
Test status
Simulation time 51453930 ps
CPU time 0.86 seconds
Started Mar 10 01:17:35 PM PDT 24
Finished Mar 10 01:17:36 PM PDT 24
Peak memory 195436 kb
Host smart-9a95de5f-dfa5-4888-938a-a38a3666b4b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1969523517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.1969523517
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4006371998
Short name T876
Test name
Test status
Simulation time 133069538 ps
CPU time 0.96 seconds
Started Mar 10 01:17:37 PM PDT 24
Finished Mar 10 01:17:38 PM PDT 24
Peak memory 196908 kb
Host smart-758e8574-e544-4ade-bc9e-d9b430a7810b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006371998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4006371998
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.11609804
Short name T890
Test name
Test status
Simulation time 497462631 ps
CPU time 1.24 seconds
Started Mar 10 01:17:39 PM PDT 24
Finished Mar 10 01:17:40 PM PDT 24
Peak memory 198208 kb
Host smart-4cd46dfa-d0a7-4df4-8cbe-0fcf96dffbee
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=11609804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.11609804
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4126651232
Short name T946
Test name
Test status
Simulation time 113079810 ps
CPU time 1.02 seconds
Started Mar 10 01:17:41 PM PDT 24
Finished Mar 10 01:17:42 PM PDT 24
Peak memory 196200 kb
Host smart-5bc1862c-dc19-4b12-b62a-59334d1f041c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126651232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4126651232
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.45793487
Short name T864
Test name
Test status
Simulation time 56955474 ps
CPU time 1.28 seconds
Started Mar 10 01:17:41 PM PDT 24
Finished Mar 10 01:17:43 PM PDT 24
Peak memory 196040 kb
Host smart-fa563f28-db78-473e-9a9c-e86d395056b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=45793487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.45793487
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.325439482
Short name T892
Test name
Test status
Simulation time 333699097 ps
CPU time 1.26 seconds
Started Mar 10 01:17:41 PM PDT 24
Finished Mar 10 01:17:42 PM PDT 24
Peak memory 195740 kb
Host smart-b0500989-bea7-453d-93cc-7ea111625697
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325439482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.325439482
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.4127647043
Short name T863
Test name
Test status
Simulation time 193845005 ps
CPU time 1.03 seconds
Started Mar 10 01:17:41 PM PDT 24
Finished Mar 10 01:17:42 PM PDT 24
Peak memory 196584 kb
Host smart-dbdb9bf7-d69f-44d0-82bb-c32d3c2e7fd4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4127647043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.4127647043
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.37745904
Short name T908
Test name
Test status
Simulation time 51843737 ps
CPU time 1.07 seconds
Started Mar 10 01:17:40 PM PDT 24
Finished Mar 10 01:17:41 PM PDT 24
Peak memory 196524 kb
Host smart-19831514-f20b-4216-bee4-509f7c157b3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37745904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.37745904
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2426877685
Short name T873
Test name
Test status
Simulation time 20919659 ps
CPU time 0.74 seconds
Started Mar 10 01:17:41 PM PDT 24
Finished Mar 10 01:17:42 PM PDT 24
Peak memory 195496 kb
Host smart-15d87b6c-59e8-408b-a2d2-46ecfdbe1121
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2426877685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2426877685
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.665859504
Short name T920
Test name
Test status
Simulation time 36265215 ps
CPU time 0.91 seconds
Started Mar 10 01:17:39 PM PDT 24
Finished Mar 10 01:17:40 PM PDT 24
Peak memory 196192 kb
Host smart-d15c1590-456c-43bb-b18c-e5b11d29604d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665859504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.665859504
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1994193029
Short name T848
Test name
Test status
Simulation time 1749032723 ps
CPU time 1.38 seconds
Started Mar 10 01:16:42 PM PDT 24
Finished Mar 10 01:16:43 PM PDT 24
Peak memory 196896 kb
Host smart-0ddb8da4-857c-4c84-801d-8433c0c87160
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1994193029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1994193029
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3623843861
Short name T883
Test name
Test status
Simulation time 229794628 ps
CPU time 1.16 seconds
Started Mar 10 01:16:46 PM PDT 24
Finished Mar 10 01:16:47 PM PDT 24
Peak memory 196532 kb
Host smart-a523af40-058b-47a2-ac88-8d7bb1d81f3d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623843861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3623843861
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1445273075
Short name T933
Test name
Test status
Simulation time 40978181 ps
CPU time 0.82 seconds
Started Mar 10 01:16:46 PM PDT 24
Finished Mar 10 01:16:48 PM PDT 24
Peak memory 195352 kb
Host smart-4a1958ed-14b5-41e3-a66c-843cf8645fe8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1445273075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1445273075
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1908908658
Short name T918
Test name
Test status
Simulation time 106800308 ps
CPU time 1.28 seconds
Started Mar 10 01:16:46 PM PDT 24
Finished Mar 10 01:16:47 PM PDT 24
Peak memory 198072 kb
Host smart-b5f32187-a3ab-49d4-abdf-fa4884980dcd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908908658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1908908658
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3235224729
Short name T874
Test name
Test status
Simulation time 123750702 ps
CPU time 0.99 seconds
Started Mar 10 01:16:51 PM PDT 24
Finished Mar 10 01:16:52 PM PDT 24
Peak memory 196668 kb
Host smart-401455fd-0ef4-4a75-9769-2568474c7d3d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3235224729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3235224729
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2731926186
Short name T849
Test name
Test status
Simulation time 138666526 ps
CPU time 1.03 seconds
Started Mar 10 01:16:51 PM PDT 24
Finished Mar 10 01:16:52 PM PDT 24
Peak memory 196612 kb
Host smart-192b9ddb-0d0c-468d-8585-77ff6c3e0811
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731926186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2731926186
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.4058360702
Short name T939
Test name
Test status
Simulation time 39336558 ps
CPU time 1.07 seconds
Started Mar 10 01:16:50 PM PDT 24
Finished Mar 10 01:16:52 PM PDT 24
Peak memory 196064 kb
Host smart-bf646a43-5027-44f7-aae1-c215dfe4b738
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4058360702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.4058360702
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.59821970
Short name T885
Test name
Test status
Simulation time 494549419 ps
CPU time 0.91 seconds
Started Mar 10 01:16:49 PM PDT 24
Finished Mar 10 01:16:50 PM PDT 24
Peak memory 196756 kb
Host smart-745e9669-690b-49a5-8cab-2f0c984dc12b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59821970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.59821970
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2211274913
Short name T940
Test name
Test status
Simulation time 63212294 ps
CPU time 1.03 seconds
Started Mar 10 01:16:50 PM PDT 24
Finished Mar 10 01:16:51 PM PDT 24
Peak memory 195792 kb
Host smart-c95619b2-91a5-4437-b32b-227a33dd000c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2211274913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2211274913
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.465463519
Short name T865
Test name
Test status
Simulation time 194861861 ps
CPU time 1.01 seconds
Started Mar 10 01:16:51 PM PDT 24
Finished Mar 10 01:16:53 PM PDT 24
Peak memory 198088 kb
Host smart-bc7530d1-9342-44b8-a47c-adeef9e312bf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465463519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.465463519
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%