cp_pins | cp_stable_cycles | cp_pin_value | cp_filter_en | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[0] |
auto[0] |
55209 |
1 |
|
|
T22 |
1759 |
|
T18 |
1370 |
|
T96 |
1968 |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[0] |
auto[1] |
49226 |
1 |
|
|
T22 |
1778 |
|
T18 |
629 |
|
T96 |
2075 |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[1] |
auto[0] |
52224 |
1 |
|
|
T22 |
1630 |
|
T18 |
1880 |
|
T96 |
1723 |
all_gpio_pins[0] |
filter_cycles_or_more |
auto[1] |
auto[1] |
45334 |
1 |
|
|
T22 |
1079 |
|
T18 |
494 |
|
T96 |
975 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
31 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1615 |
1 |
|
|
T22 |
52 |
|
T18 |
32 |
|
T96 |
49 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1617 |
1 |
|
|
T22 |
56 |
|
T18 |
27 |
|
T96 |
49 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
31 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1587 |
1 |
|
|
T22 |
52 |
|
T18 |
31 |
|
T96 |
48 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1575 |
1 |
|
|
T22 |
54 |
|
T18 |
26 |
|
T96 |
49 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
31 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1556 |
1 |
|
|
T22 |
52 |
|
T18 |
31 |
|
T96 |
48 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1546 |
1 |
|
|
T22 |
53 |
|
T18 |
26 |
|
T96 |
48 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
31 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1517 |
1 |
|
|
T22 |
52 |
|
T18 |
31 |
|
T96 |
46 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1517 |
1 |
|
|
T22 |
52 |
|
T18 |
26 |
|
T96 |
47 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
31 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1497 |
1 |
|
|
T22 |
52 |
|
T18 |
31 |
|
T96 |
46 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
675 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1484 |
1 |
|
|
T22 |
51 |
|
T18 |
25 |
|
T96 |
47 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
31 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1454 |
1 |
|
|
T22 |
52 |
|
T18 |
31 |
|
T96 |
43 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
675 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1451 |
1 |
|
|
T22 |
51 |
|
T18 |
24 |
|
T96 |
47 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
674 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
31 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1423 |
1 |
|
|
T22 |
51 |
|
T18 |
31 |
|
T96 |
41 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
672 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1424 |
1 |
|
|
T22 |
50 |
|
T18 |
23 |
|
T96 |
47 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
674 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
31 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1388 |
1 |
|
|
T22 |
50 |
|
T18 |
30 |
|
T96 |
41 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
672 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1389 |
1 |
|
|
T22 |
48 |
|
T18 |
21 |
|
T96 |
46 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T22 |
22 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1360 |
1 |
|
|
T22 |
49 |
|
T18 |
30 |
|
T96 |
41 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
669 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1361 |
1 |
|
|
T22 |
48 |
|
T18 |
20 |
|
T96 |
46 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T22 |
22 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1328 |
1 |
|
|
T22 |
47 |
|
T18 |
30 |
|
T96 |
39 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
669 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1334 |
1 |
|
|
T22 |
48 |
|
T18 |
20 |
|
T96 |
45 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
668 |
1 |
|
|
T22 |
22 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1296 |
1 |
|
|
T22 |
45 |
|
T18 |
30 |
|
T96 |
39 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1301 |
1 |
|
|
T22 |
48 |
|
T18 |
19 |
|
T96 |
43 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
668 |
1 |
|
|
T22 |
22 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1264 |
1 |
|
|
T22 |
43 |
|
T18 |
29 |
|
T96 |
39 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1264 |
1 |
|
|
T22 |
45 |
|
T18 |
19 |
|
T96 |
40 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
667 |
1 |
|
|
T22 |
22 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1235 |
1 |
|
|
T22 |
41 |
|
T18 |
29 |
|
T96 |
38 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1231 |
1 |
|
|
T22 |
44 |
|
T18 |
19 |
|
T96 |
39 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
667 |
1 |
|
|
T22 |
22 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1203 |
1 |
|
|
T22 |
38 |
|
T18 |
28 |
|
T96 |
38 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1199 |
1 |
|
|
T22 |
44 |
|
T18 |
18 |
|
T96 |
37 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
667 |
1 |
|
|
T22 |
22 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1180 |
1 |
|
|
T22 |
37 |
|
T18 |
27 |
|
T96 |
38 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T22 |
18 |
|
T18 |
20 |
|
T96 |
30 |
all_gpio_pins[0] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1175 |
1 |
|
|
T22 |
42 |
|
T18 |
17 |
|
T96 |
36 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[0] |
auto[0] |
53087 |
1 |
|
|
T22 |
1591 |
|
T18 |
684 |
|
T96 |
1523 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[0] |
auto[1] |
43562 |
1 |
|
|
T22 |
1396 |
|
T18 |
2050 |
|
T96 |
1414 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56763 |
1 |
|
|
T22 |
1260 |
|
T18 |
690 |
|
T96 |
2706 |
all_gpio_pins[1] |
filter_cycles_or_more |
auto[1] |
auto[1] |
48322 |
1 |
|
|
T22 |
1788 |
|
T18 |
784 |
|
T96 |
1053 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
36 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1611 |
1 |
|
|
T22 |
62 |
|
T18 |
45 |
|
T96 |
47 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
697 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1600 |
1 |
|
|
T22 |
60 |
|
T18 |
45 |
|
T96 |
50 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
36 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1569 |
1 |
|
|
T22 |
61 |
|
T18 |
45 |
|
T96 |
43 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
697 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1574 |
1 |
|
|
T22 |
59 |
|
T18 |
44 |
|
T96 |
50 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
36 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1539 |
1 |
|
|
T22 |
60 |
|
T18 |
44 |
|
T96 |
43 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
697 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1547 |
1 |
|
|
T22 |
58 |
|
T18 |
44 |
|
T96 |
47 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
36 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1509 |
1 |
|
|
T22 |
58 |
|
T18 |
43 |
|
T96 |
40 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
697 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1516 |
1 |
|
|
T22 |
56 |
|
T18 |
42 |
|
T96 |
46 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
21 |
|
T18 |
11 |
|
T96 |
36 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1485 |
1 |
|
|
T22 |
56 |
|
T18 |
43 |
|
T96 |
40 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1488 |
1 |
|
|
T22 |
56 |
|
T18 |
39 |
|
T96 |
43 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
21 |
|
T18 |
11 |
|
T96 |
36 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1458 |
1 |
|
|
T22 |
55 |
|
T18 |
43 |
|
T96 |
39 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1454 |
1 |
|
|
T22 |
56 |
|
T18 |
36 |
|
T96 |
41 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T22 |
21 |
|
T18 |
11 |
|
T96 |
36 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1427 |
1 |
|
|
T22 |
53 |
|
T18 |
42 |
|
T96 |
39 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1426 |
1 |
|
|
T22 |
55 |
|
T18 |
36 |
|
T96 |
41 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T22 |
21 |
|
T18 |
11 |
|
T96 |
36 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1397 |
1 |
|
|
T22 |
53 |
|
T18 |
41 |
|
T96 |
39 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1391 |
1 |
|
|
T22 |
54 |
|
T18 |
35 |
|
T96 |
41 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
674 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
35 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1372 |
1 |
|
|
T22 |
53 |
|
T18 |
40 |
|
T96 |
40 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1360 |
1 |
|
|
T22 |
53 |
|
T18 |
34 |
|
T96 |
39 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
674 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
35 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1332 |
1 |
|
|
T22 |
51 |
|
T18 |
38 |
|
T96 |
40 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1324 |
1 |
|
|
T22 |
52 |
|
T18 |
32 |
|
T96 |
38 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
35 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1302 |
1 |
|
|
T22 |
51 |
|
T18 |
37 |
|
T96 |
40 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1292 |
1 |
|
|
T22 |
50 |
|
T18 |
29 |
|
T96 |
38 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
35 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1266 |
1 |
|
|
T22 |
51 |
|
T18 |
36 |
|
T96 |
40 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1268 |
1 |
|
|
T22 |
49 |
|
T18 |
29 |
|
T96 |
37 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
35 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1239 |
1 |
|
|
T22 |
50 |
|
T18 |
35 |
|
T96 |
40 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1233 |
1 |
|
|
T22 |
49 |
|
T18 |
28 |
|
T96 |
36 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
35 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1204 |
1 |
|
|
T22 |
49 |
|
T18 |
35 |
|
T96 |
40 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1197 |
1 |
|
|
T22 |
48 |
|
T18 |
27 |
|
T96 |
35 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
35 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1165 |
1 |
|
|
T22 |
48 |
|
T18 |
34 |
|
T96 |
38 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
23 |
|
T18 |
11 |
|
T96 |
33 |
all_gpio_pins[1] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1173 |
1 |
|
|
T22 |
47 |
|
T18 |
25 |
|
T96 |
35 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[0] |
auto[0] |
57894 |
1 |
|
|
T22 |
1473 |
|
T18 |
703 |
|
T96 |
1349 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[0] |
auto[1] |
42973 |
1 |
|
|
T22 |
1722 |
|
T18 |
819 |
|
T96 |
1086 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[1] |
auto[0] |
53514 |
1 |
|
|
T22 |
1467 |
|
T18 |
2087 |
|
T96 |
1509 |
all_gpio_pins[2] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46411 |
1 |
|
|
T22 |
1284 |
|
T18 |
694 |
|
T96 |
2676 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1651 |
1 |
|
|
T22 |
63 |
|
T18 |
39 |
|
T96 |
66 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1658 |
1 |
|
|
T22 |
63 |
|
T18 |
35 |
|
T96 |
68 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1621 |
1 |
|
|
T22 |
61 |
|
T18 |
39 |
|
T96 |
64 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1631 |
1 |
|
|
T22 |
63 |
|
T18 |
34 |
|
T96 |
68 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1588 |
1 |
|
|
T22 |
61 |
|
T18 |
37 |
|
T96 |
59 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1591 |
1 |
|
|
T22 |
63 |
|
T18 |
34 |
|
T96 |
64 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1552 |
1 |
|
|
T22 |
59 |
|
T18 |
37 |
|
T96 |
58 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1561 |
1 |
|
|
T22 |
63 |
|
T18 |
32 |
|
T96 |
63 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1527 |
1 |
|
|
T22 |
58 |
|
T18 |
35 |
|
T96 |
58 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1527 |
1 |
|
|
T22 |
63 |
|
T18 |
31 |
|
T96 |
62 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1497 |
1 |
|
|
T22 |
58 |
|
T18 |
35 |
|
T96 |
57 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1487 |
1 |
|
|
T22 |
59 |
|
T18 |
31 |
|
T96 |
62 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
681 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1466 |
1 |
|
|
T22 |
54 |
|
T18 |
34 |
|
T96 |
55 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
675 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1455 |
1 |
|
|
T22 |
57 |
|
T18 |
29 |
|
T96 |
62 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
681 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1449 |
1 |
|
|
T22 |
53 |
|
T18 |
34 |
|
T96 |
54 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
675 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1426 |
1 |
|
|
T22 |
55 |
|
T18 |
29 |
|
T96 |
62 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T22 |
24 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1417 |
1 |
|
|
T22 |
51 |
|
T18 |
33 |
|
T96 |
51 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1393 |
1 |
|
|
T22 |
53 |
|
T18 |
29 |
|
T96 |
62 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T22 |
24 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1375 |
1 |
|
|
T22 |
50 |
|
T18 |
32 |
|
T96 |
45 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1357 |
1 |
|
|
T22 |
51 |
|
T18 |
29 |
|
T96 |
61 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T22 |
24 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1337 |
1 |
|
|
T22 |
48 |
|
T18 |
31 |
|
T96 |
44 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
672 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1322 |
1 |
|
|
T22 |
50 |
|
T18 |
28 |
|
T96 |
60 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T22 |
24 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1306 |
1 |
|
|
T22 |
47 |
|
T18 |
30 |
|
T96 |
42 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
672 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1276 |
1 |
|
|
T22 |
50 |
|
T18 |
26 |
|
T96 |
60 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T22 |
24 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1278 |
1 |
|
|
T22 |
46 |
|
T18 |
30 |
|
T96 |
40 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
672 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1238 |
1 |
|
|
T22 |
47 |
|
T18 |
26 |
|
T96 |
59 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T22 |
24 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1251 |
1 |
|
|
T22 |
46 |
|
T18 |
29 |
|
T96 |
39 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
672 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1206 |
1 |
|
|
T22 |
45 |
|
T18 |
25 |
|
T96 |
59 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T22 |
24 |
|
T18 |
12 |
|
T96 |
22 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1223 |
1 |
|
|
T22 |
46 |
|
T18 |
27 |
|
T96 |
38 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
672 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[2] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1165 |
1 |
|
|
T22 |
44 |
|
T18 |
25 |
|
T96 |
57 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58539 |
1 |
|
|
T22 |
1490 |
|
T18 |
954 |
|
T96 |
2522 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46512 |
1 |
|
|
T22 |
1752 |
|
T18 |
1745 |
|
T96 |
1023 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[1] |
auto[0] |
51011 |
1 |
|
|
T22 |
1829 |
|
T18 |
1041 |
|
T96 |
2287 |
all_gpio_pins[3] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46397 |
1 |
|
|
T22 |
1020 |
|
T18 |
710 |
|
T96 |
1153 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T22 |
31 |
|
T18 |
15 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1591 |
1 |
|
|
T22 |
48 |
|
T18 |
30 |
|
T96 |
49 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1596 |
1 |
|
|
T22 |
50 |
|
T18 |
28 |
|
T96 |
45 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T22 |
31 |
|
T18 |
15 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1568 |
1 |
|
|
T22 |
47 |
|
T18 |
29 |
|
T96 |
48 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1562 |
1 |
|
|
T22 |
50 |
|
T18 |
28 |
|
T96 |
45 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
31 |
|
T18 |
15 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1534 |
1 |
|
|
T22 |
46 |
|
T18 |
28 |
|
T96 |
46 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1529 |
1 |
|
|
T22 |
50 |
|
T18 |
28 |
|
T96 |
45 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
31 |
|
T18 |
15 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1498 |
1 |
|
|
T22 |
46 |
|
T18 |
27 |
|
T96 |
44 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1498 |
1 |
|
|
T22 |
50 |
|
T18 |
28 |
|
T96 |
44 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T22 |
31 |
|
T18 |
14 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1486 |
1 |
|
|
T22 |
46 |
|
T18 |
27 |
|
T96 |
43 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
665 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1463 |
1 |
|
|
T22 |
50 |
|
T18 |
26 |
|
T96 |
41 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T22 |
31 |
|
T18 |
14 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1455 |
1 |
|
|
T22 |
46 |
|
T18 |
25 |
|
T96 |
42 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
665 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1429 |
1 |
|
|
T22 |
49 |
|
T18 |
26 |
|
T96 |
39 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
669 |
1 |
|
|
T22 |
31 |
|
T18 |
14 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1430 |
1 |
|
|
T22 |
46 |
|
T18 |
25 |
|
T96 |
42 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
661 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1400 |
1 |
|
|
T22 |
48 |
|
T18 |
26 |
|
T96 |
38 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
669 |
1 |
|
|
T22 |
31 |
|
T18 |
14 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1402 |
1 |
|
|
T22 |
46 |
|
T18 |
25 |
|
T96 |
40 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
661 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1376 |
1 |
|
|
T22 |
48 |
|
T18 |
26 |
|
T96 |
36 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
664 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1369 |
1 |
|
|
T22 |
43 |
|
T18 |
25 |
|
T96 |
40 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1349 |
1 |
|
|
T22 |
47 |
|
T18 |
26 |
|
T96 |
35 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
664 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1349 |
1 |
|
|
T22 |
43 |
|
T18 |
25 |
|
T96 |
39 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1321 |
1 |
|
|
T22 |
46 |
|
T18 |
26 |
|
T96 |
35 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
662 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1311 |
1 |
|
|
T22 |
40 |
|
T18 |
24 |
|
T96 |
38 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1297 |
1 |
|
|
T22 |
44 |
|
T18 |
26 |
|
T96 |
35 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
662 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
24 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1277 |
1 |
|
|
T22 |
38 |
|
T18 |
23 |
|
T96 |
36 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1256 |
1 |
|
|
T22 |
41 |
|
T18 |
25 |
|
T96 |
35 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
660 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
23 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1247 |
1 |
|
|
T22 |
37 |
|
T18 |
21 |
|
T96 |
36 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1226 |
1 |
|
|
T22 |
40 |
|
T18 |
25 |
|
T96 |
34 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
660 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
23 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1216 |
1 |
|
|
T22 |
36 |
|
T18 |
19 |
|
T96 |
36 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1194 |
1 |
|
|
T22 |
39 |
|
T18 |
25 |
|
T96 |
33 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
660 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
23 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1176 |
1 |
|
|
T22 |
36 |
|
T18 |
17 |
|
T96 |
35 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
28 |
all_gpio_pins[3] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1169 |
1 |
|
|
T22 |
36 |
|
T18 |
25 |
|
T96 |
33 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[0] |
auto[0] |
56137 |
1 |
|
|
T22 |
1513 |
|
T18 |
866 |
|
T96 |
1277 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[0] |
auto[1] |
44476 |
1 |
|
|
T22 |
1590 |
|
T18 |
621 |
|
T96 |
1061 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55444 |
1 |
|
|
T22 |
1810 |
|
T18 |
1038 |
|
T96 |
1668 |
all_gpio_pins[4] |
filter_cycles_or_more |
auto[1] |
auto[1] |
45776 |
1 |
|
|
T22 |
1397 |
|
T18 |
1798 |
|
T96 |
2463 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
715 |
1 |
|
|
T22 |
18 |
|
T18 |
19 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1577 |
1 |
|
|
T22 |
56 |
|
T18 |
29 |
|
T96 |
65 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1574 |
1 |
|
|
T22 |
50 |
|
T18 |
28 |
|
T96 |
68 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
715 |
1 |
|
|
T22 |
18 |
|
T18 |
19 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1540 |
1 |
|
|
T22 |
53 |
|
T18 |
29 |
|
T96 |
64 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1544 |
1 |
|
|
T22 |
50 |
|
T18 |
27 |
|
T96 |
67 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T22 |
18 |
|
T18 |
19 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1510 |
1 |
|
|
T22 |
52 |
|
T18 |
29 |
|
T96 |
61 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1511 |
1 |
|
|
T22 |
49 |
|
T18 |
26 |
|
T96 |
66 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T22 |
18 |
|
T18 |
19 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1473 |
1 |
|
|
T22 |
50 |
|
T18 |
29 |
|
T96 |
60 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1479 |
1 |
|
|
T22 |
49 |
|
T18 |
25 |
|
T96 |
65 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
710 |
1 |
|
|
T22 |
18 |
|
T18 |
18 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1458 |
1 |
|
|
T22 |
49 |
|
T18 |
28 |
|
T96 |
59 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1464 |
1 |
|
|
T22 |
48 |
|
T18 |
25 |
|
T96 |
65 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
710 |
1 |
|
|
T22 |
18 |
|
T18 |
18 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1416 |
1 |
|
|
T22 |
49 |
|
T18 |
28 |
|
T96 |
58 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
709 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1436 |
1 |
|
|
T22 |
46 |
|
T18 |
25 |
|
T96 |
63 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
704 |
1 |
|
|
T22 |
18 |
|
T18 |
18 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1386 |
1 |
|
|
T22 |
49 |
|
T18 |
27 |
|
T96 |
56 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1406 |
1 |
|
|
T22 |
45 |
|
T18 |
25 |
|
T96 |
61 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
704 |
1 |
|
|
T22 |
18 |
|
T18 |
18 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1356 |
1 |
|
|
T22 |
48 |
|
T18 |
26 |
|
T96 |
56 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1379 |
1 |
|
|
T22 |
45 |
|
T18 |
25 |
|
T96 |
60 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T22 |
17 |
|
T18 |
18 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1329 |
1 |
|
|
T22 |
48 |
|
T18 |
25 |
|
T96 |
53 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
705 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1338 |
1 |
|
|
T22 |
44 |
|
T18 |
25 |
|
T96 |
58 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T22 |
17 |
|
T18 |
18 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1310 |
1 |
|
|
T22 |
47 |
|
T18 |
25 |
|
T96 |
51 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
705 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1307 |
1 |
|
|
T22 |
43 |
|
T18 |
25 |
|
T96 |
58 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T22 |
17 |
|
T18 |
18 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1282 |
1 |
|
|
T22 |
45 |
|
T18 |
25 |
|
T96 |
51 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
704 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1280 |
1 |
|
|
T22 |
43 |
|
T18 |
25 |
|
T96 |
56 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T22 |
17 |
|
T18 |
18 |
|
T96 |
27 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1253 |
1 |
|
|
T22 |
42 |
|
T18 |
24 |
|
T96 |
48 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
704 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1254 |
1 |
|
|
T22 |
42 |
|
T18 |
25 |
|
T96 |
56 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
17 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1225 |
1 |
|
|
T22 |
42 |
|
T18 |
24 |
|
T96 |
45 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
704 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1224 |
1 |
|
|
T22 |
41 |
|
T18 |
24 |
|
T96 |
55 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
17 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1182 |
1 |
|
|
T22 |
40 |
|
T18 |
24 |
|
T96 |
44 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
704 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1193 |
1 |
|
|
T22 |
40 |
|
T18 |
23 |
|
T96 |
54 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
17 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1150 |
1 |
|
|
T22 |
38 |
|
T18 |
24 |
|
T96 |
42 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
704 |
1 |
|
|
T22 |
23 |
|
T18 |
20 |
|
T96 |
24 |
all_gpio_pins[4] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1156 |
1 |
|
|
T22 |
40 |
|
T18 |
22 |
|
T96 |
53 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[0] |
auto[0] |
56627 |
1 |
|
|
T22 |
1778 |
|
T18 |
1283 |
|
T96 |
1692 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48646 |
1 |
|
|
T22 |
1236 |
|
T18 |
655 |
|
T96 |
1098 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[1] |
auto[0] |
58330 |
1 |
|
|
T22 |
1802 |
|
T18 |
2160 |
|
T96 |
2714 |
all_gpio_pins[5] |
filter_cycles_or_more |
auto[1] |
auto[1] |
39339 |
1 |
|
|
T22 |
1319 |
|
T18 |
453 |
|
T96 |
1168 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
666 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1591 |
1 |
|
|
T22 |
55 |
|
T18 |
28 |
|
T96 |
52 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
688 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1561 |
1 |
|
|
T22 |
55 |
|
T18 |
23 |
|
T96 |
56 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
666 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1566 |
1 |
|
|
T22 |
54 |
|
T18 |
28 |
|
T96 |
51 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
688 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1538 |
1 |
|
|
T22 |
54 |
|
T18 |
22 |
|
T96 |
56 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
665 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1533 |
1 |
|
|
T22 |
54 |
|
T18 |
28 |
|
T96 |
50 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
688 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1499 |
1 |
|
|
T22 |
52 |
|
T18 |
20 |
|
T96 |
55 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
665 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1500 |
1 |
|
|
T22 |
51 |
|
T18 |
28 |
|
T96 |
50 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
688 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1467 |
1 |
|
|
T22 |
51 |
|
T18 |
19 |
|
T96 |
53 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
662 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1475 |
1 |
|
|
T22 |
51 |
|
T18 |
28 |
|
T96 |
49 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1429 |
1 |
|
|
T22 |
49 |
|
T18 |
19 |
|
T96 |
53 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
662 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1447 |
1 |
|
|
T22 |
51 |
|
T18 |
26 |
|
T96 |
47 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1403 |
1 |
|
|
T22 |
49 |
|
T18 |
19 |
|
T96 |
52 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
656 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1418 |
1 |
|
|
T22 |
51 |
|
T18 |
25 |
|
T96 |
45 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1377 |
1 |
|
|
T22 |
46 |
|
T18 |
19 |
|
T96 |
52 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
656 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1384 |
1 |
|
|
T22 |
49 |
|
T18 |
24 |
|
T96 |
44 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
682 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1349 |
1 |
|
|
T22 |
45 |
|
T18 |
18 |
|
T96 |
50 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
652 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
29 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1343 |
1 |
|
|
T22 |
48 |
|
T18 |
24 |
|
T96 |
44 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1331 |
1 |
|
|
T22 |
45 |
|
T18 |
17 |
|
T96 |
50 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
652 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
29 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1309 |
1 |
|
|
T22 |
45 |
|
T18 |
24 |
|
T96 |
44 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1306 |
1 |
|
|
T22 |
45 |
|
T18 |
17 |
|
T96 |
49 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
651 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
29 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1277 |
1 |
|
|
T22 |
44 |
|
T18 |
24 |
|
T96 |
44 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1278 |
1 |
|
|
T22 |
45 |
|
T18 |
17 |
|
T96 |
49 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
651 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
29 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1247 |
1 |
|
|
T22 |
44 |
|
T18 |
24 |
|
T96 |
44 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1242 |
1 |
|
|
T22 |
43 |
|
T18 |
17 |
|
T96 |
47 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
650 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
29 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1217 |
1 |
|
|
T22 |
43 |
|
T18 |
24 |
|
T96 |
42 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
679 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1203 |
1 |
|
|
T22 |
43 |
|
T18 |
17 |
|
T96 |
47 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
650 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
29 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1195 |
1 |
|
|
T22 |
43 |
|
T18 |
24 |
|
T96 |
41 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
679 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1161 |
1 |
|
|
T22 |
43 |
|
T18 |
13 |
|
T96 |
44 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
650 |
1 |
|
|
T22 |
25 |
|
T18 |
13 |
|
T96 |
29 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1162 |
1 |
|
|
T22 |
42 |
|
T18 |
23 |
|
T96 |
40 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
679 |
1 |
|
|
T22 |
24 |
|
T18 |
18 |
|
T96 |
26 |
all_gpio_pins[5] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1137 |
1 |
|
|
T22 |
41 |
|
T18 |
13 |
|
T96 |
44 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[0] |
auto[0] |
55137 |
1 |
|
|
T22 |
1776 |
|
T18 |
631 |
|
T96 |
1360 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46127 |
1 |
|
|
T22 |
1774 |
|
T18 |
1753 |
|
T96 |
1150 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[1] |
auto[0] |
53461 |
1 |
|
|
T22 |
1432 |
|
T18 |
1218 |
|
T96 |
2638 |
all_gpio_pins[6] |
filter_cycles_or_more |
auto[1] |
auto[1] |
48188 |
1 |
|
|
T22 |
1166 |
|
T18 |
756 |
|
T96 |
1597 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1556 |
1 |
|
|
T22 |
60 |
|
T18 |
37 |
|
T96 |
62 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1548 |
1 |
|
|
T22 |
56 |
|
T18 |
35 |
|
T96 |
62 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1525 |
1 |
|
|
T22 |
57 |
|
T18 |
36 |
|
T96 |
60 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1507 |
1 |
|
|
T22 |
55 |
|
T18 |
35 |
|
T96 |
61 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
691 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1498 |
1 |
|
|
T22 |
55 |
|
T18 |
35 |
|
T96 |
57 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1483 |
1 |
|
|
T22 |
55 |
|
T18 |
33 |
|
T96 |
61 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
691 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1469 |
1 |
|
|
T22 |
55 |
|
T18 |
35 |
|
T96 |
54 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1461 |
1 |
|
|
T22 |
53 |
|
T18 |
33 |
|
T96 |
59 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T22 |
21 |
|
T18 |
11 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1439 |
1 |
|
|
T22 |
55 |
|
T18 |
33 |
|
T96 |
53 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1437 |
1 |
|
|
T22 |
52 |
|
T18 |
32 |
|
T96 |
58 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T22 |
21 |
|
T18 |
11 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1414 |
1 |
|
|
T22 |
53 |
|
T18 |
33 |
|
T96 |
52 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1408 |
1 |
|
|
T22 |
51 |
|
T18 |
31 |
|
T96 |
58 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
21 |
|
T18 |
11 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1387 |
1 |
|
|
T22 |
52 |
|
T18 |
32 |
|
T96 |
50 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1379 |
1 |
|
|
T22 |
50 |
|
T18 |
30 |
|
T96 |
57 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
21 |
|
T18 |
11 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1359 |
1 |
|
|
T22 |
52 |
|
T18 |
32 |
|
T96 |
49 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1346 |
1 |
|
|
T22 |
49 |
|
T18 |
30 |
|
T96 |
55 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1337 |
1 |
|
|
T22 |
50 |
|
T18 |
32 |
|
T96 |
48 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1313 |
1 |
|
|
T22 |
48 |
|
T18 |
30 |
|
T96 |
54 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1313 |
1 |
|
|
T22 |
49 |
|
T18 |
32 |
|
T96 |
47 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1283 |
1 |
|
|
T22 |
46 |
|
T18 |
30 |
|
T96 |
53 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1280 |
1 |
|
|
T22 |
47 |
|
T18 |
31 |
|
T96 |
46 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1253 |
1 |
|
|
T22 |
44 |
|
T18 |
30 |
|
T96 |
53 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1249 |
1 |
|
|
T22 |
47 |
|
T18 |
30 |
|
T96 |
46 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1223 |
1 |
|
|
T22 |
40 |
|
T18 |
29 |
|
T96 |
48 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1213 |
1 |
|
|
T22 |
46 |
|
T18 |
30 |
|
T96 |
46 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1203 |
1 |
|
|
T22 |
40 |
|
T18 |
29 |
|
T96 |
47 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1180 |
1 |
|
|
T22 |
45 |
|
T18 |
29 |
|
T96 |
44 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1177 |
1 |
|
|
T22 |
40 |
|
T18 |
27 |
|
T96 |
46 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1140 |
1 |
|
|
T22 |
43 |
|
T18 |
29 |
|
T96 |
43 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
24 |
|
T18 |
13 |
|
T96 |
21 |
all_gpio_pins[6] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1149 |
1 |
|
|
T22 |
40 |
|
T18 |
26 |
|
T96 |
45 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[0] |
auto[0] |
53339 |
1 |
|
|
T22 |
1357 |
|
T18 |
1111 |
|
T96 |
1882 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[0] |
auto[1] |
43770 |
1 |
|
|
T22 |
1608 |
|
T18 |
614 |
|
T96 |
2016 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56254 |
1 |
|
|
T22 |
1204 |
|
T18 |
1994 |
|
T96 |
2052 |
all_gpio_pins[7] |
filter_cycles_or_more |
auto[1] |
auto[1] |
48627 |
1 |
|
|
T22 |
1913 |
|
T18 |
674 |
|
T96 |
801 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T22 |
21 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1591 |
1 |
|
|
T22 |
60 |
|
T18 |
24 |
|
T96 |
55 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1564 |
1 |
|
|
T22 |
63 |
|
T18 |
24 |
|
T96 |
54 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T22 |
21 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1562 |
1 |
|
|
T22 |
59 |
|
T18 |
24 |
|
T96 |
53 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1531 |
1 |
|
|
T22 |
61 |
|
T18 |
24 |
|
T96 |
50 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T22 |
21 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1537 |
1 |
|
|
T22 |
59 |
|
T18 |
23 |
|
T96 |
53 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1505 |
1 |
|
|
T22 |
59 |
|
T18 |
24 |
|
T96 |
48 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T22 |
21 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1513 |
1 |
|
|
T22 |
58 |
|
T18 |
22 |
|
T96 |
50 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1474 |
1 |
|
|
T22 |
59 |
|
T18 |
24 |
|
T96 |
46 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1483 |
1 |
|
|
T22 |
57 |
|
T18 |
21 |
|
T96 |
50 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
720 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1445 |
1 |
|
|
T22 |
59 |
|
T18 |
24 |
|
T96 |
46 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1452 |
1 |
|
|
T22 |
55 |
|
T18 |
21 |
|
T96 |
50 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
720 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1410 |
1 |
|
|
T22 |
59 |
|
T18 |
24 |
|
T96 |
46 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1423 |
1 |
|
|
T22 |
55 |
|
T18 |
21 |
|
T96 |
50 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1381 |
1 |
|
|
T22 |
57 |
|
T18 |
24 |
|
T96 |
46 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1390 |
1 |
|
|
T22 |
55 |
|
T18 |
21 |
|
T96 |
48 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1343 |
1 |
|
|
T22 |
57 |
|
T18 |
22 |
|
T96 |
43 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1352 |
1 |
|
|
T22 |
54 |
|
T18 |
21 |
|
T96 |
48 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1307 |
1 |
|
|
T22 |
55 |
|
T18 |
22 |
|
T96 |
43 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1326 |
1 |
|
|
T22 |
54 |
|
T18 |
21 |
|
T96 |
45 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1269 |
1 |
|
|
T22 |
53 |
|
T18 |
22 |
|
T96 |
42 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1293 |
1 |
|
|
T22 |
54 |
|
T18 |
21 |
|
T96 |
43 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
714 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1244 |
1 |
|
|
T22 |
49 |
|
T18 |
21 |
|
T96 |
41 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1268 |
1 |
|
|
T22 |
51 |
|
T18 |
21 |
|
T96 |
43 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
714 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1215 |
1 |
|
|
T22 |
48 |
|
T18 |
20 |
|
T96 |
39 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
27 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1233 |
1 |
|
|
T22 |
50 |
|
T18 |
21 |
|
T96 |
42 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1183 |
1 |
|
|
T22 |
47 |
|
T18 |
20 |
|
T96 |
35 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
27 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1198 |
1 |
|
|
T22 |
49 |
|
T18 |
20 |
|
T96 |
42 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1151 |
1 |
|
|
T22 |
45 |
|
T18 |
20 |
|
T96 |
34 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
27 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1169 |
1 |
|
|
T22 |
49 |
|
T18 |
19 |
|
T96 |
42 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T22 |
18 |
|
T18 |
21 |
|
T96 |
28 |
all_gpio_pins[7] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1128 |
1 |
|
|
T22 |
44 |
|
T18 |
20 |
|
T96 |
34 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[0] |
auto[0] |
59954 |
1 |
|
|
T22 |
1352 |
|
T18 |
935 |
|
T96 |
1384 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[0] |
auto[1] |
42500 |
1 |
|
|
T22 |
1057 |
|
T18 |
764 |
|
T96 |
1274 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[1] |
auto[0] |
52320 |
1 |
|
|
T22 |
1855 |
|
T18 |
974 |
|
T96 |
1460 |
all_gpio_pins[8] |
filter_cycles_or_more |
auto[1] |
auto[1] |
47329 |
1 |
|
|
T22 |
1960 |
|
T18 |
1673 |
|
T96 |
2471 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1603 |
1 |
|
|
T22 |
54 |
|
T18 |
32 |
|
T96 |
66 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1612 |
1 |
|
|
T22 |
55 |
|
T18 |
29 |
|
T96 |
72 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1565 |
1 |
|
|
T22 |
52 |
|
T18 |
32 |
|
T96 |
64 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1586 |
1 |
|
|
T22 |
55 |
|
T18 |
28 |
|
T96 |
70 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1530 |
1 |
|
|
T22 |
52 |
|
T18 |
31 |
|
T96 |
62 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1555 |
1 |
|
|
T22 |
55 |
|
T18 |
28 |
|
T96 |
68 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1506 |
1 |
|
|
T22 |
51 |
|
T18 |
31 |
|
T96 |
60 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1518 |
1 |
|
|
T22 |
53 |
|
T18 |
28 |
|
T96 |
66 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1477 |
1 |
|
|
T22 |
49 |
|
T18 |
30 |
|
T96 |
58 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1487 |
1 |
|
|
T22 |
52 |
|
T18 |
27 |
|
T96 |
65 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1438 |
1 |
|
|
T22 |
48 |
|
T18 |
30 |
|
T96 |
57 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
667 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1454 |
1 |
|
|
T22 |
51 |
|
T18 |
27 |
|
T96 |
64 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
674 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T22 |
48 |
|
T18 |
30 |
|
T96 |
55 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1437 |
1 |
|
|
T22 |
51 |
|
T18 |
27 |
|
T96 |
63 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
674 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1386 |
1 |
|
|
T22 |
46 |
|
T18 |
30 |
|
T96 |
54 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1405 |
1 |
|
|
T22 |
50 |
|
T18 |
26 |
|
T96 |
63 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
669 |
1 |
|
|
T22 |
21 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1359 |
1 |
|
|
T22 |
45 |
|
T18 |
29 |
|
T96 |
52 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1379 |
1 |
|
|
T22 |
50 |
|
T18 |
26 |
|
T96 |
63 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
669 |
1 |
|
|
T22 |
21 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1321 |
1 |
|
|
T22 |
44 |
|
T18 |
29 |
|
T96 |
52 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1349 |
1 |
|
|
T22 |
50 |
|
T18 |
26 |
|
T96 |
60 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
668 |
1 |
|
|
T22 |
21 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1291 |
1 |
|
|
T22 |
43 |
|
T18 |
29 |
|
T96 |
52 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1318 |
1 |
|
|
T22 |
48 |
|
T18 |
24 |
|
T96 |
60 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
668 |
1 |
|
|
T22 |
21 |
|
T18 |
15 |
|
T96 |
23 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1259 |
1 |
|
|
T22 |
42 |
|
T18 |
29 |
|
T96 |
49 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1284 |
1 |
|
|
T22 |
47 |
|
T18 |
23 |
|
T96 |
58 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
666 |
1 |
|
|
T22 |
21 |
|
T18 |
15 |
|
T96 |
22 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1235 |
1 |
|
|
T22 |
41 |
|
T18 |
28 |
|
T96 |
47 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
656 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1250 |
1 |
|
|
T22 |
46 |
|
T18 |
23 |
|
T96 |
57 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
666 |
1 |
|
|
T22 |
21 |
|
T18 |
15 |
|
T96 |
22 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1211 |
1 |
|
|
T22 |
41 |
|
T18 |
26 |
|
T96 |
46 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
656 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1225 |
1 |
|
|
T22 |
40 |
|
T18 |
22 |
|
T96 |
57 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
666 |
1 |
|
|
T22 |
21 |
|
T18 |
15 |
|
T96 |
22 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1173 |
1 |
|
|
T22 |
41 |
|
T18 |
26 |
|
T96 |
46 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
656 |
1 |
|
|
T22 |
21 |
|
T18 |
18 |
|
T96 |
17 |
all_gpio_pins[8] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1191 |
1 |
|
|
T22 |
39 |
|
T18 |
21 |
|
T96 |
57 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[0] |
auto[0] |
53967 |
1 |
|
|
T22 |
1320 |
|
T18 |
896 |
|
T96 |
1968 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[0] |
auto[1] |
43981 |
1 |
|
|
T22 |
1156 |
|
T18 |
1702 |
|
T96 |
2180 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[1] |
auto[0] |
62593 |
1 |
|
|
T22 |
2141 |
|
T18 |
1155 |
|
T96 |
1339 |
all_gpio_pins[9] |
filter_cycles_or_more |
auto[1] |
auto[1] |
41926 |
1 |
|
|
T22 |
1546 |
|
T18 |
559 |
|
T96 |
1036 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
740 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
35 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1540 |
1 |
|
|
T22 |
59 |
|
T18 |
29 |
|
T96 |
56 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1545 |
1 |
|
|
T22 |
57 |
|
T18 |
33 |
|
T96 |
57 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
740 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
35 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1507 |
1 |
|
|
T22 |
59 |
|
T18 |
29 |
|
T96 |
54 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1522 |
1 |
|
|
T22 |
56 |
|
T18 |
33 |
|
T96 |
56 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
35 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1472 |
1 |
|
|
T22 |
54 |
|
T18 |
29 |
|
T96 |
53 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1489 |
1 |
|
|
T22 |
55 |
|
T18 |
32 |
|
T96 |
55 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
739 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
35 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1435 |
1 |
|
|
T22 |
51 |
|
T18 |
29 |
|
T96 |
50 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
732 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1459 |
1 |
|
|
T22 |
54 |
|
T18 |
32 |
|
T96 |
55 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
736 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
35 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1402 |
1 |
|
|
T22 |
49 |
|
T18 |
27 |
|
T96 |
49 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1429 |
1 |
|
|
T22 |
54 |
|
T18 |
31 |
|
T96 |
55 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
736 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
35 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1358 |
1 |
|
|
T22 |
49 |
|
T18 |
27 |
|
T96 |
49 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
728 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1401 |
1 |
|
|
T22 |
54 |
|
T18 |
31 |
|
T96 |
54 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
730 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
35 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1340 |
1 |
|
|
T22 |
47 |
|
T18 |
27 |
|
T96 |
48 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1368 |
1 |
|
|
T22 |
53 |
|
T18 |
30 |
|
T96 |
52 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
730 |
1 |
|
|
T22 |
21 |
|
T18 |
20 |
|
T96 |
35 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1304 |
1 |
|
|
T22 |
44 |
|
T18 |
27 |
|
T96 |
46 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1334 |
1 |
|
|
T22 |
53 |
|
T18 |
30 |
|
T96 |
48 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
723 |
1 |
|
|
T22 |
20 |
|
T18 |
20 |
|
T96 |
34 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1281 |
1 |
|
|
T22 |
42 |
|
T18 |
27 |
|
T96 |
45 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
720 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1306 |
1 |
|
|
T22 |
53 |
|
T18 |
29 |
|
T96 |
47 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
723 |
1 |
|
|
T22 |
20 |
|
T18 |
20 |
|
T96 |
34 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1246 |
1 |
|
|
T22 |
42 |
|
T18 |
26 |
|
T96 |
43 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
720 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1277 |
1 |
|
|
T22 |
52 |
|
T18 |
27 |
|
T96 |
44 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T22 |
20 |
|
T18 |
20 |
|
T96 |
34 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1211 |
1 |
|
|
T22 |
42 |
|
T18 |
26 |
|
T96 |
41 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
718 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1245 |
1 |
|
|
T22 |
52 |
|
T18 |
27 |
|
T96 |
42 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T22 |
20 |
|
T18 |
20 |
|
T96 |
34 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1180 |
1 |
|
|
T22 |
40 |
|
T18 |
26 |
|
T96 |
41 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
718 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1212 |
1 |
|
|
T22 |
50 |
|
T18 |
25 |
|
T96 |
40 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T22 |
20 |
|
T18 |
20 |
|
T96 |
34 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1146 |
1 |
|
|
T22 |
39 |
|
T18 |
26 |
|
T96 |
39 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1195 |
1 |
|
|
T22 |
50 |
|
T18 |
25 |
|
T96 |
39 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T22 |
20 |
|
T18 |
20 |
|
T96 |
34 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1115 |
1 |
|
|
T22 |
38 |
|
T18 |
22 |
|
T96 |
39 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1173 |
1 |
|
|
T22 |
50 |
|
T18 |
24 |
|
T96 |
39 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T22 |
20 |
|
T18 |
20 |
|
T96 |
34 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1090 |
1 |
|
|
T22 |
38 |
|
T18 |
22 |
|
T96 |
38 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T22 |
23 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[9] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1151 |
1 |
|
|
T22 |
49 |
|
T18 |
23 |
|
T96 |
39 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[0] |
auto[0] |
56441 |
1 |
|
|
T22 |
2347 |
|
T18 |
1979 |
|
T96 |
2186 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[0] |
auto[1] |
44571 |
1 |
|
|
T22 |
1124 |
|
T18 |
792 |
|
T96 |
2172 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56601 |
1 |
|
|
T22 |
1563 |
|
T18 |
777 |
|
T96 |
1570 |
all_gpio_pins[10] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44386 |
1 |
|
|
T22 |
1080 |
|
T18 |
695 |
|
T96 |
790 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T22 |
29 |
|
T18 |
12 |
|
T96 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1561 |
1 |
|
|
T22 |
54 |
|
T18 |
42 |
|
T96 |
51 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1558 |
1 |
|
|
T22 |
60 |
|
T18 |
36 |
|
T96 |
49 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T22 |
29 |
|
T18 |
12 |
|
T96 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1534 |
1 |
|
|
T22 |
52 |
|
T18 |
41 |
|
T96 |
50 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1525 |
1 |
|
|
T22 |
59 |
|
T18 |
34 |
|
T96 |
47 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T22 |
29 |
|
T18 |
12 |
|
T96 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1505 |
1 |
|
|
T22 |
52 |
|
T18 |
39 |
|
T96 |
49 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1493 |
1 |
|
|
T22 |
58 |
|
T18 |
34 |
|
T96 |
47 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T22 |
29 |
|
T18 |
12 |
|
T96 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1481 |
1 |
|
|
T22 |
50 |
|
T18 |
39 |
|
T96 |
49 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
717 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1462 |
1 |
|
|
T22 |
58 |
|
T18 |
33 |
|
T96 |
46 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T22 |
29 |
|
T18 |
11 |
|
T96 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1457 |
1 |
|
|
T22 |
48 |
|
T18 |
38 |
|
T96 |
49 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1429 |
1 |
|
|
T22 |
55 |
|
T18 |
32 |
|
T96 |
44 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T22 |
29 |
|
T18 |
11 |
|
T96 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1428 |
1 |
|
|
T22 |
47 |
|
T18 |
38 |
|
T96 |
48 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1408 |
1 |
|
|
T22 |
53 |
|
T18 |
32 |
|
T96 |
42 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
708 |
1 |
|
|
T22 |
29 |
|
T18 |
11 |
|
T96 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1401 |
1 |
|
|
T22 |
46 |
|
T18 |
38 |
|
T96 |
47 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1373 |
1 |
|
|
T22 |
51 |
|
T18 |
31 |
|
T96 |
42 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
708 |
1 |
|
|
T22 |
29 |
|
T18 |
11 |
|
T96 |
30 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1386 |
1 |
|
|
T22 |
45 |
|
T18 |
38 |
|
T96 |
47 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
713 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1350 |
1 |
|
|
T22 |
49 |
|
T18 |
30 |
|
T96 |
41 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T22 |
29 |
|
T18 |
11 |
|
T96 |
29 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1353 |
1 |
|
|
T22 |
45 |
|
T18 |
37 |
|
T96 |
47 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1324 |
1 |
|
|
T22 |
48 |
|
T18 |
29 |
|
T96 |
41 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T22 |
29 |
|
T18 |
11 |
|
T96 |
29 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1321 |
1 |
|
|
T22 |
42 |
|
T18 |
36 |
|
T96 |
46 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
711 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1298 |
1 |
|
|
T22 |
47 |
|
T18 |
29 |
|
T96 |
41 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T22 |
29 |
|
T18 |
11 |
|
T96 |
29 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1280 |
1 |
|
|
T22 |
40 |
|
T18 |
35 |
|
T96 |
46 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1262 |
1 |
|
|
T22 |
46 |
|
T18 |
28 |
|
T96 |
39 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T22 |
29 |
|
T18 |
11 |
|
T96 |
29 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1247 |
1 |
|
|
T22 |
39 |
|
T18 |
34 |
|
T96 |
46 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1236 |
1 |
|
|
T22 |
46 |
|
T18 |
26 |
|
T96 |
39 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T22 |
29 |
|
T18 |
11 |
|
T96 |
29 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1208 |
1 |
|
|
T22 |
36 |
|
T18 |
32 |
|
T96 |
43 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1193 |
1 |
|
|
T22 |
45 |
|
T18 |
26 |
|
T96 |
37 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T22 |
29 |
|
T18 |
11 |
|
T96 |
29 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1176 |
1 |
|
|
T22 |
34 |
|
T18 |
32 |
|
T96 |
43 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1159 |
1 |
|
|
T22 |
42 |
|
T18 |
26 |
|
T96 |
34 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
701 |
1 |
|
|
T22 |
29 |
|
T18 |
11 |
|
T96 |
29 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1149 |
1 |
|
|
T22 |
33 |
|
T18 |
32 |
|
T96 |
41 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
31 |
all_gpio_pins[10] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1123 |
1 |
|
|
T22 |
42 |
|
T18 |
24 |
|
T96 |
32 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[0] |
auto[0] |
52479 |
1 |
|
|
T22 |
1236 |
|
T18 |
968 |
|
T96 |
2876 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48270 |
1 |
|
|
T22 |
1390 |
|
T18 |
1740 |
|
T96 |
1068 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[1] |
auto[0] |
58187 |
1 |
|
|
T22 |
1365 |
|
T18 |
765 |
|
T96 |
2009 |
all_gpio_pins[11] |
filter_cycles_or_more |
auto[1] |
auto[1] |
42490 |
1 |
|
|
T22 |
2006 |
|
T18 |
806 |
|
T96 |
805 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T22 |
20 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1580 |
1 |
|
|
T22 |
65 |
|
T18 |
38 |
|
T96 |
46 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
744 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1560 |
1 |
|
|
T22 |
65 |
|
T18 |
38 |
|
T96 |
41 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T22 |
20 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1549 |
1 |
|
|
T22 |
64 |
|
T18 |
38 |
|
T96 |
45 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
744 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1534 |
1 |
|
|
T22 |
64 |
|
T18 |
37 |
|
T96 |
41 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T22 |
20 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1520 |
1 |
|
|
T22 |
62 |
|
T18 |
34 |
|
T96 |
45 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
744 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1509 |
1 |
|
|
T22 |
61 |
|
T18 |
37 |
|
T96 |
41 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T22 |
20 |
|
T18 |
15 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1485 |
1 |
|
|
T22 |
62 |
|
T18 |
33 |
|
T96 |
44 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
744 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1480 |
1 |
|
|
T22 |
60 |
|
T18 |
37 |
|
T96 |
41 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1462 |
1 |
|
|
T22 |
62 |
|
T18 |
32 |
|
T96 |
44 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
743 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1447 |
1 |
|
|
T22 |
59 |
|
T18 |
37 |
|
T96 |
39 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
726 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1427 |
1 |
|
|
T22 |
61 |
|
T18 |
32 |
|
T96 |
43 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
743 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1409 |
1 |
|
|
T22 |
59 |
|
T18 |
36 |
|
T96 |
39 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
721 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1390 |
1 |
|
|
T22 |
57 |
|
T18 |
32 |
|
T96 |
42 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1385 |
1 |
|
|
T22 |
58 |
|
T18 |
36 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
721 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1360 |
1 |
|
|
T22 |
56 |
|
T18 |
32 |
|
T96 |
41 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
737 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1350 |
1 |
|
|
T22 |
58 |
|
T18 |
35 |
|
T96 |
35 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1323 |
1 |
|
|
T22 |
55 |
|
T18 |
30 |
|
T96 |
40 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1320 |
1 |
|
|
T22 |
57 |
|
T18 |
32 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1298 |
1 |
|
|
T22 |
54 |
|
T18 |
29 |
|
T96 |
40 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
733 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1292 |
1 |
|
|
T22 |
56 |
|
T18 |
32 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1260 |
1 |
|
|
T22 |
53 |
|
T18 |
29 |
|
T96 |
39 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1258 |
1 |
|
|
T22 |
54 |
|
T18 |
31 |
|
T96 |
32 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
33 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1223 |
1 |
|
|
T22 |
51 |
|
T18 |
28 |
|
T96 |
39 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1237 |
1 |
|
|
T22 |
53 |
|
T18 |
30 |
|
T96 |
28 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
32 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1201 |
1 |
|
|
T22 |
50 |
|
T18 |
27 |
|
T96 |
39 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1205 |
1 |
|
|
T22 |
53 |
|
T18 |
29 |
|
T96 |
27 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
32 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1170 |
1 |
|
|
T22 |
47 |
|
T18 |
25 |
|
T96 |
38 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1172 |
1 |
|
|
T22 |
53 |
|
T18 |
27 |
|
T96 |
27 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
32 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1147 |
1 |
|
|
T22 |
44 |
|
T18 |
25 |
|
T96 |
38 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
731 |
1 |
|
|
T22 |
20 |
|
T18 |
14 |
|
T96 |
37 |
all_gpio_pins[11] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1140 |
1 |
|
|
T22 |
51 |
|
T18 |
27 |
|
T96 |
27 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[0] |
auto[0] |
52631 |
1 |
|
|
T22 |
1649 |
|
T18 |
1038 |
|
T96 |
1578 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[0] |
auto[1] |
47417 |
1 |
|
|
T22 |
1918 |
|
T18 |
843 |
|
T96 |
1106 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[1] |
auto[0] |
52062 |
1 |
|
|
T22 |
1403 |
|
T18 |
892 |
|
T96 |
2904 |
all_gpio_pins[12] |
filter_cycles_or_more |
auto[1] |
auto[1] |
50428 |
1 |
|
|
T22 |
1221 |
|
T18 |
1729 |
|
T96 |
1094 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T22 |
21 |
|
T18 |
17 |
|
T96 |
26 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1617 |
1 |
|
|
T22 |
58 |
|
T18 |
26 |
|
T96 |
56 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1609 |
1 |
|
|
T22 |
59 |
|
T18 |
31 |
|
T96 |
49 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T22 |
21 |
|
T18 |
17 |
|
T96 |
26 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1587 |
1 |
|
|
T22 |
58 |
|
T18 |
26 |
|
T96 |
55 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1569 |
1 |
|
|
T22 |
56 |
|
T18 |
28 |
|
T96 |
47 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T22 |
21 |
|
T18 |
17 |
|
T96 |
26 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1558 |
1 |
|
|
T22 |
56 |
|
T18 |
25 |
|
T96 |
55 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1544 |
1 |
|
|
T22 |
55 |
|
T18 |
28 |
|
T96 |
47 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T22 |
21 |
|
T18 |
17 |
|
T96 |
26 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1525 |
1 |
|
|
T22 |
55 |
|
T18 |
25 |
|
T96 |
52 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1506 |
1 |
|
|
T22 |
54 |
|
T18 |
28 |
|
T96 |
47 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
655 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1501 |
1 |
|
|
T22 |
55 |
|
T18 |
24 |
|
T96 |
51 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1478 |
1 |
|
|
T22 |
52 |
|
T18 |
28 |
|
T96 |
47 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
655 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1476 |
1 |
|
|
T22 |
55 |
|
T18 |
24 |
|
T96 |
49 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1440 |
1 |
|
|
T22 |
49 |
|
T18 |
28 |
|
T96 |
45 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
650 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1437 |
1 |
|
|
T22 |
54 |
|
T18 |
24 |
|
T96 |
49 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
655 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1409 |
1 |
|
|
T22 |
48 |
|
T18 |
27 |
|
T96 |
44 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
650 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T22 |
54 |
|
T18 |
23 |
|
T96 |
48 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
655 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1378 |
1 |
|
|
T22 |
47 |
|
T18 |
27 |
|
T96 |
44 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
644 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
25 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1382 |
1 |
|
|
T22 |
54 |
|
T18 |
22 |
|
T96 |
48 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1340 |
1 |
|
|
T22 |
46 |
|
T18 |
27 |
|
T96 |
44 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
644 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
25 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1354 |
1 |
|
|
T22 |
48 |
|
T18 |
22 |
|
T96 |
48 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1320 |
1 |
|
|
T22 |
46 |
|
T18 |
27 |
|
T96 |
43 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
641 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
25 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1325 |
1 |
|
|
T22 |
48 |
|
T18 |
21 |
|
T96 |
45 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1282 |
1 |
|
|
T22 |
45 |
|
T18 |
26 |
|
T96 |
42 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
641 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
25 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1287 |
1 |
|
|
T22 |
47 |
|
T18 |
19 |
|
T96 |
45 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1255 |
1 |
|
|
T22 |
44 |
|
T18 |
25 |
|
T96 |
42 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
641 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
25 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1253 |
1 |
|
|
T22 |
47 |
|
T18 |
19 |
|
T96 |
44 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1222 |
1 |
|
|
T22 |
44 |
|
T18 |
25 |
|
T96 |
40 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
641 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
25 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1229 |
1 |
|
|
T22 |
46 |
|
T18 |
19 |
|
T96 |
42 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1199 |
1 |
|
|
T22 |
43 |
|
T18 |
25 |
|
T96 |
40 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
641 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
25 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T22 |
44 |
|
T18 |
18 |
|
T96 |
41 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
653 |
1 |
|
|
T22 |
19 |
|
T18 |
12 |
|
T96 |
33 |
all_gpio_pins[12] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1173 |
1 |
|
|
T22 |
43 |
|
T18 |
25 |
|
T96 |
40 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[0] |
auto[0] |
54685 |
1 |
|
|
T22 |
1543 |
|
T18 |
687 |
|
T96 |
1200 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[0] |
auto[1] |
44782 |
1 |
|
|
T22 |
1526 |
|
T18 |
863 |
|
T96 |
1400 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[1] |
auto[0] |
53298 |
1 |
|
|
T22 |
1012 |
|
T18 |
1995 |
|
T96 |
2658 |
all_gpio_pins[13] |
filter_cycles_or_more |
auto[1] |
auto[1] |
48495 |
1 |
|
|
T22 |
2007 |
|
T18 |
848 |
|
T96 |
1205 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
13 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1641 |
1 |
|
|
T22 |
71 |
|
T18 |
37 |
|
T96 |
59 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
640 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1671 |
1 |
|
|
T22 |
69 |
|
T18 |
35 |
|
T96 |
60 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
13 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1612 |
1 |
|
|
T22 |
71 |
|
T18 |
36 |
|
T96 |
59 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
640 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1641 |
1 |
|
|
T22 |
65 |
|
T18 |
34 |
|
T96 |
60 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
13 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1584 |
1 |
|
|
T22 |
71 |
|
T18 |
34 |
|
T96 |
59 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
640 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1612 |
1 |
|
|
T22 |
64 |
|
T18 |
33 |
|
T96 |
58 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
13 |
|
T18 |
13 |
|
T96 |
30 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1556 |
1 |
|
|
T22 |
71 |
|
T18 |
34 |
|
T96 |
59 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
640 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1579 |
1 |
|
|
T22 |
62 |
|
T18 |
33 |
|
T96 |
57 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T22 |
13 |
|
T18 |
12 |
|
T96 |
30 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1527 |
1 |
|
|
T22 |
69 |
|
T18 |
31 |
|
T96 |
59 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
636 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1548 |
1 |
|
|
T22 |
59 |
|
T18 |
31 |
|
T96 |
54 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T22 |
13 |
|
T18 |
12 |
|
T96 |
30 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1497 |
1 |
|
|
T22 |
68 |
|
T18 |
31 |
|
T96 |
58 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
636 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1510 |
1 |
|
|
T22 |
58 |
|
T18 |
28 |
|
T96 |
53 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
667 |
1 |
|
|
T22 |
13 |
|
T18 |
12 |
|
T96 |
30 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1464 |
1 |
|
|
T22 |
67 |
|
T18 |
31 |
|
T96 |
58 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
632 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1480 |
1 |
|
|
T22 |
55 |
|
T18 |
27 |
|
T96 |
52 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
667 |
1 |
|
|
T22 |
13 |
|
T18 |
12 |
|
T96 |
30 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1437 |
1 |
|
|
T22 |
66 |
|
T18 |
31 |
|
T96 |
57 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
632 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1453 |
1 |
|
|
T22 |
55 |
|
T18 |
26 |
|
T96 |
50 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
664 |
1 |
|
|
T22 |
13 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1405 |
1 |
|
|
T22 |
64 |
|
T18 |
31 |
|
T96 |
58 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
632 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1433 |
1 |
|
|
T22 |
54 |
|
T18 |
23 |
|
T96 |
49 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
664 |
1 |
|
|
T22 |
13 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1369 |
1 |
|
|
T22 |
61 |
|
T18 |
29 |
|
T96 |
58 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
632 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1402 |
1 |
|
|
T22 |
52 |
|
T18 |
22 |
|
T96 |
47 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T22 |
13 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1331 |
1 |
|
|
T22 |
60 |
|
T18 |
29 |
|
T96 |
56 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
632 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1370 |
1 |
|
|
T22 |
49 |
|
T18 |
22 |
|
T96 |
46 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T22 |
13 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1287 |
1 |
|
|
T22 |
58 |
|
T18 |
29 |
|
T96 |
54 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
632 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1331 |
1 |
|
|
T22 |
48 |
|
T18 |
21 |
|
T96 |
44 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T22 |
13 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1251 |
1 |
|
|
T22 |
57 |
|
T18 |
29 |
|
T96 |
54 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
631 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1303 |
1 |
|
|
T22 |
47 |
|
T18 |
21 |
|
T96 |
44 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T22 |
13 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1211 |
1 |
|
|
T22 |
54 |
|
T18 |
28 |
|
T96 |
51 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
631 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1274 |
1 |
|
|
T22 |
47 |
|
T18 |
21 |
|
T96 |
43 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
659 |
1 |
|
|
T22 |
13 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1183 |
1 |
|
|
T22 |
54 |
|
T18 |
28 |
|
T96 |
50 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
631 |
1 |
|
|
T22 |
15 |
|
T18 |
15 |
|
T96 |
29 |
all_gpio_pins[13] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1250 |
1 |
|
|
T22 |
47 |
|
T18 |
21 |
|
T96 |
42 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[0] |
auto[0] |
55411 |
1 |
|
|
T22 |
1376 |
|
T18 |
2137 |
|
T96 |
2240 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[0] |
auto[1] |
43456 |
1 |
|
|
T22 |
1343 |
|
T18 |
712 |
|
T96 |
2073 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[1] |
auto[0] |
51556 |
1 |
|
|
T22 |
1186 |
|
T18 |
778 |
|
T96 |
1436 |
all_gpio_pins[14] |
filter_cycles_or_more |
auto[1] |
auto[1] |
51396 |
1 |
|
|
T22 |
2066 |
|
T18 |
706 |
|
T96 |
1155 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
25 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1583 |
1 |
|
|
T22 |
67 |
|
T18 |
32 |
|
T96 |
50 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1573 |
1 |
|
|
T22 |
71 |
|
T18 |
32 |
|
T96 |
45 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
25 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1549 |
1 |
|
|
T22 |
66 |
|
T18 |
31 |
|
T96 |
48 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1544 |
1 |
|
|
T22 |
70 |
|
T18 |
31 |
|
T96 |
44 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
698 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
25 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1523 |
1 |
|
|
T22 |
66 |
|
T18 |
30 |
|
T96 |
46 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1521 |
1 |
|
|
T22 |
69 |
|
T18 |
31 |
|
T96 |
44 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
698 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
25 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1492 |
1 |
|
|
T22 |
62 |
|
T18 |
30 |
|
T96 |
43 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
707 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1495 |
1 |
|
|
T22 |
69 |
|
T18 |
31 |
|
T96 |
43 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
25 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1467 |
1 |
|
|
T22 |
61 |
|
T18 |
30 |
|
T96 |
43 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
705 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1472 |
1 |
|
|
T22 |
68 |
|
T18 |
31 |
|
T96 |
43 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
25 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1441 |
1 |
|
|
T22 |
60 |
|
T18 |
29 |
|
T96 |
42 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
705 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1446 |
1 |
|
|
T22 |
68 |
|
T18 |
29 |
|
T96 |
43 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
25 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T22 |
59 |
|
T18 |
27 |
|
T96 |
42 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
702 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1419 |
1 |
|
|
T22 |
65 |
|
T18 |
29 |
|
T96 |
43 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
25 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1384 |
1 |
|
|
T22 |
57 |
|
T18 |
26 |
|
T96 |
40 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
702 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1393 |
1 |
|
|
T22 |
63 |
|
T18 |
29 |
|
T96 |
41 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
19 |
|
T18 |
17 |
|
T96 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1355 |
1 |
|
|
T22 |
56 |
|
T18 |
26 |
|
T96 |
40 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
701 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1353 |
1 |
|
|
T22 |
61 |
|
T18 |
29 |
|
T96 |
40 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
19 |
|
T18 |
17 |
|
T96 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1318 |
1 |
|
|
T22 |
55 |
|
T18 |
26 |
|
T96 |
39 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
701 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1323 |
1 |
|
|
T22 |
60 |
|
T18 |
28 |
|
T96 |
40 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
681 |
1 |
|
|
T22 |
19 |
|
T18 |
17 |
|
T96 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1282 |
1 |
|
|
T22 |
54 |
|
T18 |
25 |
|
T96 |
39 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1294 |
1 |
|
|
T22 |
58 |
|
T18 |
28 |
|
T96 |
40 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
681 |
1 |
|
|
T22 |
19 |
|
T18 |
17 |
|
T96 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1252 |
1 |
|
|
T22 |
53 |
|
T18 |
24 |
|
T96 |
38 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1267 |
1 |
|
|
T22 |
56 |
|
T18 |
28 |
|
T96 |
40 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
681 |
1 |
|
|
T22 |
19 |
|
T18 |
17 |
|
T96 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1208 |
1 |
|
|
T22 |
50 |
|
T18 |
22 |
|
T96 |
37 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
698 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1244 |
1 |
|
|
T22 |
55 |
|
T18 |
28 |
|
T96 |
40 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
681 |
1 |
|
|
T22 |
19 |
|
T18 |
17 |
|
T96 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1166 |
1 |
|
|
T22 |
46 |
|
T18 |
22 |
|
T96 |
36 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
698 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1217 |
1 |
|
|
T22 |
53 |
|
T18 |
27 |
|
T96 |
40 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
681 |
1 |
|
|
T22 |
19 |
|
T18 |
17 |
|
T96 |
24 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1125 |
1 |
|
|
T22 |
46 |
|
T18 |
22 |
|
T96 |
35 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
698 |
1 |
|
|
T22 |
16 |
|
T18 |
16 |
|
T96 |
29 |
all_gpio_pins[14] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1189 |
1 |
|
|
T22 |
53 |
|
T18 |
27 |
|
T96 |
38 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[0] |
auto[0] |
53600 |
1 |
|
|
T22 |
2044 |
|
T18 |
949 |
|
T96 |
1566 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46319 |
1 |
|
|
T22 |
1501 |
|
T18 |
686 |
|
T96 |
2279 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56576 |
1 |
|
|
T22 |
1785 |
|
T18 |
2306 |
|
T96 |
1762 |
all_gpio_pins[15] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44576 |
1 |
|
|
T22 |
948 |
|
T18 |
386 |
|
T96 |
1232 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
740 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
20 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1581 |
1 |
|
|
T22 |
43 |
|
T18 |
27 |
|
T96 |
58 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1591 |
1 |
|
|
T22 |
40 |
|
T18 |
24 |
|
T96 |
56 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
740 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
20 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1554 |
1 |
|
|
T22 |
43 |
|
T18 |
27 |
|
T96 |
57 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1563 |
1 |
|
|
T22 |
39 |
|
T18 |
24 |
|
T96 |
56 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
740 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
20 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1520 |
1 |
|
|
T22 |
43 |
|
T18 |
27 |
|
T96 |
57 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1532 |
1 |
|
|
T22 |
39 |
|
T18 |
24 |
|
T96 |
55 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
740 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
20 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1483 |
1 |
|
|
T22 |
42 |
|
T18 |
27 |
|
T96 |
56 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
723 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1506 |
1 |
|
|
T22 |
39 |
|
T18 |
23 |
|
T96 |
55 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
734 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
20 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1459 |
1 |
|
|
T22 |
40 |
|
T18 |
26 |
|
T96 |
55 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1473 |
1 |
|
|
T22 |
37 |
|
T18 |
23 |
|
T96 |
55 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
734 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
20 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1429 |
1 |
|
|
T22 |
39 |
|
T18 |
26 |
|
T96 |
53 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
721 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1451 |
1 |
|
|
T22 |
37 |
|
T18 |
21 |
|
T96 |
51 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
727 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
20 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1399 |
1 |
|
|
T22 |
39 |
|
T18 |
25 |
|
T96 |
52 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1419 |
1 |
|
|
T22 |
35 |
|
T18 |
20 |
|
T96 |
49 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
727 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
20 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1366 |
1 |
|
|
T22 |
39 |
|
T18 |
25 |
|
T96 |
51 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
719 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1389 |
1 |
|
|
T22 |
34 |
|
T18 |
20 |
|
T96 |
49 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
19 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1343 |
1 |
|
|
T22 |
39 |
|
T18 |
24 |
|
T96 |
51 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
718 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1353 |
1 |
|
|
T22 |
33 |
|
T18 |
20 |
|
T96 |
48 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
720 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
19 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1314 |
1 |
|
|
T22 |
38 |
|
T18 |
24 |
|
T96 |
51 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
718 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1313 |
1 |
|
|
T22 |
33 |
|
T18 |
20 |
|
T96 |
47 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
19 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1283 |
1 |
|
|
T22 |
38 |
|
T18 |
23 |
|
T96 |
48 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1278 |
1 |
|
|
T22 |
30 |
|
T18 |
17 |
|
T96 |
44 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
19 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1250 |
1 |
|
|
T22 |
37 |
|
T18 |
23 |
|
T96 |
47 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
716 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1250 |
1 |
|
|
T22 |
28 |
|
T18 |
16 |
|
T96 |
43 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
19 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1224 |
1 |
|
|
T22 |
37 |
|
T18 |
22 |
|
T96 |
47 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1212 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
43 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
19 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1191 |
1 |
|
|
T22 |
36 |
|
T18 |
22 |
|
T96 |
44 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1182 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
42 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
719 |
1 |
|
|
T22 |
30 |
|
T18 |
21 |
|
T96 |
19 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1158 |
1 |
|
|
T22 |
36 |
|
T18 |
21 |
|
T96 |
44 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
715 |
1 |
|
|
T22 |
32 |
|
T18 |
24 |
|
T96 |
21 |
all_gpio_pins[15] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1151 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
38 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[0] |
auto[0] |
60939 |
1 |
|
|
T22 |
1359 |
|
T18 |
1958 |
|
T96 |
2466 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[0] |
auto[1] |
44238 |
1 |
|
|
T22 |
1657 |
|
T18 |
683 |
|
T96 |
1120 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[1] |
auto[0] |
53234 |
1 |
|
|
T22 |
1834 |
|
T18 |
1296 |
|
T96 |
2375 |
all_gpio_pins[16] |
filter_cycles_or_more |
auto[1] |
auto[1] |
44624 |
1 |
|
|
T22 |
1208 |
|
T18 |
642 |
|
T96 |
996 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
700 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1559 |
1 |
|
|
T22 |
56 |
|
T18 |
29 |
|
T96 |
43 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1554 |
1 |
|
|
T22 |
51 |
|
T18 |
26 |
|
T96 |
44 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
700 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1522 |
1 |
|
|
T22 |
56 |
|
T18 |
28 |
|
T96 |
42 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1526 |
1 |
|
|
T22 |
51 |
|
T18 |
26 |
|
T96 |
44 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1488 |
1 |
|
|
T22 |
52 |
|
T18 |
28 |
|
T96 |
42 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1498 |
1 |
|
|
T22 |
51 |
|
T18 |
25 |
|
T96 |
44 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1456 |
1 |
|
|
T22 |
51 |
|
T18 |
26 |
|
T96 |
41 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1475 |
1 |
|
|
T22 |
50 |
|
T18 |
25 |
|
T96 |
44 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
698 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1423 |
1 |
|
|
T22 |
51 |
|
T18 |
25 |
|
T96 |
40 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1443 |
1 |
|
|
T22 |
50 |
|
T18 |
24 |
|
T96 |
42 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
698 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1388 |
1 |
|
|
T22 |
48 |
|
T18 |
24 |
|
T96 |
39 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1412 |
1 |
|
|
T22 |
50 |
|
T18 |
23 |
|
T96 |
41 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1351 |
1 |
|
|
T22 |
46 |
|
T18 |
22 |
|
T96 |
39 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1383 |
1 |
|
|
T22 |
48 |
|
T18 |
23 |
|
T96 |
39 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1318 |
1 |
|
|
T22 |
45 |
|
T18 |
22 |
|
T96 |
38 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1355 |
1 |
|
|
T22 |
47 |
|
T18 |
23 |
|
T96 |
39 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1289 |
1 |
|
|
T22 |
44 |
|
T18 |
22 |
|
T96 |
37 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1328 |
1 |
|
|
T22 |
47 |
|
T18 |
23 |
|
T96 |
39 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1255 |
1 |
|
|
T22 |
42 |
|
T18 |
22 |
|
T96 |
37 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1299 |
1 |
|
|
T22 |
47 |
|
T18 |
22 |
|
T96 |
37 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1226 |
1 |
|
|
T22 |
41 |
|
T18 |
22 |
|
T96 |
37 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1268 |
1 |
|
|
T22 |
45 |
|
T18 |
22 |
|
T96 |
36 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T22 |
41 |
|
T18 |
22 |
|
T96 |
37 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1238 |
1 |
|
|
T22 |
44 |
|
T18 |
22 |
|
T96 |
34 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1176 |
1 |
|
|
T22 |
41 |
|
T18 |
21 |
|
T96 |
36 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1212 |
1 |
|
|
T22 |
44 |
|
T18 |
21 |
|
T96 |
31 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1151 |
1 |
|
|
T22 |
40 |
|
T18 |
21 |
|
T96 |
36 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1175 |
1 |
|
|
T22 |
44 |
|
T18 |
20 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
29 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1125 |
1 |
|
|
T22 |
38 |
|
T18 |
20 |
|
T96 |
36 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
30 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[16] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1143 |
1 |
|
|
T22 |
42 |
|
T18 |
20 |
|
T96 |
29 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58056 |
1 |
|
|
T22 |
1533 |
|
T18 |
622 |
|
T96 |
1705 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[0] |
auto[1] |
47151 |
1 |
|
|
T22 |
1409 |
|
T18 |
1794 |
|
T96 |
2254 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[1] |
auto[0] |
54020 |
1 |
|
|
T22 |
1472 |
|
T18 |
794 |
|
T96 |
1482 |
all_gpio_pins[17] |
filter_cycles_or_more |
auto[1] |
auto[1] |
43202 |
1 |
|
|
T22 |
1669 |
|
T18 |
1054 |
|
T96 |
1304 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T22 |
20 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1600 |
1 |
|
|
T22 |
63 |
|
T18 |
40 |
|
T96 |
59 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1590 |
1 |
|
|
T22 |
61 |
|
T18 |
38 |
|
T96 |
58 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
692 |
1 |
|
|
T22 |
20 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1562 |
1 |
|
|
T22 |
62 |
|
T18 |
39 |
|
T96 |
57 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1551 |
1 |
|
|
T22 |
60 |
|
T18 |
38 |
|
T96 |
58 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
691 |
1 |
|
|
T22 |
20 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1530 |
1 |
|
|
T22 |
61 |
|
T18 |
39 |
|
T96 |
56 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1518 |
1 |
|
|
T22 |
60 |
|
T18 |
38 |
|
T96 |
56 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
691 |
1 |
|
|
T22 |
20 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1499 |
1 |
|
|
T22 |
59 |
|
T18 |
39 |
|
T96 |
54 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1481 |
1 |
|
|
T22 |
56 |
|
T18 |
38 |
|
T96 |
55 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1474 |
1 |
|
|
T22 |
59 |
|
T18 |
39 |
|
T96 |
51 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1452 |
1 |
|
|
T22 |
54 |
|
T18 |
37 |
|
T96 |
55 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1439 |
1 |
|
|
T22 |
57 |
|
T18 |
39 |
|
T96 |
50 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1419 |
1 |
|
|
T22 |
52 |
|
T18 |
37 |
|
T96 |
54 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
684 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1413 |
1 |
|
|
T22 |
57 |
|
T18 |
37 |
|
T96 |
48 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1382 |
1 |
|
|
T22 |
52 |
|
T18 |
36 |
|
T96 |
50 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
684 |
1 |
|
|
T22 |
20 |
|
T18 |
11 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1383 |
1 |
|
|
T22 |
56 |
|
T18 |
36 |
|
T96 |
48 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1351 |
1 |
|
|
T22 |
51 |
|
T18 |
36 |
|
T96 |
49 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T22 |
19 |
|
T18 |
11 |
|
T96 |
23 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1359 |
1 |
|
|
T22 |
55 |
|
T18 |
34 |
|
T96 |
48 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1310 |
1 |
|
|
T22 |
50 |
|
T18 |
35 |
|
T96 |
49 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T22 |
19 |
|
T18 |
11 |
|
T96 |
23 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1323 |
1 |
|
|
T22 |
55 |
|
T18 |
33 |
|
T96 |
44 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1277 |
1 |
|
|
T22 |
48 |
|
T18 |
33 |
|
T96 |
49 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
672 |
1 |
|
|
T22 |
19 |
|
T18 |
11 |
|
T96 |
23 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1291 |
1 |
|
|
T22 |
53 |
|
T18 |
32 |
|
T96 |
43 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
688 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1240 |
1 |
|
|
T22 |
47 |
|
T18 |
33 |
|
T96 |
48 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
672 |
1 |
|
|
T22 |
19 |
|
T18 |
11 |
|
T96 |
23 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1256 |
1 |
|
|
T22 |
51 |
|
T18 |
30 |
|
T96 |
43 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
688 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1209 |
1 |
|
|
T22 |
47 |
|
T18 |
30 |
|
T96 |
47 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T22 |
19 |
|
T18 |
11 |
|
T96 |
23 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1230 |
1 |
|
|
T22 |
50 |
|
T18 |
29 |
|
T96 |
41 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1172 |
1 |
|
|
T22 |
43 |
|
T18 |
30 |
|
T96 |
47 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T22 |
19 |
|
T18 |
11 |
|
T96 |
23 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1208 |
1 |
|
|
T22 |
48 |
|
T18 |
29 |
|
T96 |
41 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1145 |
1 |
|
|
T22 |
41 |
|
T18 |
29 |
|
T96 |
47 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
671 |
1 |
|
|
T22 |
19 |
|
T18 |
11 |
|
T96 |
23 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1188 |
1 |
|
|
T22 |
47 |
|
T18 |
28 |
|
T96 |
40 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[17] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1123 |
1 |
|
|
T22 |
40 |
|
T18 |
29 |
|
T96 |
46 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[0] |
auto[0] |
48676 |
1 |
|
|
T22 |
1360 |
|
T18 |
705 |
|
T96 |
1721 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[0] |
auto[1] |
47871 |
1 |
|
|
T22 |
1429 |
|
T18 |
826 |
|
T96 |
1178 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[1] |
auto[0] |
58545 |
1 |
|
|
T22 |
1243 |
|
T18 |
955 |
|
T96 |
3043 |
all_gpio_pins[18] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46168 |
1 |
|
|
T22 |
1853 |
|
T18 |
1789 |
|
T96 |
945 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
640 |
1 |
|
|
T22 |
19 |
|
T18 |
14 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1689 |
1 |
|
|
T22 |
70 |
|
T18 |
40 |
|
T96 |
51 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1632 |
1 |
|
|
T22 |
63 |
|
T18 |
41 |
|
T96 |
50 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
640 |
1 |
|
|
T22 |
19 |
|
T18 |
14 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1658 |
1 |
|
|
T22 |
70 |
|
T18 |
38 |
|
T96 |
51 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1601 |
1 |
|
|
T22 |
61 |
|
T18 |
41 |
|
T96 |
48 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
640 |
1 |
|
|
T22 |
19 |
|
T18 |
14 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1633 |
1 |
|
|
T22 |
70 |
|
T18 |
38 |
|
T96 |
51 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1563 |
1 |
|
|
T22 |
60 |
|
T18 |
41 |
|
T96 |
48 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
640 |
1 |
|
|
T22 |
19 |
|
T18 |
14 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1601 |
1 |
|
|
T22 |
70 |
|
T18 |
35 |
|
T96 |
51 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1532 |
1 |
|
|
T22 |
59 |
|
T18 |
40 |
|
T96 |
45 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
635 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1569 |
1 |
|
|
T22 |
68 |
|
T18 |
34 |
|
T96 |
51 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1500 |
1 |
|
|
T22 |
59 |
|
T18 |
35 |
|
T96 |
43 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
635 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1533 |
1 |
|
|
T22 |
65 |
|
T18 |
32 |
|
T96 |
49 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
690 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1474 |
1 |
|
|
T22 |
58 |
|
T18 |
35 |
|
T96 |
41 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
630 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1480 |
1 |
|
|
T22 |
61 |
|
T18 |
30 |
|
T96 |
48 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1445 |
1 |
|
|
T22 |
57 |
|
T18 |
35 |
|
T96 |
41 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
630 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1448 |
1 |
|
|
T22 |
58 |
|
T18 |
29 |
|
T96 |
48 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1411 |
1 |
|
|
T22 |
57 |
|
T18 |
35 |
|
T96 |
37 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
626 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1418 |
1 |
|
|
T22 |
57 |
|
T18 |
27 |
|
T96 |
47 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1385 |
1 |
|
|
T22 |
56 |
|
T18 |
35 |
|
T96 |
37 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
626 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1387 |
1 |
|
|
T22 |
56 |
|
T18 |
27 |
|
T96 |
46 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1348 |
1 |
|
|
T22 |
53 |
|
T18 |
35 |
|
T96 |
36 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
621 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1340 |
1 |
|
|
T22 |
54 |
|
T18 |
27 |
|
T96 |
45 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1311 |
1 |
|
|
T22 |
52 |
|
T18 |
34 |
|
T96 |
36 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
621 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1311 |
1 |
|
|
T22 |
53 |
|
T18 |
27 |
|
T96 |
44 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1287 |
1 |
|
|
T22 |
52 |
|
T18 |
34 |
|
T96 |
35 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
619 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1273 |
1 |
|
|
T22 |
53 |
|
T18 |
25 |
|
T96 |
41 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1267 |
1 |
|
|
T22 |
51 |
|
T18 |
34 |
|
T96 |
35 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
619 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1246 |
1 |
|
|
T22 |
53 |
|
T18 |
25 |
|
T96 |
41 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1228 |
1 |
|
|
T22 |
49 |
|
T18 |
33 |
|
T96 |
32 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
619 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1216 |
1 |
|
|
T22 |
51 |
|
T18 |
25 |
|
T96 |
41 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
26 |
all_gpio_pins[18] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1190 |
1 |
|
|
T22 |
45 |
|
T18 |
32 |
|
T96 |
31 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[0] |
auto[0] |
57231 |
1 |
|
|
T22 |
1774 |
|
T18 |
632 |
|
T96 |
1552 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[0] |
auto[1] |
37918 |
1 |
|
|
T22 |
1937 |
|
T18 |
1894 |
|
T96 |
1201 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[1] |
auto[0] |
56196 |
1 |
|
|
T22 |
1358 |
|
T18 |
720 |
|
T96 |
2517 |
all_gpio_pins[19] |
filter_cycles_or_more |
auto[1] |
auto[1] |
49492 |
1 |
|
|
T22 |
989 |
|
T18 |
952 |
|
T96 |
1411 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T22 |
24 |
|
T18 |
17 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1637 |
1 |
|
|
T22 |
57 |
|
T18 |
40 |
|
T96 |
66 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1651 |
1 |
|
|
T22 |
54 |
|
T18 |
44 |
|
T96 |
68 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T22 |
24 |
|
T18 |
17 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1605 |
1 |
|
|
T22 |
57 |
|
T18 |
36 |
|
T96 |
62 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1617 |
1 |
|
|
T22 |
53 |
|
T18 |
43 |
|
T96 |
67 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
24 |
|
T18 |
17 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1567 |
1 |
|
|
T22 |
57 |
|
T18 |
35 |
|
T96 |
59 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1586 |
1 |
|
|
T22 |
53 |
|
T18 |
41 |
|
T96 |
67 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
24 |
|
T18 |
17 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1547 |
1 |
|
|
T22 |
56 |
|
T18 |
35 |
|
T96 |
59 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1557 |
1 |
|
|
T22 |
52 |
|
T18 |
41 |
|
T96 |
64 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1522 |
1 |
|
|
T22 |
56 |
|
T18 |
35 |
|
T96 |
59 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1531 |
1 |
|
|
T22 |
52 |
|
T18 |
41 |
|
T96 |
64 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
688 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1481 |
1 |
|
|
T22 |
55 |
|
T18 |
34 |
|
T96 |
56 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1502 |
1 |
|
|
T22 |
51 |
|
T18 |
40 |
|
T96 |
62 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
684 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1453 |
1 |
|
|
T22 |
55 |
|
T18 |
32 |
|
T96 |
55 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
676 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1476 |
1 |
|
|
T22 |
50 |
|
T18 |
38 |
|
T96 |
60 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
684 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1418 |
1 |
|
|
T22 |
55 |
|
T18 |
31 |
|
T96 |
54 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
676 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1453 |
1 |
|
|
T22 |
50 |
|
T18 |
37 |
|
T96 |
60 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1376 |
1 |
|
|
T22 |
54 |
|
T18 |
30 |
|
T96 |
52 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
674 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1417 |
1 |
|
|
T22 |
47 |
|
T18 |
37 |
|
T96 |
57 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1352 |
1 |
|
|
T22 |
54 |
|
T18 |
30 |
|
T96 |
51 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
674 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1386 |
1 |
|
|
T22 |
43 |
|
T18 |
37 |
|
T96 |
56 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1321 |
1 |
|
|
T22 |
52 |
|
T18 |
30 |
|
T96 |
51 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1355 |
1 |
|
|
T22 |
40 |
|
T18 |
35 |
|
T96 |
55 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1277 |
1 |
|
|
T22 |
52 |
|
T18 |
29 |
|
T96 |
51 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1308 |
1 |
|
|
T22 |
40 |
|
T18 |
34 |
|
T96 |
54 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1242 |
1 |
|
|
T22 |
49 |
|
T18 |
29 |
|
T96 |
49 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1278 |
1 |
|
|
T22 |
38 |
|
T18 |
32 |
|
T96 |
53 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T22 |
47 |
|
T18 |
28 |
|
T96 |
45 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1239 |
1 |
|
|
T22 |
34 |
|
T18 |
32 |
|
T96 |
50 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
24 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1170 |
1 |
|
|
T22 |
46 |
|
T18 |
28 |
|
T96 |
43 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
18 |
all_gpio_pins[19] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1211 |
1 |
|
|
T22 |
34 |
|
T18 |
32 |
|
T96 |
49 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[0] |
auto[0] |
59259 |
1 |
|
|
T22 |
1728 |
|
T18 |
1810 |
|
T96 |
2470 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[0] |
auto[1] |
45637 |
1 |
|
|
T22 |
1093 |
|
T18 |
810 |
|
T96 |
1234 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55586 |
1 |
|
|
T22 |
2191 |
|
T18 |
985 |
|
T96 |
1784 |
all_gpio_pins[20] |
filter_cycles_or_more |
auto[1] |
auto[1] |
40237 |
1 |
|
|
T22 |
1157 |
|
T18 |
757 |
|
T96 |
1283 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
732 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1592 |
1 |
|
|
T22 |
51 |
|
T18 |
31 |
|
T96 |
52 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1614 |
1 |
|
|
T22 |
52 |
|
T18 |
32 |
|
T96 |
54 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
732 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1568 |
1 |
|
|
T22 |
49 |
|
T18 |
31 |
|
T96 |
50 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1591 |
1 |
|
|
T22 |
52 |
|
T18 |
32 |
|
T96 |
53 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1545 |
1 |
|
|
T22 |
48 |
|
T18 |
31 |
|
T96 |
48 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1572 |
1 |
|
|
T22 |
51 |
|
T18 |
32 |
|
T96 |
53 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
731 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1510 |
1 |
|
|
T22 |
47 |
|
T18 |
28 |
|
T96 |
46 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
699 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1536 |
1 |
|
|
T22 |
50 |
|
T18 |
29 |
|
T96 |
51 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
729 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1480 |
1 |
|
|
T22 |
46 |
|
T18 |
28 |
|
T96 |
45 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1511 |
1 |
|
|
T22 |
50 |
|
T18 |
28 |
|
T96 |
50 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
729 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1457 |
1 |
|
|
T22 |
44 |
|
T18 |
28 |
|
T96 |
45 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1479 |
1 |
|
|
T22 |
48 |
|
T18 |
27 |
|
T96 |
50 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1437 |
1 |
|
|
T22 |
44 |
|
T18 |
28 |
|
T96 |
43 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1450 |
1 |
|
|
T22 |
48 |
|
T18 |
27 |
|
T96 |
48 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
722 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1407 |
1 |
|
|
T22 |
44 |
|
T18 |
28 |
|
T96 |
41 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1417 |
1 |
|
|
T22 |
45 |
|
T18 |
26 |
|
T96 |
47 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1376 |
1 |
|
|
T22 |
43 |
|
T18 |
28 |
|
T96 |
41 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1385 |
1 |
|
|
T22 |
44 |
|
T18 |
26 |
|
T96 |
47 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
717 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1342 |
1 |
|
|
T22 |
40 |
|
T18 |
27 |
|
T96 |
40 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1351 |
1 |
|
|
T22 |
44 |
|
T18 |
26 |
|
T96 |
45 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1305 |
1 |
|
|
T22 |
40 |
|
T18 |
27 |
|
T96 |
39 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1318 |
1 |
|
|
T22 |
44 |
|
T18 |
26 |
|
T96 |
45 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
713 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
29 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1273 |
1 |
|
|
T22 |
39 |
|
T18 |
26 |
|
T96 |
38 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1281 |
1 |
|
|
T22 |
42 |
|
T18 |
25 |
|
T96 |
45 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1238 |
1 |
|
|
T22 |
37 |
|
T18 |
26 |
|
T96 |
37 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1242 |
1 |
|
|
T22 |
42 |
|
T18 |
25 |
|
T96 |
43 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1214 |
1 |
|
|
T22 |
35 |
|
T18 |
24 |
|
T96 |
37 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1216 |
1 |
|
|
T22 |
42 |
|
T18 |
25 |
|
T96 |
43 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
712 |
1 |
|
|
T22 |
27 |
|
T18 |
17 |
|
T96 |
28 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1176 |
1 |
|
|
T22 |
34 |
|
T18 |
24 |
|
T96 |
37 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
26 |
all_gpio_pins[20] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1184 |
1 |
|
|
T22 |
42 |
|
T18 |
25 |
|
T96 |
43 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[0] |
auto[0] |
56052 |
1 |
|
|
T22 |
1721 |
|
T18 |
1036 |
|
T96 |
1519 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48469 |
1 |
|
|
T22 |
1894 |
|
T18 |
1762 |
|
T96 |
1034 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[1] |
auto[0] |
49719 |
1 |
|
|
T22 |
1467 |
|
T18 |
797 |
|
T96 |
1405 |
all_gpio_pins[21] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46897 |
1 |
|
|
T22 |
1165 |
|
T18 |
682 |
|
T96 |
2501 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T22 |
22 |
|
T18 |
18 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1640 |
1 |
|
|
T22 |
55 |
|
T18 |
34 |
|
T96 |
71 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
675 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1653 |
1 |
|
|
T22 |
57 |
|
T18 |
38 |
|
T96 |
69 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T22 |
22 |
|
T18 |
18 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1604 |
1 |
|
|
T22 |
54 |
|
T18 |
34 |
|
T96 |
68 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
675 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1619 |
1 |
|
|
T22 |
57 |
|
T18 |
38 |
|
T96 |
68 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T22 |
22 |
|
T18 |
18 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1574 |
1 |
|
|
T22 |
53 |
|
T18 |
34 |
|
T96 |
65 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
675 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1588 |
1 |
|
|
T22 |
56 |
|
T18 |
38 |
|
T96 |
66 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T22 |
22 |
|
T18 |
18 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1540 |
1 |
|
|
T22 |
52 |
|
T18 |
34 |
|
T96 |
63 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
675 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1560 |
1 |
|
|
T22 |
55 |
|
T18 |
38 |
|
T96 |
66 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1523 |
1 |
|
|
T22 |
52 |
|
T18 |
34 |
|
T96 |
63 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1525 |
1 |
|
|
T22 |
52 |
|
T18 |
36 |
|
T96 |
66 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1480 |
1 |
|
|
T22 |
51 |
|
T18 |
34 |
|
T96 |
60 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1490 |
1 |
|
|
T22 |
50 |
|
T18 |
35 |
|
T96 |
65 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1459 |
1 |
|
|
T22 |
50 |
|
T18 |
31 |
|
T96 |
59 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1459 |
1 |
|
|
T22 |
49 |
|
T18 |
32 |
|
T96 |
64 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1417 |
1 |
|
|
T22 |
49 |
|
T18 |
30 |
|
T96 |
59 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1429 |
1 |
|
|
T22 |
47 |
|
T18 |
32 |
|
T96 |
64 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1379 |
1 |
|
|
T22 |
49 |
|
T18 |
28 |
|
T96 |
57 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
665 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1391 |
1 |
|
|
T22 |
43 |
|
T18 |
31 |
|
T96 |
63 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1344 |
1 |
|
|
T22 |
48 |
|
T18 |
28 |
|
T96 |
55 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
665 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1366 |
1 |
|
|
T22 |
43 |
|
T18 |
30 |
|
T96 |
58 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
678 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1305 |
1 |
|
|
T22 |
47 |
|
T18 |
28 |
|
T96 |
51 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
664 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1329 |
1 |
|
|
T22 |
41 |
|
T18 |
30 |
|
T96 |
56 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
678 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
23 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1274 |
1 |
|
|
T22 |
46 |
|
T18 |
28 |
|
T96 |
48 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
664 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1293 |
1 |
|
|
T22 |
39 |
|
T18 |
28 |
|
T96 |
56 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
677 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
22 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1241 |
1 |
|
|
T22 |
45 |
|
T18 |
27 |
|
T96 |
47 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
664 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1258 |
1 |
|
|
T22 |
38 |
|
T18 |
26 |
|
T96 |
55 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
677 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
22 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1219 |
1 |
|
|
T22 |
45 |
|
T18 |
27 |
|
T96 |
45 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
664 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1216 |
1 |
|
|
T22 |
36 |
|
T18 |
25 |
|
T96 |
53 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
677 |
1 |
|
|
T22 |
22 |
|
T18 |
17 |
|
T96 |
22 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1189 |
1 |
|
|
T22 |
44 |
|
T18 |
26 |
|
T96 |
43 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
664 |
1 |
|
|
T22 |
19 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[21] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1180 |
1 |
|
|
T22 |
36 |
|
T18 |
23 |
|
T96 |
50 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[0] |
auto[0] |
54805 |
1 |
|
|
T22 |
1397 |
|
T18 |
1194 |
|
T96 |
1555 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[0] |
auto[1] |
45422 |
1 |
|
|
T22 |
1269 |
|
T18 |
1749 |
|
T96 |
1927 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[1] |
auto[0] |
52016 |
1 |
|
|
T22 |
1345 |
|
T18 |
808 |
|
T96 |
1949 |
all_gpio_pins[22] |
filter_cycles_or_more |
auto[1] |
auto[1] |
49467 |
1 |
|
|
T22 |
2017 |
|
T18 |
687 |
|
T96 |
1353 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1617 |
1 |
|
|
T22 |
60 |
|
T18 |
31 |
|
T96 |
52 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1624 |
1 |
|
|
T22 |
63 |
|
T18 |
31 |
|
T96 |
53 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
695 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1586 |
1 |
|
|
T22 |
60 |
|
T18 |
30 |
|
T96 |
51 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1594 |
1 |
|
|
T22 |
63 |
|
T18 |
31 |
|
T96 |
53 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1558 |
1 |
|
|
T22 |
57 |
|
T18 |
29 |
|
T96 |
50 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1564 |
1 |
|
|
T22 |
62 |
|
T18 |
31 |
|
T96 |
51 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
694 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1515 |
1 |
|
|
T22 |
54 |
|
T18 |
29 |
|
T96 |
49 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1537 |
1 |
|
|
T22 |
62 |
|
T18 |
31 |
|
T96 |
51 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
691 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1486 |
1 |
|
|
T22 |
52 |
|
T18 |
29 |
|
T96 |
48 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1501 |
1 |
|
|
T22 |
60 |
|
T18 |
30 |
|
T96 |
51 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
691 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1460 |
1 |
|
|
T22 |
50 |
|
T18 |
29 |
|
T96 |
47 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1460 |
1 |
|
|
T22 |
57 |
|
T18 |
28 |
|
T96 |
50 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1426 |
1 |
|
|
T22 |
48 |
|
T18 |
29 |
|
T96 |
46 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1433 |
1 |
|
|
T22 |
55 |
|
T18 |
28 |
|
T96 |
50 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
27 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1397 |
1 |
|
|
T22 |
48 |
|
T18 |
28 |
|
T96 |
45 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1403 |
1 |
|
|
T22 |
55 |
|
T18 |
27 |
|
T96 |
50 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
677 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
26 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1363 |
1 |
|
|
T22 |
48 |
|
T18 |
28 |
|
T96 |
46 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1366 |
1 |
|
|
T22 |
55 |
|
T18 |
26 |
|
T96 |
48 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
677 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
26 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1340 |
1 |
|
|
T22 |
46 |
|
T18 |
28 |
|
T96 |
46 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1328 |
1 |
|
|
T22 |
53 |
|
T18 |
25 |
|
T96 |
47 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
26 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1298 |
1 |
|
|
T22 |
44 |
|
T18 |
28 |
|
T96 |
44 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1294 |
1 |
|
|
T22 |
51 |
|
T18 |
25 |
|
T96 |
45 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
26 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1271 |
1 |
|
|
T22 |
44 |
|
T18 |
27 |
|
T96 |
43 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1253 |
1 |
|
|
T22 |
50 |
|
T18 |
24 |
|
T96 |
41 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
26 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1239 |
1 |
|
|
T22 |
43 |
|
T18 |
27 |
|
T96 |
42 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1217 |
1 |
|
|
T22 |
49 |
|
T18 |
22 |
|
T96 |
38 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
26 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1206 |
1 |
|
|
T22 |
43 |
|
T18 |
26 |
|
T96 |
41 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1185 |
1 |
|
|
T22 |
47 |
|
T18 |
21 |
|
T96 |
37 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
25 |
|
T18 |
14 |
|
T96 |
26 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1183 |
1 |
|
|
T22 |
43 |
|
T18 |
26 |
|
T96 |
40 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
671 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[22] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1155 |
1 |
|
|
T22 |
46 |
|
T18 |
21 |
|
T96 |
37 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[0] |
auto[0] |
59454 |
1 |
|
|
T22 |
1905 |
|
T18 |
2184 |
|
T96 |
1518 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[0] |
auto[1] |
48915 |
1 |
|
|
T22 |
1765 |
|
T18 |
665 |
|
T96 |
2391 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[1] |
auto[0] |
53438 |
1 |
|
|
T22 |
1590 |
|
T18 |
1069 |
|
T96 |
1246 |
all_gpio_pins[23] |
filter_cycles_or_more |
auto[1] |
auto[1] |
40651 |
1 |
|
|
T22 |
921 |
|
T18 |
485 |
|
T96 |
1477 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
681 |
1 |
|
|
T22 |
25 |
|
T18 |
16 |
|
T96 |
22 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1598 |
1 |
|
|
T22 |
53 |
|
T18 |
30 |
|
T96 |
65 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1597 |
1 |
|
|
T22 |
48 |
|
T18 |
30 |
|
T96 |
72 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
681 |
1 |
|
|
T22 |
25 |
|
T18 |
16 |
|
T96 |
22 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1573 |
1 |
|
|
T22 |
52 |
|
T18 |
30 |
|
T96 |
62 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1570 |
1 |
|
|
T22 |
47 |
|
T18 |
30 |
|
T96 |
71 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T22 |
25 |
|
T18 |
16 |
|
T96 |
22 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1549 |
1 |
|
|
T22 |
52 |
|
T18 |
30 |
|
T96 |
62 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1547 |
1 |
|
|
T22 |
45 |
|
T18 |
30 |
|
T96 |
70 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
680 |
1 |
|
|
T22 |
25 |
|
T18 |
16 |
|
T96 |
22 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1518 |
1 |
|
|
T22 |
52 |
|
T18 |
30 |
|
T96 |
62 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1517 |
1 |
|
|
T22 |
44 |
|
T18 |
30 |
|
T96 |
69 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
25 |
|
T18 |
15 |
|
T96 |
22 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1492 |
1 |
|
|
T22 |
51 |
|
T18 |
29 |
|
T96 |
61 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1472 |
1 |
|
|
T22 |
40 |
|
T18 |
28 |
|
T96 |
68 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
25 |
|
T18 |
15 |
|
T96 |
22 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1455 |
1 |
|
|
T22 |
51 |
|
T18 |
29 |
|
T96 |
60 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1445 |
1 |
|
|
T22 |
39 |
|
T18 |
27 |
|
T96 |
68 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T22 |
25 |
|
T18 |
15 |
|
T96 |
22 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1421 |
1 |
|
|
T22 |
51 |
|
T18 |
29 |
|
T96 |
60 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1416 |
1 |
|
|
T22 |
38 |
|
T18 |
27 |
|
T96 |
65 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
670 |
1 |
|
|
T22 |
25 |
|
T18 |
15 |
|
T96 |
22 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1393 |
1 |
|
|
T22 |
49 |
|
T18 |
29 |
|
T96 |
58 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1372 |
1 |
|
|
T22 |
36 |
|
T18 |
27 |
|
T96 |
62 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
666 |
1 |
|
|
T22 |
25 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1355 |
1 |
|
|
T22 |
47 |
|
T18 |
28 |
|
T96 |
58 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1339 |
1 |
|
|
T22 |
36 |
|
T18 |
27 |
|
T96 |
57 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
666 |
1 |
|
|
T22 |
25 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1324 |
1 |
|
|
T22 |
47 |
|
T18 |
28 |
|
T96 |
56 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
662 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1307 |
1 |
|
|
T22 |
36 |
|
T18 |
27 |
|
T96 |
56 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
663 |
1 |
|
|
T22 |
25 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1303 |
1 |
|
|
T22 |
47 |
|
T18 |
24 |
|
T96 |
56 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
661 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1273 |
1 |
|
|
T22 |
35 |
|
T18 |
26 |
|
T96 |
55 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
663 |
1 |
|
|
T22 |
25 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1275 |
1 |
|
|
T22 |
46 |
|
T18 |
23 |
|
T96 |
55 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
661 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1231 |
1 |
|
|
T22 |
34 |
|
T18 |
25 |
|
T96 |
54 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
663 |
1 |
|
|
T22 |
25 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1248 |
1 |
|
|
T22 |
45 |
|
T18 |
23 |
|
T96 |
54 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1199 |
1 |
|
|
T22 |
34 |
|
T18 |
24 |
|
T96 |
50 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
663 |
1 |
|
|
T22 |
25 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1214 |
1 |
|
|
T22 |
44 |
|
T18 |
23 |
|
T96 |
51 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1167 |
1 |
|
|
T22 |
34 |
|
T18 |
23 |
|
T96 |
50 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
663 |
1 |
|
|
T22 |
25 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1182 |
1 |
|
|
T22 |
44 |
|
T18 |
22 |
|
T96 |
47 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
660 |
1 |
|
|
T22 |
29 |
|
T18 |
15 |
|
T96 |
14 |
all_gpio_pins[23] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1137 |
1 |
|
|
T22 |
33 |
|
T18 |
23 |
|
T96 |
50 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[0] |
auto[0] |
54903 |
1 |
|
|
T22 |
2007 |
|
T18 |
1111 |
|
T96 |
1504 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[0] |
auto[1] |
41203 |
1 |
|
|
T22 |
1081 |
|
T18 |
566 |
|
T96 |
1160 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[1] |
auto[0] |
65942 |
1 |
|
|
T22 |
2192 |
|
T18 |
2097 |
|
T96 |
2793 |
all_gpio_pins[24] |
filter_cycles_or_more |
auto[1] |
auto[1] |
40631 |
1 |
|
|
T22 |
1066 |
|
T18 |
685 |
|
T96 |
1304 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1537 |
1 |
|
|
T22 |
42 |
|
T18 |
32 |
|
T96 |
60 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1575 |
1 |
|
|
T22 |
47 |
|
T18 |
36 |
|
T96 |
60 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1507 |
1 |
|
|
T22 |
41 |
|
T18 |
31 |
|
T96 |
57 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1545 |
1 |
|
|
T22 |
47 |
|
T18 |
36 |
|
T96 |
58 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1482 |
1 |
|
|
T22 |
41 |
|
T18 |
30 |
|
T96 |
56 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1511 |
1 |
|
|
T22 |
47 |
|
T18 |
33 |
|
T96 |
58 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
718 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1464 |
1 |
|
|
T22 |
41 |
|
T18 |
30 |
|
T96 |
56 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1472 |
1 |
|
|
T22 |
46 |
|
T18 |
32 |
|
T96 |
56 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1442 |
1 |
|
|
T22 |
41 |
|
T18 |
29 |
|
T96 |
55 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
679 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1450 |
1 |
|
|
T22 |
46 |
|
T18 |
32 |
|
T96 |
54 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
714 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1424 |
1 |
|
|
T22 |
41 |
|
T18 |
28 |
|
T96 |
55 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
679 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1426 |
1 |
|
|
T22 |
44 |
|
T18 |
32 |
|
T96 |
54 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
708 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1389 |
1 |
|
|
T22 |
41 |
|
T18 |
27 |
|
T96 |
52 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1395 |
1 |
|
|
T22 |
42 |
|
T18 |
32 |
|
T96 |
51 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
708 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1357 |
1 |
|
|
T22 |
39 |
|
T18 |
27 |
|
T96 |
52 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1359 |
1 |
|
|
T22 |
40 |
|
T18 |
32 |
|
T96 |
49 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1331 |
1 |
|
|
T22 |
37 |
|
T18 |
27 |
|
T96 |
50 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1329 |
1 |
|
|
T22 |
40 |
|
T18 |
32 |
|
T96 |
47 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1297 |
1 |
|
|
T22 |
36 |
|
T18 |
27 |
|
T96 |
49 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
673 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1297 |
1 |
|
|
T22 |
39 |
|
T18 |
31 |
|
T96 |
46 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
698 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1264 |
1 |
|
|
T22 |
35 |
|
T18 |
25 |
|
T96 |
49 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
669 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1265 |
1 |
|
|
T22 |
39 |
|
T18 |
29 |
|
T96 |
46 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
698 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1236 |
1 |
|
|
T22 |
35 |
|
T18 |
25 |
|
T96 |
49 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
669 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1236 |
1 |
|
|
T22 |
38 |
|
T18 |
29 |
|
T96 |
45 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1200 |
1 |
|
|
T22 |
33 |
|
T18 |
24 |
|
T96 |
48 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
669 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1202 |
1 |
|
|
T22 |
37 |
|
T18 |
28 |
|
T96 |
43 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1165 |
1 |
|
|
T22 |
33 |
|
T18 |
24 |
|
T96 |
47 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
669 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1162 |
1 |
|
|
T22 |
36 |
|
T18 |
28 |
|
T96 |
41 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1127 |
1 |
|
|
T22 |
32 |
|
T18 |
23 |
|
T96 |
45 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
669 |
1 |
|
|
T22 |
23 |
|
T18 |
9 |
|
T96 |
22 |
all_gpio_pins[24] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1133 |
1 |
|
|
T22 |
34 |
|
T18 |
28 |
|
T96 |
40 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[0] |
auto[0] |
56186 |
1 |
|
|
T22 |
1443 |
|
T18 |
784 |
|
T96 |
1922 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[0] |
auto[1] |
41156 |
1 |
|
|
T22 |
1434 |
|
T18 |
792 |
|
T96 |
2071 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[1] |
auto[0] |
57139 |
1 |
|
|
T22 |
1887 |
|
T18 |
778 |
|
T96 |
1908 |
all_gpio_pins[25] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46376 |
1 |
|
|
T22 |
1145 |
|
T18 |
1783 |
|
T96 |
1081 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
27 |
|
T18 |
14 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1642 |
1 |
|
|
T22 |
62 |
|
T18 |
43 |
|
T96 |
48 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1640 |
1 |
|
|
T22 |
62 |
|
T18 |
41 |
|
T96 |
46 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
27 |
|
T18 |
14 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1615 |
1 |
|
|
T22 |
62 |
|
T18 |
43 |
|
T96 |
47 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1610 |
1 |
|
|
T22 |
60 |
|
T18 |
41 |
|
T96 |
45 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
27 |
|
T18 |
14 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1588 |
1 |
|
|
T22 |
60 |
|
T18 |
43 |
|
T96 |
47 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1578 |
1 |
|
|
T22 |
59 |
|
T18 |
40 |
|
T96 |
45 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
27 |
|
T18 |
14 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1550 |
1 |
|
|
T22 |
57 |
|
T18 |
43 |
|
T96 |
45 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1538 |
1 |
|
|
T22 |
57 |
|
T18 |
38 |
|
T96 |
43 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
27 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1510 |
1 |
|
|
T22 |
57 |
|
T18 |
42 |
|
T96 |
45 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1504 |
1 |
|
|
T22 |
57 |
|
T18 |
37 |
|
T96 |
42 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
27 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1489 |
1 |
|
|
T22 |
56 |
|
T18 |
42 |
|
T96 |
45 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1470 |
1 |
|
|
T22 |
56 |
|
T18 |
36 |
|
T96 |
40 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
27 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1461 |
1 |
|
|
T22 |
56 |
|
T18 |
42 |
|
T96 |
43 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1436 |
1 |
|
|
T22 |
53 |
|
T18 |
34 |
|
T96 |
39 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
683 |
1 |
|
|
T22 |
27 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1432 |
1 |
|
|
T22 |
55 |
|
T18 |
40 |
|
T96 |
42 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1411 |
1 |
|
|
T22 |
53 |
|
T18 |
33 |
|
T96 |
38 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
678 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1398 |
1 |
|
|
T22 |
53 |
|
T18 |
39 |
|
T96 |
42 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1376 |
1 |
|
|
T22 |
50 |
|
T18 |
32 |
|
T96 |
36 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
678 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1367 |
1 |
|
|
T22 |
53 |
|
T18 |
38 |
|
T96 |
41 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1340 |
1 |
|
|
T22 |
48 |
|
T18 |
31 |
|
T96 |
34 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1336 |
1 |
|
|
T22 |
53 |
|
T18 |
36 |
|
T96 |
39 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1315 |
1 |
|
|
T22 |
46 |
|
T18 |
31 |
|
T96 |
34 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
675 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1307 |
1 |
|
|
T22 |
52 |
|
T18 |
34 |
|
T96 |
39 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
684 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1285 |
1 |
|
|
T22 |
41 |
|
T18 |
31 |
|
T96 |
34 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
674 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1271 |
1 |
|
|
T22 |
51 |
|
T18 |
32 |
|
T96 |
38 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1251 |
1 |
|
|
T22 |
41 |
|
T18 |
31 |
|
T96 |
33 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
674 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1229 |
1 |
|
|
T22 |
50 |
|
T18 |
32 |
|
T96 |
36 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1224 |
1 |
|
|
T22 |
41 |
|
T18 |
29 |
|
T96 |
33 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
674 |
1 |
|
|
T22 |
26 |
|
T18 |
13 |
|
T96 |
24 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1205 |
1 |
|
|
T22 |
50 |
|
T18 |
32 |
|
T96 |
35 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
683 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
26 |
all_gpio_pins[25] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1182 |
1 |
|
|
T22 |
38 |
|
T18 |
26 |
|
T96 |
31 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[0] |
auto[0] |
57509 |
1 |
|
|
T22 |
2249 |
|
T18 |
776 |
|
T96 |
1467 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[0] |
auto[1] |
43374 |
1 |
|
|
T22 |
1281 |
|
T18 |
1703 |
|
T96 |
1372 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[1] |
auto[0] |
58875 |
1 |
|
|
T22 |
1807 |
|
T18 |
1247 |
|
T96 |
1803 |
all_gpio_pins[26] |
filter_cycles_or_more |
auto[1] |
auto[1] |
43111 |
1 |
|
|
T22 |
990 |
|
T18 |
696 |
|
T96 |
2183 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
26 |
|
T18 |
16 |
|
T96 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1565 |
1 |
|
|
T22 |
47 |
|
T18 |
31 |
|
T96 |
55 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
704 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1550 |
1 |
|
|
T22 |
45 |
|
T18 |
31 |
|
T96 |
58 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
26 |
|
T18 |
16 |
|
T96 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1542 |
1 |
|
|
T22 |
47 |
|
T18 |
30 |
|
T96 |
55 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
704 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1518 |
1 |
|
|
T22 |
44 |
|
T18 |
30 |
|
T96 |
57 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
26 |
|
T18 |
16 |
|
T96 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1520 |
1 |
|
|
T22 |
47 |
|
T18 |
30 |
|
T96 |
53 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
704 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1484 |
1 |
|
|
T22 |
42 |
|
T18 |
29 |
|
T96 |
56 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
26 |
|
T18 |
16 |
|
T96 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1494 |
1 |
|
|
T22 |
46 |
|
T18 |
30 |
|
T96 |
52 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
704 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1452 |
1 |
|
|
T22 |
38 |
|
T18 |
28 |
|
T96 |
54 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T22 |
26 |
|
T18 |
16 |
|
T96 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1467 |
1 |
|
|
T22 |
45 |
|
T18 |
30 |
|
T96 |
51 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
701 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1412 |
1 |
|
|
T22 |
37 |
|
T18 |
27 |
|
T96 |
52 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
689 |
1 |
|
|
T22 |
26 |
|
T18 |
16 |
|
T96 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1430 |
1 |
|
|
T22 |
45 |
|
T18 |
27 |
|
T96 |
51 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
701 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1380 |
1 |
|
|
T22 |
36 |
|
T18 |
27 |
|
T96 |
51 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
684 |
1 |
|
|
T22 |
26 |
|
T18 |
16 |
|
T96 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1403 |
1 |
|
|
T22 |
45 |
|
T18 |
27 |
|
T96 |
50 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1347 |
1 |
|
|
T22 |
34 |
|
T18 |
27 |
|
T96 |
50 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
684 |
1 |
|
|
T22 |
26 |
|
T18 |
16 |
|
T96 |
24 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1371 |
1 |
|
|
T22 |
45 |
|
T18 |
26 |
|
T96 |
48 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
696 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1315 |
1 |
|
|
T22 |
33 |
|
T18 |
26 |
|
T96 |
49 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
25 |
|
T18 |
16 |
|
T96 |
23 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1343 |
1 |
|
|
T22 |
44 |
|
T18 |
24 |
|
T96 |
47 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1291 |
1 |
|
|
T22 |
33 |
|
T18 |
25 |
|
T96 |
47 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
25 |
|
T18 |
16 |
|
T96 |
23 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1318 |
1 |
|
|
T22 |
44 |
|
T18 |
24 |
|
T96 |
46 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
694 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1262 |
1 |
|
|
T22 |
30 |
|
T18 |
25 |
|
T96 |
43 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
677 |
1 |
|
|
T22 |
25 |
|
T18 |
16 |
|
T96 |
23 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1287 |
1 |
|
|
T22 |
44 |
|
T18 |
23 |
|
T96 |
46 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1224 |
1 |
|
|
T22 |
30 |
|
T18 |
25 |
|
T96 |
43 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
677 |
1 |
|
|
T22 |
25 |
|
T18 |
16 |
|
T96 |
23 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1252 |
1 |
|
|
T22 |
42 |
|
T18 |
23 |
|
T96 |
46 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1197 |
1 |
|
|
T22 |
30 |
|
T18 |
25 |
|
T96 |
42 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
25 |
|
T18 |
16 |
|
T96 |
23 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1221 |
1 |
|
|
T22 |
42 |
|
T18 |
20 |
|
T96 |
44 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1164 |
1 |
|
|
T22 |
30 |
|
T18 |
25 |
|
T96 |
42 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
25 |
|
T18 |
16 |
|
T96 |
23 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T22 |
42 |
|
T18 |
20 |
|
T96 |
43 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1131 |
1 |
|
|
T22 |
29 |
|
T18 |
24 |
|
T96 |
42 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
676 |
1 |
|
|
T22 |
25 |
|
T18 |
16 |
|
T96 |
23 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1171 |
1 |
|
|
T22 |
42 |
|
T18 |
20 |
|
T96 |
41 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
692 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[26] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1096 |
1 |
|
|
T22 |
28 |
|
T18 |
22 |
|
T96 |
42 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[0] |
auto[0] |
55552 |
1 |
|
|
T22 |
1010 |
|
T18 |
1878 |
|
T96 |
2724 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[0] |
auto[1] |
44626 |
1 |
|
|
T22 |
1358 |
|
T18 |
941 |
|
T96 |
1232 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[1] |
auto[0] |
52835 |
1 |
|
|
T22 |
1401 |
|
T18 |
773 |
|
T96 |
1256 |
all_gpio_pins[27] |
filter_cycles_or_more |
auto[1] |
auto[1] |
48477 |
1 |
|
|
T22 |
2058 |
|
T18 |
738 |
|
T96 |
1405 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
654 |
1 |
|
|
T22 |
21 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1666 |
1 |
|
|
T22 |
70 |
|
T18 |
38 |
|
T96 |
61 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1658 |
1 |
|
|
T22 |
68 |
|
T18 |
37 |
|
T96 |
66 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
654 |
1 |
|
|
T22 |
21 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1633 |
1 |
|
|
T22 |
69 |
|
T18 |
38 |
|
T96 |
60 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1625 |
1 |
|
|
T22 |
68 |
|
T18 |
36 |
|
T96 |
66 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
654 |
1 |
|
|
T22 |
21 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1601 |
1 |
|
|
T22 |
67 |
|
T18 |
37 |
|
T96 |
59 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1592 |
1 |
|
|
T22 |
66 |
|
T18 |
36 |
|
T96 |
66 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
654 |
1 |
|
|
T22 |
21 |
|
T18 |
13 |
|
T96 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1561 |
1 |
|
|
T22 |
65 |
|
T18 |
36 |
|
T96 |
56 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
657 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1560 |
1 |
|
|
T22 |
66 |
|
T18 |
35 |
|
T96 |
65 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
650 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1520 |
1 |
|
|
T22 |
65 |
|
T18 |
35 |
|
T96 |
53 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
655 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1533 |
1 |
|
|
T22 |
63 |
|
T18 |
35 |
|
T96 |
65 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
650 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1479 |
1 |
|
|
T22 |
64 |
|
T18 |
33 |
|
T96 |
53 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
655 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1501 |
1 |
|
|
T22 |
63 |
|
T18 |
33 |
|
T96 |
64 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
643 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1448 |
1 |
|
|
T22 |
63 |
|
T18 |
33 |
|
T96 |
52 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
652 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1477 |
1 |
|
|
T22 |
62 |
|
T18 |
32 |
|
T96 |
64 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
643 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
25 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1429 |
1 |
|
|
T22 |
63 |
|
T18 |
33 |
|
T96 |
51 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
652 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1454 |
1 |
|
|
T22 |
62 |
|
T18 |
30 |
|
T96 |
61 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
639 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1385 |
1 |
|
|
T22 |
58 |
|
T18 |
32 |
|
T96 |
51 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
649 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1424 |
1 |
|
|
T22 |
59 |
|
T18 |
30 |
|
T96 |
59 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
639 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1357 |
1 |
|
|
T22 |
57 |
|
T18 |
30 |
|
T96 |
51 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
649 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1387 |
1 |
|
|
T22 |
58 |
|
T18 |
30 |
|
T96 |
58 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
637 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1333 |
1 |
|
|
T22 |
57 |
|
T18 |
30 |
|
T96 |
48 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
647 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1360 |
1 |
|
|
T22 |
58 |
|
T18 |
30 |
|
T96 |
57 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
637 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1293 |
1 |
|
|
T22 |
53 |
|
T18 |
28 |
|
T96 |
46 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
647 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1321 |
1 |
|
|
T22 |
56 |
|
T18 |
29 |
|
T96 |
56 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
637 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1269 |
1 |
|
|
T22 |
51 |
|
T18 |
27 |
|
T96 |
44 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
647 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1288 |
1 |
|
|
T22 |
55 |
|
T18 |
28 |
|
T96 |
56 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
637 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1234 |
1 |
|
|
T22 |
50 |
|
T18 |
27 |
|
T96 |
41 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
647 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1256 |
1 |
|
|
T22 |
55 |
|
T18 |
27 |
|
T96 |
55 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
637 |
1 |
|
|
T22 |
21 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1192 |
1 |
|
|
T22 |
49 |
|
T18 |
27 |
|
T96 |
40 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
647 |
1 |
|
|
T22 |
23 |
|
T18 |
13 |
|
T96 |
19 |
all_gpio_pins[27] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1224 |
1 |
|
|
T22 |
54 |
|
T18 |
27 |
|
T96 |
55 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[0] |
auto[0] |
52337 |
1 |
|
|
T22 |
1448 |
|
T18 |
986 |
|
T96 |
1350 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[0] |
auto[1] |
50631 |
1 |
|
|
T22 |
1405 |
|
T18 |
1798 |
|
T96 |
1746 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[1] |
auto[0] |
55333 |
1 |
|
|
T22 |
1887 |
|
T18 |
821 |
|
T96 |
2471 |
all_gpio_pins[28] |
filter_cycles_or_more |
auto[1] |
auto[1] |
42383 |
1 |
|
|
T22 |
1361 |
|
T18 |
788 |
|
T96 |
1236 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
706 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
18 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1652 |
1 |
|
|
T22 |
62 |
|
T18 |
32 |
|
T96 |
59 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1668 |
1 |
|
|
T22 |
61 |
|
T18 |
32 |
|
T96 |
57 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
706 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
18 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1616 |
1 |
|
|
T22 |
60 |
|
T18 |
30 |
|
T96 |
58 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1633 |
1 |
|
|
T22 |
61 |
|
T18 |
31 |
|
T96 |
56 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
18 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1583 |
1 |
|
|
T22 |
59 |
|
T18 |
28 |
|
T96 |
58 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1593 |
1 |
|
|
T22 |
57 |
|
T18 |
31 |
|
T96 |
56 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T22 |
20 |
|
T18 |
17 |
|
T96 |
18 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1552 |
1 |
|
|
T22 |
56 |
|
T18 |
27 |
|
T96 |
56 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1561 |
1 |
|
|
T22 |
56 |
|
T18 |
29 |
|
T96 |
55 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T22 |
20 |
|
T18 |
16 |
|
T96 |
18 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1521 |
1 |
|
|
T22 |
54 |
|
T18 |
27 |
|
T96 |
56 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
679 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1525 |
1 |
|
|
T22 |
56 |
|
T18 |
28 |
|
T96 |
54 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T22 |
20 |
|
T18 |
16 |
|
T96 |
18 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1481 |
1 |
|
|
T22 |
52 |
|
T18 |
26 |
|
T96 |
54 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
679 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1489 |
1 |
|
|
T22 |
56 |
|
T18 |
27 |
|
T96 |
53 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
20 |
|
T18 |
16 |
|
T96 |
18 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1449 |
1 |
|
|
T22 |
51 |
|
T18 |
26 |
|
T96 |
54 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
674 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1454 |
1 |
|
|
T22 |
56 |
|
T18 |
27 |
|
T96 |
52 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
20 |
|
T18 |
16 |
|
T96 |
18 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1415 |
1 |
|
|
T22 |
50 |
|
T18 |
26 |
|
T96 |
54 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
674 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1428 |
1 |
|
|
T22 |
55 |
|
T18 |
27 |
|
T96 |
50 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T22 |
19 |
|
T18 |
16 |
|
T96 |
17 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1388 |
1 |
|
|
T22 |
49 |
|
T18 |
26 |
|
T96 |
54 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1395 |
1 |
|
|
T22 |
55 |
|
T18 |
27 |
|
T96 |
50 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T22 |
19 |
|
T18 |
16 |
|
T96 |
17 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1354 |
1 |
|
|
T22 |
47 |
|
T18 |
25 |
|
T96 |
53 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
670 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1372 |
1 |
|
|
T22 |
55 |
|
T18 |
25 |
|
T96 |
50 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
684 |
1 |
|
|
T22 |
19 |
|
T18 |
16 |
|
T96 |
17 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1320 |
1 |
|
|
T22 |
47 |
|
T18 |
24 |
|
T96 |
53 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1346 |
1 |
|
|
T22 |
54 |
|
T18 |
25 |
|
T96 |
50 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
684 |
1 |
|
|
T22 |
19 |
|
T18 |
16 |
|
T96 |
17 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1288 |
1 |
|
|
T22 |
46 |
|
T18 |
24 |
|
T96 |
52 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1315 |
1 |
|
|
T22 |
52 |
|
T18 |
24 |
|
T96 |
49 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
684 |
1 |
|
|
T22 |
19 |
|
T18 |
16 |
|
T96 |
17 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1259 |
1 |
|
|
T22 |
46 |
|
T18 |
24 |
|
T96 |
50 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1281 |
1 |
|
|
T22 |
50 |
|
T18 |
24 |
|
T96 |
48 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
684 |
1 |
|
|
T22 |
19 |
|
T18 |
16 |
|
T96 |
17 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1223 |
1 |
|
|
T22 |
45 |
|
T18 |
21 |
|
T96 |
49 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1237 |
1 |
|
|
T22 |
50 |
|
T18 |
24 |
|
T96 |
48 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
684 |
1 |
|
|
T22 |
19 |
|
T18 |
16 |
|
T96 |
17 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1191 |
1 |
|
|
T22 |
45 |
|
T18 |
21 |
|
T96 |
47 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
668 |
1 |
|
|
T22 |
21 |
|
T18 |
16 |
|
T96 |
20 |
all_gpio_pins[28] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1209 |
1 |
|
|
T22 |
49 |
|
T18 |
23 |
|
T96 |
48 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[0] |
auto[0] |
54418 |
1 |
|
|
T22 |
1702 |
|
T18 |
754 |
|
T96 |
2029 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46864 |
1 |
|
|
T22 |
887 |
|
T18 |
772 |
|
T96 |
1101 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[1] |
auto[0] |
53207 |
1 |
|
|
T22 |
1727 |
|
T18 |
887 |
|
T96 |
3067 |
all_gpio_pins[29] |
filter_cycles_or_more |
auto[1] |
auto[1] |
47962 |
1 |
|
|
T22 |
1913 |
|
T18 |
1956 |
|
T96 |
960 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T22 |
29 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1574 |
1 |
|
|
T22 |
45 |
|
T18 |
35 |
|
T96 |
45 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1571 |
1 |
|
|
T22 |
51 |
|
T18 |
34 |
|
T96 |
37 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T22 |
29 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1551 |
1 |
|
|
T22 |
45 |
|
T18 |
35 |
|
T96 |
43 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1549 |
1 |
|
|
T22 |
51 |
|
T18 |
33 |
|
T96 |
35 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T22 |
29 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1532 |
1 |
|
|
T22 |
45 |
|
T18 |
35 |
|
T96 |
42 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1517 |
1 |
|
|
T22 |
51 |
|
T18 |
30 |
|
T96 |
34 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
696 |
1 |
|
|
T22 |
29 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1500 |
1 |
|
|
T22 |
44 |
|
T18 |
35 |
|
T96 |
40 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1497 |
1 |
|
|
T22 |
51 |
|
T18 |
30 |
|
T96 |
33 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
29 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1471 |
1 |
|
|
T22 |
44 |
|
T18 |
33 |
|
T96 |
40 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1464 |
1 |
|
|
T22 |
51 |
|
T18 |
27 |
|
T96 |
32 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
693 |
1 |
|
|
T22 |
29 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1454 |
1 |
|
|
T22 |
42 |
|
T18 |
33 |
|
T96 |
40 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1422 |
1 |
|
|
T22 |
51 |
|
T18 |
27 |
|
T96 |
32 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T22 |
29 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1436 |
1 |
|
|
T22 |
42 |
|
T18 |
33 |
|
T96 |
40 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1388 |
1 |
|
|
T22 |
49 |
|
T18 |
27 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
686 |
1 |
|
|
T22 |
29 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1397 |
1 |
|
|
T22 |
42 |
|
T18 |
32 |
|
T96 |
38 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
689 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1359 |
1 |
|
|
T22 |
48 |
|
T18 |
27 |
|
T96 |
29 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1358 |
1 |
|
|
T22 |
40 |
|
T18 |
31 |
|
T96 |
37 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1307 |
1 |
|
|
T22 |
47 |
|
T18 |
25 |
|
T96 |
29 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
682 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1313 |
1 |
|
|
T22 |
40 |
|
T18 |
31 |
|
T96 |
33 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
687 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1279 |
1 |
|
|
T22 |
45 |
|
T18 |
25 |
|
T96 |
29 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1278 |
1 |
|
|
T22 |
38 |
|
T18 |
31 |
|
T96 |
33 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1247 |
1 |
|
|
T22 |
43 |
|
T18 |
25 |
|
T96 |
28 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1233 |
1 |
|
|
T22 |
33 |
|
T18 |
31 |
|
T96 |
33 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1218 |
1 |
|
|
T22 |
42 |
|
T18 |
25 |
|
T96 |
28 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1202 |
1 |
|
|
T22 |
33 |
|
T18 |
30 |
|
T96 |
33 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1190 |
1 |
|
|
T22 |
42 |
|
T18 |
25 |
|
T96 |
27 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1171 |
1 |
|
|
T22 |
32 |
|
T18 |
30 |
|
T96 |
32 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1156 |
1 |
|
|
T22 |
42 |
|
T18 |
25 |
|
T96 |
25 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
679 |
1 |
|
|
T22 |
28 |
|
T18 |
13 |
|
T96 |
22 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1141 |
1 |
|
|
T22 |
30 |
|
T18 |
29 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
685 |
1 |
|
|
T22 |
23 |
|
T18 |
14 |
|
T96 |
30 |
all_gpio_pins[29] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1132 |
1 |
|
|
T22 |
40 |
|
T18 |
25 |
|
T96 |
25 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[0] |
auto[0] |
53450 |
1 |
|
|
T22 |
1509 |
|
T18 |
1024 |
|
T96 |
1759 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[0] |
auto[1] |
46432 |
1 |
|
|
T22 |
1033 |
|
T18 |
1839 |
|
T96 |
1266 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[1] |
auto[0] |
57800 |
1 |
|
|
T22 |
1618 |
|
T18 |
675 |
|
T96 |
2551 |
all_gpio_pins[30] |
filter_cycles_or_more |
auto[1] |
auto[1] |
42696 |
1 |
|
|
T22 |
1944 |
|
T18 |
683 |
|
T96 |
1237 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
708 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
21 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1649 |
1 |
|
|
T22 |
53 |
|
T18 |
38 |
|
T96 |
59 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1646 |
1 |
|
|
T22 |
58 |
|
T18 |
40 |
|
T96 |
57 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
708 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
21 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1620 |
1 |
|
|
T22 |
53 |
|
T18 |
38 |
|
T96 |
59 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1622 |
1 |
|
|
T22 |
58 |
|
T18 |
39 |
|
T96 |
56 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
707 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
21 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1589 |
1 |
|
|
T22 |
52 |
|
T18 |
37 |
|
T96 |
59 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1598 |
1 |
|
|
T22 |
58 |
|
T18 |
38 |
|
T96 |
53 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
707 |
1 |
|
|
T22 |
27 |
|
T18 |
16 |
|
T96 |
21 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1557 |
1 |
|
|
T22 |
51 |
|
T18 |
37 |
|
T96 |
58 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
706 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1560 |
1 |
|
|
T22 |
58 |
|
T18 |
38 |
|
T96 |
53 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
702 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1526 |
1 |
|
|
T22 |
49 |
|
T18 |
37 |
|
T96 |
57 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1523 |
1 |
|
|
T22 |
56 |
|
T18 |
37 |
|
T96 |
53 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
702 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1484 |
1 |
|
|
T22 |
47 |
|
T18 |
36 |
|
T96 |
55 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
703 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1501 |
1 |
|
|
T22 |
56 |
|
T18 |
37 |
|
T96 |
52 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1459 |
1 |
|
|
T22 |
46 |
|
T18 |
35 |
|
T96 |
54 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
698 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1470 |
1 |
|
|
T22 |
55 |
|
T18 |
37 |
|
T96 |
50 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
697 |
1 |
|
|
T22 |
27 |
|
T18 |
15 |
|
T96 |
21 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1423 |
1 |
|
|
T22 |
45 |
|
T18 |
34 |
|
T96 |
52 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
698 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1433 |
1 |
|
|
T22 |
54 |
|
T18 |
37 |
|
T96 |
48 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
691 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
20 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1382 |
1 |
|
|
T22 |
43 |
|
T18 |
33 |
|
T96 |
48 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1401 |
1 |
|
|
T22 |
52 |
|
T18 |
35 |
|
T96 |
47 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
691 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
20 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1344 |
1 |
|
|
T22 |
42 |
|
T18 |
33 |
|
T96 |
48 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
695 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1366 |
1 |
|
|
T22 |
51 |
|
T18 |
32 |
|
T96 |
44 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
20 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1310 |
1 |
|
|
T22 |
41 |
|
T18 |
33 |
|
T96 |
45 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1331 |
1 |
|
|
T22 |
50 |
|
T18 |
30 |
|
T96 |
42 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
20 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1278 |
1 |
|
|
T22 |
39 |
|
T18 |
32 |
|
T96 |
45 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1304 |
1 |
|
|
T22 |
50 |
|
T18 |
29 |
|
T96 |
41 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
20 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1242 |
1 |
|
|
T22 |
37 |
|
T18 |
32 |
|
T96 |
43 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1276 |
1 |
|
|
T22 |
49 |
|
T18 |
28 |
|
T96 |
41 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
20 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T22 |
36 |
|
T18 |
32 |
|
T96 |
43 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1234 |
1 |
|
|
T22 |
48 |
|
T18 |
26 |
|
T96 |
40 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
26 |
|
T18 |
15 |
|
T96 |
20 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1159 |
1 |
|
|
T22 |
35 |
|
T18 |
30 |
|
T96 |
42 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
693 |
1 |
|
|
T22 |
22 |
|
T18 |
13 |
|
T96 |
23 |
all_gpio_pins[30] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1203 |
1 |
|
|
T22 |
47 |
|
T18 |
23 |
|
T96 |
39 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[0] |
auto[0] |
58186 |
1 |
|
|
T22 |
1307 |
|
T18 |
2035 |
|
T96 |
1205 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[0] |
auto[1] |
42992 |
1 |
|
|
T22 |
1132 |
|
T18 |
604 |
|
T96 |
2385 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[1] |
auto[0] |
54933 |
1 |
|
|
T22 |
1785 |
|
T18 |
833 |
|
T96 |
1607 |
all_gpio_pins[31] |
filter_cycles_or_more |
auto[1] |
auto[1] |
46236 |
1 |
|
|
T22 |
1974 |
|
T18 |
846 |
|
T96 |
1286 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[0] |
706 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[0] |
auto[1] |
1574 |
1 |
|
|
T22 |
51 |
|
T18 |
38 |
|
T96 |
69 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[1] |
auto[1] |
auto[1] |
1580 |
1 |
|
|
T22 |
55 |
|
T18 |
34 |
|
T96 |
67 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[0] |
706 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[0] |
auto[1] |
1548 |
1 |
|
|
T22 |
50 |
|
T18 |
38 |
|
T96 |
67 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[2] |
auto[1] |
auto[1] |
1548 |
1 |
|
|
T22 |
53 |
|
T18 |
34 |
|
T96 |
64 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[0] |
auto[1] |
1514 |
1 |
|
|
T22 |
49 |
|
T18 |
38 |
|
T96 |
66 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[3] |
auto[1] |
auto[1] |
1521 |
1 |
|
|
T22 |
53 |
|
T18 |
34 |
|
T96 |
62 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[0] |
705 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[0] |
auto[1] |
1479 |
1 |
|
|
T22 |
49 |
|
T18 |
38 |
|
T96 |
65 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[0] |
691 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[4] |
auto[1] |
auto[1] |
1481 |
1 |
|
|
T22 |
53 |
|
T18 |
32 |
|
T96 |
59 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[0] |
auto[1] |
1441 |
1 |
|
|
T22 |
48 |
|
T18 |
37 |
|
T96 |
63 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[5] |
auto[1] |
auto[1] |
1459 |
1 |
|
|
T22 |
52 |
|
T18 |
32 |
|
T96 |
58 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[0] |
703 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[0] |
auto[1] |
1414 |
1 |
|
|
T22 |
47 |
|
T18 |
35 |
|
T96 |
63 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[0] |
686 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[6] |
auto[1] |
auto[1] |
1440 |
1 |
|
|
T22 |
49 |
|
T18 |
31 |
|
T96 |
58 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[0] |
auto[1] |
1382 |
1 |
|
|
T22 |
46 |
|
T18 |
34 |
|
T96 |
62 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[7] |
auto[1] |
auto[1] |
1415 |
1 |
|
|
T22 |
48 |
|
T18 |
30 |
|
T96 |
56 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[0] |
699 |
1 |
|
|
T22 |
26 |
|
T18 |
12 |
|
T96 |
24 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[0] |
auto[1] |
1350 |
1 |
|
|
T22 |
46 |
|
T18 |
34 |
|
T96 |
61 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[0] |
681 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[8] |
auto[1] |
auto[1] |
1370 |
1 |
|
|
T22 |
47 |
|
T18 |
28 |
|
T96 |
54 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[0] |
auto[1] |
1319 |
1 |
|
|
T22 |
45 |
|
T18 |
33 |
|
T96 |
61 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[9] |
auto[1] |
auto[1] |
1341 |
1 |
|
|
T22 |
47 |
|
T18 |
27 |
|
T96 |
53 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[0] |
690 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[0] |
auto[1] |
1294 |
1 |
|
|
T22 |
45 |
|
T18 |
33 |
|
T96 |
61 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[0] |
680 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[10] |
auto[1] |
auto[1] |
1319 |
1 |
|
|
T22 |
47 |
|
T18 |
27 |
|
T96 |
52 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[0] |
auto[1] |
1273 |
1 |
|
|
T22 |
43 |
|
T18 |
30 |
|
T96 |
61 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[11] |
auto[1] |
auto[1] |
1295 |
1 |
|
|
T22 |
47 |
|
T18 |
27 |
|
T96 |
51 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[0] |
auto[1] |
1229 |
1 |
|
|
T22 |
40 |
|
T18 |
30 |
|
T96 |
58 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[0] |
678 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[12] |
auto[1] |
auto[1] |
1261 |
1 |
|
|
T22 |
46 |
|
T18 |
27 |
|
T96 |
50 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[0] |
auto[1] |
1197 |
1 |
|
|
T22 |
37 |
|
T18 |
30 |
|
T96 |
56 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[13] |
auto[1] |
auto[1] |
1227 |
1 |
|
|
T22 |
42 |
|
T18 |
27 |
|
T96 |
45 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[0] |
auto[1] |
1169 |
1 |
|
|
T22 |
37 |
|
T18 |
30 |
|
T96 |
56 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[14] |
auto[1] |
auto[1] |
1203 |
1 |
|
|
T22 |
41 |
|
T18 |
26 |
|
T96 |
44 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[0] |
687 |
1 |
|
|
T22 |
25 |
|
T18 |
12 |
|
T96 |
23 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[0] |
auto[1] |
1148 |
1 |
|
|
T22 |
36 |
|
T18 |
27 |
|
T96 |
55 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[0] |
677 |
1 |
|
|
T22 |
22 |
|
T18 |
15 |
|
T96 |
25 |
all_gpio_pins[31] |
one_to_filter_cycles_minus_1[15] |
auto[1] |
auto[1] |
1166 |
1 |
|
|
T22 |
41 |
|
T18 |
24 |
|
T96 |
41 |