Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4415993	1			T22	103		T23	1		T24	56
all_pins[1]	4415993	1			T22	103		T23	1		T24	56
all_pins[2]	4415993	1			T22	103		T23	1		T24	56
all_pins[3]	4415993	1			T22	103		T23	1		T24	56
all_pins[4]	4415993	1			T22	103		T23	1		T24	56
all_pins[5]	4415993	1			T22	103		T23	1		T24	56
all_pins[6]	4415993	1			T22	103		T23	1		T24	56
all_pins[7]	4415993	1			T22	103		T23	1		T24	56
all_pins[8]	4415993	1			T22	103		T23	1		T24	56
all_pins[9]	4415993	1			T22	103		T23	1		T24	56
all_pins[10]	4415993	1			T22	103		T23	1		T24	56
all_pins[11]	4415993	1			T22	103		T23	1		T24	56
all_pins[12]	4415993	1			T22	103		T23	1		T24	56
all_pins[13]	4415993	1			T22	103		T23	1		T24	56
all_pins[14]	4415993	1			T22	103		T23	1		T24	56
all_pins[15]	4415993	1			T22	103		T23	1		T24	56
all_pins[16]	4415993	1			T22	103		T23	1		T24	56
all_pins[17]	4415993	1			T22	103		T23	1		T24	56
all_pins[18]	4415993	1			T22	103		T23	1		T24	56
all_pins[19]	4415993	1			T22	103		T23	1		T24	56
all_pins[20]	4415993	1			T22	103		T23	1		T24	56
all_pins[21]	4415993	1			T22	103		T23	1		T24	56
all_pins[22]	4415993	1			T22	103		T23	1		T24	56
all_pins[23]	4415993	1			T22	103		T23	1		T24	56
all_pins[24]	4415993	1			T22	103		T23	1		T24	56
all_pins[25]	4415993	1			T22	103		T23	1		T24	56
all_pins[26]	4415993	1			T22	103		T23	1		T24	56
all_pins[27]	4415993	1			T22	103		T23	1		T24	56
all_pins[28]	4415993	1			T22	103		T23	1		T24	56
all_pins[29]	4415993	1			T22	103		T23	1		T24	56
all_pins[30]	4415993	1			T22	103		T23	1		T24	56
all_pins[31]	4415993	1			T22	103		T23	1		T24	56

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	87811119	1			T22	1719		T23	32		T24	1478
values[0x1]	53500657	1			T22	1577		T24	314		T25	8703
transitions[0x0=>0x1]	32070038	1			T22	820		T24	213		T25	5377
transitions[0x1=>0x0]	32069892	1			T22	819		T24	213		T25	5376

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2743743	1			T22	60		T23	1		T24	34
all_pins[0]	values[0x1]	1672250	1			T22	43		T24	22		T25	269
all_pins[0]	transitions[0x0=>0x1]	1036348	1			T22	23		T24	17		T25	167
all_pins[0]	transitions[0x1=>0x0]	1031599	1			T22	25		T24	6		T25	190
all_pins[1]	values[0x0]	2742940	1			T22	41		T23	1		T24	47
all_pins[1]	values[0x1]	1673053	1			T22	62		T24	9		T25	274
all_pins[1]	transitions[0x0=>0x1]	1002822	1			T22	43		T24	4		T25	162
all_pins[1]	transitions[0x1=>0x0]	1002019	1			T22	24		T24	17		T25	157
all_pins[2]	values[0x0]	2746421	1			T22	47		T23	1		T24	53
all_pins[2]	values[0x1]	1669572	1			T22	56		T24	3		T25	297
all_pins[2]	transitions[0x0=>0x1]	1001052	1			T22	22		T24	1		T25	202
all_pins[2]	transitions[0x1=>0x0]	1004533	1			T22	28		T24	7		T25	179
all_pins[3]	values[0x0]	2748006	1			T22	50		T23	1		T24	41
all_pins[3]	values[0x1]	1667987	1			T22	53		T24	15		T25	285
all_pins[3]	transitions[0x0=>0x1]	999018	1			T22	22		T24	14		T25	161
all_pins[3]	transitions[0x1=>0x0]	1000603	1			T22	25		T24	2		T25	173
all_pins[4]	values[0x0]	2741119	1			T22	48		T23	1		T24	43
all_pins[4]	values[0x1]	1674874	1			T22	55		T24	13		T25	279
all_pins[4]	transitions[0x0=>0x1]	1004005	1			T22	25		T24	13		T25	176
all_pins[4]	transitions[0x1=>0x0]	997118	1			T22	23		T24	15		T25	182
all_pins[5]	values[0x0]	2742505	1			T22	49		T23	1		T24	36
all_pins[5]	values[0x1]	1673488	1			T22	54		T24	20		T25	222
all_pins[5]	transitions[0x0=>0x1]	998089	1			T22	26		T24	11		T25	134
all_pins[5]	transitions[0x1=>0x0]	999475	1			T22	27		T24	4		T25	191
all_pins[6]	values[0x0]	2737425	1			T22	54		T23	1		T24	38
all_pins[6]	values[0x1]	1678568	1			T22	49		T24	18		T25	222
all_pins[6]	transitions[0x0=>0x1]	1005514	1			T22	29		T24	7		T25	159
all_pins[6]	transitions[0x1=>0x0]	1000434	1			T22	34		T24	9		T25	159
all_pins[7]	values[0x0]	2751763	1			T22	56		T23	1		T24	39
all_pins[7]	values[0x1]	1664230	1			T22	47		T24	17		T25	251
all_pins[7]	transitions[0x0=>0x1]	992214	1			T22	29		T24	12		T25	203
all_pins[7]	transitions[0x1=>0x0]	1006552	1			T22	31		T24	13		T25	174
all_pins[8]	values[0x0]	2738144	1			T22	45		T23	1		T24	52
all_pins[8]	values[0x1]	1677849	1			T22	58		T24	4		T25	315
all_pins[8]	transitions[0x0=>0x1]	1007154	1			T22	36		T25	201		T27	36
all_pins[8]	transitions[0x1=>0x0]	993535	1			T22	25		T24	13		T25	137
all_pins[9]	values[0x0]	2739258	1			T22	60		T23	1		T24	50
all_pins[9]	values[0x1]	1676735	1			T22	43		T24	6		T25	335
all_pins[9]	transitions[0x0=>0x1]	1003512	1			T22	19		T24	6		T25	180
all_pins[9]	transitions[0x1=>0x0]	1004626	1			T22	34		T24	4		T25	160
all_pins[10]	values[0x0]	2744645	1			T22	47		T23	1		T24	45
all_pins[10]	values[0x1]	1671348	1			T22	56		T24	11		T25	306
all_pins[10]	transitions[0x0=>0x1]	1000554	1			T22	33		T24	11		T25	164
all_pins[10]	transitions[0x1=>0x0]	1005941	1			T22	20		T24	6		T25	193
all_pins[11]	values[0x0]	2751396	1			T22	54		T23	1		T24	49
all_pins[11]	values[0x1]	1664597	1			T22	49		T24	7		T25	244
all_pins[11]	transitions[0x0=>0x1]	998353	1			T22	22		T24	3		T25	141
all_pins[11]	transitions[0x1=>0x0]	1005104	1			T22	29		T24	7		T25	203
all_pins[12]	values[0x0]	2741731	1			T22	56		T23	1		T24	45
all_pins[12]	values[0x1]	1674262	1			T22	47		T24	11		T25	265
all_pins[12]	transitions[0x0=>0x1]	1005351	1			T22	28		T24	7		T25	178
all_pins[12]	transitions[0x1=>0x0]	995686	1			T22	30		T24	3		T25	157
all_pins[13]	values[0x0]	2740907	1			T22	59		T23	1		T24	43
all_pins[13]	values[0x1]	1675086	1			T22	44		T24	13		T25	296
all_pins[13]	transitions[0x0=>0x1]	1001393	1			T22	21		T24	7		T25	158
all_pins[13]	transitions[0x1=>0x0]	1000569	1			T22	24		T24	5		T25	127
all_pins[14]	values[0x0]	2746756	1			T22	58		T23	1		T24	47
all_pins[14]	values[0x1]	1669237	1			T22	45		T24	9		T25	323
all_pins[14]	transitions[0x0=>0x1]	999911	1			T22	24		T24	7		T25	203
all_pins[14]	transitions[0x1=>0x0]	1005760	1			T22	23		T24	11		T25	176
all_pins[15]	values[0x0]	2746505	1			T22	54		T23	1		T24	47
all_pins[15]	values[0x1]	1669488	1			T22	49		T24	9		T25	331
all_pins[15]	transitions[0x0=>0x1]	999016	1			T22	28		T24	3		T25	173
all_pins[15]	transitions[0x1=>0x0]	998765	1			T22	24		T24	3		T25	165
all_pins[16]	values[0x0]	2745987	1			T22	63		T23	1		T24	48
all_pins[16]	values[0x1]	1670006	1			T22	40		T24	8		T25	242
all_pins[16]	transitions[0x0=>0x1]	999755	1			T22	20		T24	3		T25	141
all_pins[16]	transitions[0x1=>0x0]	999237	1			T22	29		T24	4		T25	230
all_pins[17]	values[0x0]	2744325	1			T22	62		T23	1		T24	51
all_pins[17]	values[0x1]	1671668	1			T22	41		T24	5		T25	312
all_pins[17]	transitions[0x0=>0x1]	1001333	1			T22	23		T24	1		T25	197
all_pins[17]	transitions[0x1=>0x0]	999671	1			T22	22		T24	4		T25	127
all_pins[18]	values[0x0]	2746135	1			T22	51		T23	1		T24	46
all_pins[18]	values[0x1]	1669858	1			T22	52		T24	10		T25	312
all_pins[18]	transitions[0x0=>0x1]	1000075	1			T22	33		T24	10		T25	180
all_pins[18]	transitions[0x1=>0x0]	1001885	1			T22	22		T24	5		T25	180
all_pins[19]	values[0x0]	2744180	1			T22	56		T23	1		T24	53
all_pins[19]	values[0x1]	1671813	1			T22	47		T24	3		T25	216
all_pins[19]	transitions[0x0=>0x1]	1001987	1			T22	16		T24	2		T25	125
all_pins[19]	transitions[0x1=>0x0]	1000032	1			T22	21		T24	9		T25	221
all_pins[20]	values[0x0]	2742613	1			T22	53		T23	1		T24	44
all_pins[20]	values[0x1]	1673380	1			T22	50		T24	12		T25	250
all_pins[20]	transitions[0x0=>0x1]	1001212	1			T22	27		T24	11		T25	167
all_pins[20]	transitions[0x1=>0x0]	999645	1			T22	24		T24	2		T25	133
all_pins[21]	values[0x0]	2744596	1			T22	47		T23	1		T24	47
all_pins[21]	values[0x1]	1671397	1			T22	56		T24	9		T25	255
all_pins[21]	transitions[0x0=>0x1]	997530	1			T22	31		T24	3		T25	109
all_pins[21]	transitions[0x1=>0x0]	999513	1			T22	25		T24	6		T25	104
all_pins[22]	values[0x0]	2750012	1			T22	51		T23	1		T24	46
all_pins[22]	values[0x1]	1665981	1			T22	52		T24	10		T25	324
all_pins[22]	transitions[0x0=>0x1]	998359	1			T22	23		T24	10		T25	225
all_pins[22]	transitions[0x1=>0x0]	1003775	1			T22	27		T24	9		T25	156
all_pins[23]	values[0x0]	2747276	1			T22	41		T23	1		T24	45
all_pins[23]	values[0x1]	1668717	1			T22	62		T24	11		T25	191
all_pins[23]	transitions[0x0=>0x1]	999195	1			T22	23		T24	9		T25	118
all_pins[23]	transitions[0x1=>0x0]	996459	1			T22	13		T24	8		T25	251
all_pins[24]	values[0x0]	2735175	1			T22	65		T23	1		T24	49
all_pins[24]	values[0x1]	1680818	1			T22	38		T24	7		T25	259
all_pins[24]	transitions[0x0=>0x1]	1008496	1			T22	15		T24	4		T25	206
all_pins[24]	transitions[0x1=>0x0]	996395	1			T22	39		T24	8		T25	138
all_pins[25]	values[0x0]	2744856	1			T22	58		T23	1		T24	48
all_pins[25]	values[0x1]	1671137	1			T22	45		T24	8		T25	330
all_pins[25]	transitions[0x0=>0x1]	995425	1			T22	30		T24	3		T25	172
all_pins[25]	transitions[0x1=>0x0]	1005106	1			T22	23		T24	2		T25	101
all_pins[26]	values[0x0]	2742948	1			T22	52		T23	1		T24	56
all_pins[26]	values[0x1]	1673045	1			T22	51		T25	236		T27	50
all_pins[26]	transitions[0x0=>0x1]	1004860	1			T22	30		T25	117		T27	37
all_pins[26]	transitions[0x1=>0x0]	1002952	1			T22	24		T24	8		T25	211
all_pins[27]	values[0x0]	2744417	1			T22	57		T23	1		T24	53
all_pins[27]	values[0x1]	1671576	1			T22	46		T24	3		T25	227
all_pins[27]	transitions[0x0=>0x1]	1001091	1			T22	22		T24	3		T25	172
all_pins[27]	transitions[0x1=>0x0]	1002560	1			T22	27		T25	181		T27	27
all_pins[28]	values[0x0]	2741175	1			T22	54		T23	1		T24	51
all_pins[28]	values[0x1]	1674818	1			T22	49		T24	5		T25	226
all_pins[28]	transitions[0x0=>0x1]	1001931	1			T22	22		T24	3		T25	153
all_pins[28]	transitions[0x1=>0x0]	998689	1			T22	19		T24	1		T25	154
all_pins[29]	values[0x0]	2741187	1			T22	66		T23	1		T24	42
all_pins[29]	values[0x1]	1674806	1			T22	37		T24	14		T25	298
all_pins[29]	transitions[0x0=>0x1]	1001289	1			T22	21		T24	14		T25	193
all_pins[29]	transitions[0x1=>0x0]	1001301	1			T22	33		T24	5		T25	121
all_pins[30]	values[0x0]	2744627	1			T22	48		T23	1		T24	45
all_pins[30]	values[0x1]	1671366	1			T22	55		T24	11		T25	218
all_pins[30]	transitions[0x0=>0x1]	1001291	1			T22	39		T24	10		T25	121
all_pins[30]	transitions[0x1=>0x0]	1004731	1			T22	21		T24	13		T25	201
all_pins[31]	values[0x0]	2748346	1			T22	57		T23	1		T24	45
all_pins[31]	values[0x1]	1667647	1			T22	46		T24	11		T25	293
all_pins[31]	transitions[0x0=>0x1]	1001903	1			T22	15		T24	4		T25	219
all_pins[31]	transitions[0x1=>0x0]	1005622	1			T22	24		T24	4		T25	144