Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	14588172	1			T22	1689		T23	49		T24	93
all_values[1]	14588172	1			T22	1689		T23	49		T24	93
all_values[2]	14588172	1			T22	1689		T23	49		T24	93
all_values[3]	14588172	1			T22	1689		T23	49		T24	93
all_values[4]	14588172	1			T22	1689		T23	49		T24	93
all_values[5]	14588172	1			T22	1689		T23	49		T24	93
all_values[6]	14588172	1			T22	1689		T23	49		T24	93
all_values[7]	14588172	1			T22	1689		T23	49		T24	93
all_values[8]	14588172	1			T22	1689		T23	49		T24	93
all_values[9]	14588172	1			T22	1689		T23	49		T24	93
all_values[10]	14588172	1			T22	1689		T23	49		T24	93
all_values[11]	14588172	1			T22	1689		T23	49		T24	93
all_values[12]	14588172	1			T22	1689		T23	49		T24	93
all_values[13]	14588172	1			T22	1689		T23	49		T24	93
all_values[14]	14588172	1			T22	1689		T23	49		T24	93
all_values[15]	14588172	1			T22	1689		T23	49		T24	93
all_values[16]	14588172	1			T22	1689		T23	49		T24	93
all_values[17]	14588172	1			T22	1689		T23	49		T24	93
all_values[18]	14588172	1			T22	1689		T23	49		T24	93
all_values[19]	14588172	1			T22	1689		T23	49		T24	93
all_values[20]	14588172	1			T22	1689		T23	49		T24	93
all_values[21]	14588172	1			T22	1689		T23	49		T24	93
all_values[22]	14588172	1			T22	1689		T23	49		T24	93
all_values[23]	14588172	1			T22	1689		T23	49		T24	93
all_values[24]	14588172	1			T22	1689		T23	49		T24	93
all_values[25]	14588172	1			T22	1689		T23	49		T24	93
all_values[26]	14588172	1			T22	1689		T23	49		T24	93
all_values[27]	14588172	1			T22	1689		T23	49		T24	93
all_values[28]	14588172	1			T22	1689		T23	49		T24	93
all_values[29]	14588172	1			T22	1689		T23	49		T24	93
all_values[30]	14588172	1			T22	1689		T23	49		T24	93
all_values[31]	14588172	1			T22	1689		T23	49		T24	93

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

269430220

1

T22

54048

T23

1568

T24

2064

auto[1]

197391284

1

T24

912

T25

40461

T27

3483

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110343421

1

T22

54048

T23

1568

T24

1667

auto[1]

356478083

1

T24

1309

T25

77533

T27

5171

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

461697745

1

T22

54048

T23

1568

T24

2807

auto[1]

5123759

1

T24

169

T28

245157

T1

2018

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2846607	1			T22	1689		T23	49		T24	29
all_values[0]	auto[0]	auto[0]	auto[1]	5515480	1			T24	18		T25	1143		T27	52
all_values[0]	auto[0]	auto[1]	auto[0]	602527	1			T24	7		T25	126		T27	63
all_values[0]	auto[0]	auto[1]	auto[1]	5463317	1			T24	32		T25	1214		T27	79
all_values[0]	auto[1]	auto[0]	auto[1]	80042	1			T24	5		T28	3841		T1	25
all_values[0]	auto[1]	auto[1]	auto[1]	80199	1			T24	2		T28	3887		T1	39
all_values[1]	auto[0]	auto[0]	auto[0]	2840835	1			T22	1689		T23	49		T24	42
all_values[1]	auto[0]	auto[0]	auto[1]	5490209	1			T24	12		T25	1246		T27	55
all_values[1]	auto[0]	auto[1]	auto[0]	602062	1			T24	24		T25	104		T27	44
all_values[1]	auto[0]	auto[1]	auto[1]	5495458	1			T24	8		T25	1184		T27	66
all_values[1]	auto[1]	auto[0]	auto[1]	80246	1			T24	3		T28	3702		T1	24
all_values[1]	auto[1]	auto[1]	auto[1]	79362	1			T24	4		T28	3848		T1	39
all_values[2]	auto[0]	auto[0]	auto[0]	2841290	1			T22	1689		T23	49		T24	29
all_values[2]	auto[0]	auto[0]	auto[1]	5523678	1			T24	45		T25	1148		T27	103
all_values[2]	auto[0]	auto[1]	auto[0]	604400	1			T24	5		T25	108		T27	17
all_values[2]	auto[0]	auto[1]	auto[1]	5458643	1			T24	5		T25	1278		T27	65
all_values[2]	auto[1]	auto[0]	auto[1]	80647	1			T24	8		T28	3748		T1	35
all_values[2]	auto[1]	auto[1]	auto[1]	79514	1			T24	1		T28	3841		T1	30
all_values[3]	auto[0]	auto[0]	auto[0]	2852160	1			T22	1689		T23	49		T24	32
all_values[3]	auto[0]	auto[0]	auto[1]	5510288	1			T24	19		T25	1199		T27	57
all_values[3]	auto[0]	auto[1]	auto[0]	588087	1			T24	17		T25	68		T27	4
all_values[3]	auto[0]	auto[1]	auto[1]	5477354	1			T24	19		T25	1181		T27	126
all_values[3]	auto[1]	auto[0]	auto[1]	80512	1			T24	2		T28	3754		T1	38
all_values[3]	auto[1]	auto[1]	auto[1]	79771	1			T24	4		T28	3970		T1	29
all_values[4]	auto[0]	auto[0]	auto[0]	2837805	1			T22	1689		T23	49		T24	33
all_values[4]	auto[0]	auto[0]	auto[1]	5485559	1			T24	20		T25	1300		T27	45
all_values[4]	auto[0]	auto[1]	auto[0]	596352	1			T24	19		T25	63		T27	33
all_values[4]	auto[0]	auto[1]	auto[1]	5508785	1			T24	16		T25	1193		T27	125
all_values[4]	auto[1]	auto[0]	auto[1]	80056	1			T24	4		T28	3826		T1	31
all_values[4]	auto[1]	auto[1]	auto[1]	79615	1			T24	1		T28	3940		T1	32
all_values[5]	auto[0]	auto[0]	auto[0]	2838920	1			T22	1689		T23	49		T24	31
all_values[5]	auto[0]	auto[0]	auto[1]	5476396	1			T24	12		T25	1412		T27	74
all_values[5]	auto[0]	auto[1]	auto[0]	601850	1			T24	18		T25	109		T27	30
all_values[5]	auto[0]	auto[1]	auto[1]	5510596	1			T24	27		T25	916		T27	75
all_values[5]	auto[1]	auto[0]	auto[1]	80097	1			T24	2		T28	3787		T1	28
all_values[5]	auto[1]	auto[1]	auto[1]	80313	1			T24	3		T28	3952		T1	40
all_values[6]	auto[0]	auto[0]	auto[0]	2843840	1			T22	1689		T23	49		T24	39
all_values[6]	auto[0]	auto[0]	auto[1]	5490134	1			T24	4		T25	1419		T27	115
all_values[6]	auto[0]	auto[1]	auto[0]	603885	1			T24	21		T25	121		T27	16
all_values[6]	auto[0]	auto[1]	auto[1]	5490456	1			T24	25		T25	929		T27	54
all_values[6]	auto[1]	auto[0]	auto[1]	80028	1			T24	2		T28	3810		T1	23
all_values[6]	auto[1]	auto[1]	auto[1]	79829	1			T24	2		T28	3731		T1	39
all_values[7]	auto[0]	auto[0]	auto[0]	2848557	1			T22	1689		T23	49		T24	32
all_values[7]	auto[0]	auto[0]	auto[1]	5496006	1			T24	30		T25	1366		T27	79
all_values[7]	auto[0]	auto[1]	auto[0]	607118	1			T24	5		T25	97		T27	26
all_values[7]	auto[0]	auto[1]	auto[1]	5476242	1			T24	20		T25	1068		T27	85
all_values[7]	auto[1]	auto[0]	auto[1]	81111	1			T24	4		T28	3895		T1	28
all_values[7]	auto[1]	auto[1]	auto[1]	79138	1			T24	2		T28	3781		T1	42
all_values[8]	auto[0]	auto[0]	auto[0]	2837316	1			T22	1689		T23	49		T24	46
all_values[8]	auto[0]	auto[0]	auto[1]	5474986	1			T24	31		T25	1166		T27	75
all_values[8]	auto[0]	auto[1]	auto[0]	610480	1			T24	3		T25	49		T27	16
all_values[8]	auto[0]	auto[1]	auto[1]	5505123	1			T24	6		T25	1297		T27	106
all_values[8]	auto[1]	auto[0]	auto[1]	80354	1			T24	7		T28	3826		T1	34
all_values[8]	auto[1]	auto[1]	auto[1]	79913	1			T28	3915		T1	43		T2	28
all_values[9]	auto[0]	auto[0]	auto[0]	2836575	1			T22	1689		T23	49		T24	46
all_values[9]	auto[0]	auto[0]	auto[1]	5471225	1			T24	37		T25	984		T27	58
all_values[9]	auto[0]	auto[1]	auto[0]	594317	1			T24	2		T25	107		T27	24
all_values[9]	auto[0]	auto[1]	auto[1]	5525997	1			T24	3		T25	1464		T27	95
all_values[9]	auto[1]	auto[0]	auto[1]	79884	1			T24	3		T28	3867		T1	34
all_values[9]	auto[1]	auto[1]	auto[1]	80174	1			T24	2		T28	3758		T1	27
all_values[10]	auto[0]	auto[0]	auto[0]	2846829	1			T22	1689		T23	49		T24	29
all_values[10]	auto[0]	auto[0]	auto[1]	5499602	1			T24	18		T25	1215		T27	108
all_values[10]	auto[0]	auto[1]	auto[0]	607060	1			T24	24		T25	50		T27	8
all_values[10]	auto[0]	auto[1]	auto[1]	5474946	1			T24	16		T25	1258		T27	68
all_values[10]	auto[1]	auto[0]	auto[1]	80078	1			T24	3		T28	3757		T1	34
all_values[10]	auto[1]	auto[1]	auto[1]	79657	1			T24	3		T28	3812		T1	34
all_values[11]	auto[0]	auto[0]	auto[0]	2847998	1			T22	1689		T23	49		T24	37
all_values[11]	auto[0]	auto[0]	auto[1]	5503003	1			T24	37		T25	1180		T27	89
all_values[11]	auto[0]	auto[1]	auto[0]	601647	1			T24	7		T25	164		T27	21
all_values[11]	auto[0]	auto[1]	auto[1]	5475027	1			T24	7		T25	1196		T27	86
all_values[11]	auto[1]	auto[0]	auto[1]	80621	1			T24	3		T28	3772		T1	31
all_values[11]	auto[1]	auto[1]	auto[1]	79876	1			T24	2		T28	3868		T1	34
all_values[12]	auto[0]	auto[0]	auto[0]	2846007	1			T22	1689		T23	49		T24	43
all_values[12]	auto[0]	auto[0]	auto[1]	5478317	1			T24	24		T25	1244		T27	102
all_values[12]	auto[0]	auto[1]	auto[0]	609122	1			T24	9		T25	102		T27	17
all_values[12]	auto[0]	auto[1]	auto[1]	5494659	1			T24	14		T25	1164		T27	59
all_values[12]	auto[1]	auto[0]	auto[1]	80287	1			T24	2		T28	3909		T1	27
all_values[12]	auto[1]	auto[1]	auto[1]	79780	1			T24	1		T28	3780		T1	35
all_values[13]	auto[0]	auto[0]	auto[0]	2843255	1			T22	1689		T23	49		T24	32
all_values[13]	auto[0]	auto[0]	auto[1]	5484078	1			T24	11		T25	1188		T27	65
all_values[13]	auto[0]	auto[1]	auto[0]	606813	1			T24	31		T25	93		T27	19
all_values[13]	auto[0]	auto[1]	auto[1]	5493570	1			T24	13		T25	1255		T27	87
all_values[13]	auto[1]	auto[0]	auto[1]	80506	1			T24	2		T28	3950		T1	31
all_values[13]	auto[1]	auto[1]	auto[1]	79950	1			T24	4		T28	3796		T1	29
all_values[14]	auto[0]	auto[0]	auto[0]	2852743	1			T22	1689		T23	49		T24	26
all_values[14]	auto[0]	auto[0]	auto[1]	5502289	1			T24	24		T25	927		T27	61
all_values[14]	auto[0]	auto[1]	auto[0]	612785	1			T24	22		T25	136		T27	32
all_values[14]	auto[0]	auto[1]	auto[1]	5460634	1			T24	16		T25	1427		T27	105
all_values[14]	auto[1]	auto[0]	auto[1]	79928	1			T24	3		T28	3850		T1	29
all_values[14]	auto[1]	auto[1]	auto[1]	79793	1			T24	2		T28	3787		T1	23
all_values[15]	auto[0]	auto[0]	auto[0]	2842875	1			T22	1689		T23	49		T24	41
all_values[15]	auto[0]	auto[0]	auto[1]	5511935	1			T24	18		T25	1069		T27	50
all_values[15]	auto[0]	auto[1]	auto[0]	602535	1			T24	13		T25	87		T27	24
all_values[15]	auto[0]	auto[1]	auto[1]	5470980	1			T24	16		T25	1365		T27	127
all_values[15]	auto[1]	auto[0]	auto[1]	80471	1			T24	3		T28	3744		T1	35
all_values[15]	auto[1]	auto[1]	auto[1]	79376	1			T24	2		T28	3786		T1	27
all_values[16]	auto[0]	auto[0]	auto[0]	2844954	1			T22	1689		T23	49		T24	50
all_values[16]	auto[0]	auto[0]	auto[1]	5527672	1			T24	19		T25	1463		T27	81
all_values[16]	auto[0]	auto[1]	auto[0]	596900	1			T24	2		T25	32		T27	9
all_values[16]	auto[0]	auto[1]	auto[1]	5458667	1			T24	16		T25	1043		T27	87
all_values[16]	auto[1]	auto[0]	auto[1]	80382	1			T24	3		T28	3786		T1	25
all_values[16]	auto[1]	auto[1]	auto[1]	79597	1			T24	3		T28	3873		T1	31
all_values[17]	auto[0]	auto[0]	auto[0]	2837904	1			T22	1689		T23	49		T24	41
all_values[17]	auto[0]	auto[0]	auto[1]	5480614	1			T24	26		T25	1185		T27	74
all_values[17]	auto[0]	auto[1]	auto[0]	602386	1			T24	13		T25	58		T27	23
all_values[17]	auto[0]	auto[1]	auto[1]	5506577	1			T24	9		T25	1271		T27	72
all_values[17]	auto[1]	auto[0]	auto[1]	80456	1			T24	2		T28	3782		T1	30
all_values[17]	auto[1]	auto[1]	auto[1]	80235	1			T24	2		T28	3927		T1	30
all_values[18]	auto[0]	auto[0]	auto[0]	2851633	1			T22	1689		T23	49		T24	48
all_values[18]	auto[0]	auto[0]	auto[1]	5444920	1			T24	10		T25	1060		T27	91
all_values[18]	auto[0]	auto[1]	auto[0]	598709	1			T24	19		T25	84		T27	18
all_values[18]	auto[0]	auto[1]	auto[1]	5532357	1			T24	11		T25	1379		T27	78
all_values[18]	auto[1]	auto[0]	auto[1]	80516	1			T24	2		T28	3812		T1	29
all_values[18]	auto[1]	auto[1]	auto[1]	80037	1			T24	3		T28	3928		T1	29
all_values[19]	auto[0]	auto[0]	auto[0]	2846611	1			T22	1689		T23	49		T24	63
all_values[19]	auto[0]	auto[0]	auto[1]	5511470	1			T24	18		T25	1245		T27	75
all_values[19]	auto[0]	auto[1]	auto[0]	602165	1			T24	5		T25	76		T27	41
all_values[19]	auto[0]	auto[1]	auto[1]	5468006	1			T24	2		T25	1025		T27	61
all_values[19]	auto[1]	auto[0]	auto[1]	79720	1			T24	4		T28	3822		T1	25
all_values[19]	auto[1]	auto[1]	auto[1]	80200	1			T24	1		T28	3828		T1	24
all_values[20]	auto[0]	auto[0]	auto[0]	2840949	1			T22	1689		T23	49		T24	41
all_values[20]	auto[0]	auto[0]	auto[1]	5506451	1			T24	14		T25	1258		T27	55
all_values[20]	auto[0]	auto[1]	auto[0]	605346	1			T24	13		T25	105		T27	35
all_values[20]	auto[0]	auto[1]	auto[1]	5475576	1			T24	18		T25	1157		T27	92
all_values[20]	auto[1]	auto[0]	auto[1]	80321	1			T24	4		T28	3863		T1	37
all_values[20]	auto[1]	auto[1]	auto[1]	79529	1			T24	3		T28	3792		T1	24
all_values[21]	auto[0]	auto[0]	auto[0]	2846702	1			T22	1689		T23	49		T24	43
all_values[21]	auto[0]	auto[0]	auto[1]	5513761	1			T24	30		T25	1324		T27	65
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all_values[21]	auto[0]	auto[1]	auto[1]	5467150	1			T24	10		T25	1142		T27	116
all_values[21]	auto[1]	auto[0]	auto[1]	80357	1			T24	5		T28	3773		T1	27
all_values[21]	auto[1]	auto[1]	auto[1]	80311	1			T24	2		T28	3835		T1	47
all_values[22]	auto[0]	auto[0]	auto[0]	2857227	1			T22	1689		T23	49		T24	43
all_values[22]	auto[0]	auto[0]	auto[1]	5524968	1			T24	23		T25	1161		T27	36
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all_values[22]	auto[0]	auto[1]	auto[1]	5445223	1			T24	18		T25	1288		T27	114
all_values[22]	auto[1]	auto[0]	auto[1]	80782	1			T24	2		T28	3772		T1	40
all_values[22]	auto[1]	auto[1]	auto[1]	79213	1			T24	1		T28	3836		T1	27
all_values[23]	auto[0]	auto[0]	auto[0]	2847310	1			T22	1689		T23	49		T24	45
all_values[23]	auto[0]	auto[0]	auto[1]	5509643	1			T24	7		T25	1524		T27	109
all_values[23]	auto[0]	auto[1]	auto[0]	600817	1			T24	21		T25	132		T27	12
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all_values[23]	auto[1]	auto[1]	auto[1]	79140	1			T24	3		T28	3838		T1	18
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all_values[24]	auto[1]	auto[0]	auto[1]	79643	1			T24	5		T28	3789		T1	24
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all_values[25]	auto[0]	auto[0]	auto[0]	2847721	1			T22	1689		T23	49		T24	47
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all_values[25]	auto[0]	auto[1]	auto[1]	5470174	1			T24	14		T25	1437		T27	86
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all_values[25]	auto[1]	auto[1]	auto[1]	79394	1			T24	2		T28	3803		T1	31
all_values[26]	auto[0]	auto[0]	auto[0]	2846520	1			T22	1689		T23	49		T24	45
all_values[26]	auto[0]	auto[0]	auto[1]	5453442	1			T24	28		T25	1349		T27	83
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all_values[26]	auto[1]	auto[1]	auto[1]	79753	1			T28	3855		T1	37		T2	27
all_values[27]	auto[0]	auto[0]	auto[0]	2844231	1			T22	1689		T23	49		T24	39
all_values[27]	auto[0]	auto[0]	auto[1]	5502109	1			T24	23		T25	1457		T27	68
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all_values[27]	auto[0]	auto[1]	auto[1]	5465268	1			T24	6		T25	968		T27	85
all_values[27]	auto[1]	auto[0]	auto[1]	79939	1			T24	2		T28	3781		T1	27
all_values[27]	auto[1]	auto[1]	auto[1]	80024	1			T28	3847		T1	36		T2	24
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all_values[28]	auto[0]	auto[0]	auto[1]	5475585	1			T24	25		T25	1496		T27	87
all_values[28]	auto[0]	auto[1]	auto[0]	604406	1			T24	5		T25	85		T27	23
all_values[28]	auto[0]	auto[1]	auto[1]	5500531	1			T24	7		T25	917		T27	75
all_values[28]	auto[1]	auto[0]	auto[1]	80266	1			T24	4		T28	3975		T1	34
all_values[28]	auto[1]	auto[1]	auto[1]	80127	1			T28	3749		T1	31		T2	21
all_values[29]	auto[0]	auto[0]	auto[0]	2843032	1			T22	1689		T23	49		T24	37
all_values[29]	auto[0]	auto[0]	auto[1]	5481068	1			T24	15		T25	1181		T27	61
all_values[29]	auto[0]	auto[1]	auto[0]	612154	1			T24	20		T25	62		T27	27
all_values[29]	auto[0]	auto[1]	auto[1]	5491662	1			T24	15		T25	1311		T27	81
all_values[29]	auto[1]	auto[0]	auto[1]	79832	1			T24	1		T28	3880		T1	24
all_values[29]	auto[1]	auto[1]	auto[1]	80424	1			T24	5		T28	3813		T1	40
all_values[30]	auto[0]	auto[0]	auto[0]	2847520	1			T22	1689		T23	49		T24	30
all_values[30]	auto[0]	auto[0]	auto[1]	5493024	1			T24	20		T25	1438		T27	99
all_values[30]	auto[0]	auto[1]	auto[0]	608298	1			T24	21		T25	76		T27	24
all_values[30]	auto[0]	auto[1]	auto[1]	5479562	1			T24	18		T25	981		T27	74
all_values[30]	auto[1]	auto[0]	auto[1]	79894	1			T24	4		T28	3858		T1	29
all_values[30]	auto[1]	auto[1]	auto[1]	79874	1			T28	3803		T1	41		T2	39
all_values[31]	auto[0]	auto[0]	auto[0]	2841715	1			T22	1689		T23	49		T24	26
all_values[31]	auto[0]	auto[0]	auto[1]	5512411	1			T24	32		T25	1259		T27	80
all_values[31]	auto[0]	auto[1]	auto[0]	610249	1			T24	17		T25	66		T27	8
all_values[31]	auto[0]	auto[1]	auto[1]	5463153	1			T24	13		T25	1195		T27	108
all_values[31]	auto[1]	auto[0]	auto[1]	80185	1			T24	2		T28	3910		T1	34
all_values[31]	auto[1]	auto[1]	auto[1]	80459	1			T24	3		T28	3817		T1	27

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal