Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[1]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[2]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[3]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[4]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[5]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[6]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[7]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[8]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[9]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[10]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[11]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[12]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[13]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[14]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[15]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[16]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[17]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[18]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[19]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[20]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[21]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[22]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[23]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[24]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[25]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[26]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[27]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[28]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[29]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[30]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[31]	14327873	1			T22	1689		T23	86		T24	115

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

266950797

1

T22

27132

T23

717

T24

2000

auto[1]

191541139

1

T22

26916

T23

2035

T24

1680

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

368260711

1

T22

54048

T23

2571

T24

3472

auto[1]

90231225

1

T23

181

T24

208

T28

424303

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

341583667

1

T22

54048

T23

2108

T24

2839

auto[1]

116908269

1

T23

644

T24

841

T28

553345

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5224650	1			T22	914		T23	9		T24	36
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	4035883	1			T22	775		T23	41		T24	49
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1417968	1			T23	4		T28	66361		T29	136
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1697983	1			T23	9		T24	9		T28	100011
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	544079	1			T23	19		T24	18		T28	7493
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1407310	1			T23	4		T24	3		T28	66559
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5213770	1			T22	945		T23	14		T24	25
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	4041755	1			T22	744		T23	28		T24	43
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1424055	1			T23	4		T28	67322		T29	151
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1698836	1			T23	9		T24	12		T28	98810
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	546293	1			T23	25		T24	24		T28	7239
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1403164	1			T23	6		T24	11		T28	65757
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5222253	1			T22	804		T23	14		T24	44
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	4039638	1			T22	885		T23	66		T24	35
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1419433	1			T23	6		T24	3		T28	66461
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1699131	1			T24	19		T28	99154		T29	128
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	546978	1			T24	11		T28	6995		T30	27
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1400440	1			T24	3		T28	65531		T29	136
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5219371	1			T22	777		T23	14		T24	46
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	4033585	1			T22	912		T23	30		T24	43
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1417637	1			T23	2		T24	6		T28	66290
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1702838	1			T23	13		T24	13		T28	99448
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	546594	1			T23	27		T24	2		T28	7176
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1407848	1			T24	5		T28	65243		T29	112
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5211914	1			T22	764		T23	18		T24	71
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	4041206	1			T22	925		T23	59		T24	16
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1419465	1			T23	2		T24	5		T28	65526
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1699245	1			T24	19		T28	101682		T29	120
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	546105	1			T23	5		T24	4		T28	7500
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1409938	1			T23	2		T28	66173		T29	120
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5218508	1			T22	746		T23	21		T24	64
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	4037533	1			T22	943		T23	59		T24	21
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1412493	1			T23	6		T24	3		T28	66694
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1705821	1			T24	15		T28	100653		T29	187
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	548388	1			T24	4		T28	7429		T30	42
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1405130	1			T24	8		T28	66087		T29	116
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5209465	1			T22	899		T23	25		T24	48
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	4044197	1			T22	790		T23	59		T24	51
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1419069	1			T23	2		T24	3		T28	67681
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1703889	1			T24	12		T28	99026		T29	100
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	548034	1			T24	1		T28	7074		T30	45
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1403219	1			T28	66245		T29	135		T30	16
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5214517	1			T22	902		T23	15		T24	34
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	4040447	1			T22	787		T23	46		T24	42
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1419379	1			T23	6		T28	66454		T29	143
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1704558	1			T23	2		T24	23		T28	100286
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	547123	1			T23	15		T24	10		T28	7499
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1401849	1			T23	2		T24	6		T28	66328
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5220067	1			T22	724		T23	10		T24	49
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	4039432	1			T22	965		T23	48		T24	31
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1419435	1			T23	6		T28	67516		T29	126
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1697293	1			T23	9		T24	23		T28	98928
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	548087	1			T23	11		T24	7		T28	7605
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1403559	1			T23	2		T24	5		T28	65885
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5217170	1			T22	739		T23	14		T24	27
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	4041203	1			T22	950		T23	34		T24	64
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1421054	1			T23	6		T28	67601		T29	120
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1698089	1			T23	8		T24	7		T28	99117
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	547411	1			T23	24		T24	7		T28	7552
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1402946	1			T24	10		T28	66275		T29	136
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5214568	1			T22	891		T23	20		T24	47
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	4033329	1			T22	798		T23	60		T24	27
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1421931	1			T23	6		T24	6		T28	67247
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1702867	1			T24	30		T28	100563		T29	117
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	546397	1			T24	5		T28	7512		T30	48
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1408781	1			T28	65264		T29	146		T30	10
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5220299	1			T22	888		T23	10		T24	79
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	4036600	1			T22	801		T23	37		T24	23
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1421051	1			T24	3		T28	66903		T29	142
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1697067	1			T23	2		T24	10		T28	99197
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	548617	1			T23	31		T28	7395		T30	59
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1404239	1			T23	6		T28	66401		T29	135
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5226070	1			T22	872		T23	8		T24	41
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	4034477	1			T22	817		T23	35		T24	34
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1419676	1			T23	4		T28	66838		T29	128
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1699173	1			T23	7		T24	8		T28	99916
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	546193	1			T23	28		T24	22		T28	7178
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1402284	1			T23	4		T24	10		T28	64815
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5223396	1			T22	911		T23	12		T24	31
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	4031412	1			T22	778		T23	53		T24	47
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1421403	1			T23	2		T28	66441		T29	128
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1697634	1			T23	1		T24	19		T28	98810
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	546269	1			T23	18		T24	8		T28	7203
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1407759	1			T24	10		T28	66775		T29	153
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5220948	1			T22	842		T23	11		T24	53
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	4030955	1			T22	847		T23	50		T24	47
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1416208	1			T23	4		T24	3		T28	66959
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1705861	1			T23	6		T24	7		T28	99164
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	547812	1			T23	13		T24	5		T28	7420
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1406089	1			T23	2		T28	66917		T29	136
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5228966	1			T22	832		T23	8		T24	58
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	4023014	1			T22	857		T23	46		T24	32
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1417474	1			T23	4		T28	67187		T29	126
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1704241	1			T23	12		T24	15		T28	99177
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	550066	1			T23	14		T24	2		T28	7234
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1404112	1			T23	2		T24	8		T28	65682
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5210120	1			T22	768		T23	20		T24	54
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	4044652	1			T22	921		T23	31		T24	45
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1412656	1			T23	4		T24	2		T28	66477
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1706470	1			T23	7		T24	2		T28	99546
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	551491	1			T23	20		T24	6		T28	7572
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1402484	1			T23	4		T24	6		T28	66967
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5221423	1			T22	863		T23	15		T24	34
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	4037097	1			T22	826		T23	52		T24	59
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1414800	1			T23	6		T24	3		T28	67420
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1710057	1			T24	17		T28	99127		T29	94
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	549063	1			T23	11		T24	1		T28	7116
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1395433	1			T23	2		T24	1		T28	64406
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5235594	1			T22	853		T23	4		T24	48
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	4025773	1			T22	836		T23	55		T24	66
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1417745	1			T23	6		T28	66463		T29	135
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1700798	1			T23	8		T28	98717		T29	134
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	549625	1			T23	13		T24	1		T28	7247
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1398338	1			T28	66314		T29	110		T30	19
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5213497	1			T22	943		T23	7		T24	64
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	4038416	1			T22	746		T23	36		T24	44
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1410009	1			T23	4		T28	65701		T29	114
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1709498	1			T23	10		T24	5		T28	98966
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	549308	1			T23	29		T24	2		T28	7145
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1407145	1			T28	64812		T29	138		T30	31
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5230152	1			T22	876		T23	12		T24	23
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	4027952	1			T22	813		T23	31		T24	75
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1416126	1			T23	4		T24	2		T28	66460
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1707226	1			T23	9		T24	9		T28	99989
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	547408	1			T23	25		T24	4		T28	7427
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1399009	1			T23	5		T24	2		T28	66254
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5217682	1			T22	890		T23	18		T24	32
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	4037508	1			T22	799		T23	56		T24	46
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1420525	1			T23	4		T24	3		T28	67230
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1706438	1			T23	2		T24	22		T28	99931
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	545252	1			T23	6		T24	7		T28	7661
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1400468	1			T24	5		T28	65700		T29	124
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5226312	1			T22	850		T23	21		T24	94
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	4032016	1			T22	839		T23	43		T24	15
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1413655	1			T23	4		T24	2		T28	66189
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1703915	1			T23	2		T24	4		T28	99963
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	549406	1			T23	14		T28	7399		T30	59
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1402569	1			T23	2		T28	66447		T29	86
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5216948	1			T22	893		T23	7		T24	28
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	4035143	1			T22	796		T23	53		T24	44
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1415189	1			T24	4		T28	66505		T29	124
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1709002	1			T23	4		T24	24		T28	99614
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	549458	1			T23	20		T24	9		T28	7518
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1402133	1			T23	2		T24	6		T28	66120
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5240558	1			T22	912		T23	20		T24	47
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	4025459	1			T22	777		T23	56		T24	30
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1412650	1			T23	10		T24	3		T28	66868
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1703098	1			T24	8		T28	100051		T29	124
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	547099	1			T24	16		T28	7024		T30	42
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1399009	1			T24	11		T28	64913		T29	159
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5215926	1			T22	832		T23	12		T24	75
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	4041095	1			T22	857		T23	46		T24	12
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1414906	1			T23	2		T28	66761		T29	128
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1702437	1			T23	3		T24	27		T28	100697
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	547440	1			T23	23		T24	1		T28	7556
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1406069	1			T28	65560		T29	124		T30	10
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5236352	1			T22	836		T23	15		T24	33
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	4029093	1			T22	853		T23	49		T24	63
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1417065	1			T23	4		T28	65937		T29	124
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1704598	1			T23	4		T24	10		T28	100047
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	547413	1			T23	14		T24	7		T28	7377
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1393352	1			T24	2		T28	66766		T29	148
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5221849	1			T22	842		T23	13		T24	26
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	4039925	1			T22	847		T23	53		T24	45
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1414755	1			T23	2		T24	6		T28	66680
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1709645	1			T23	2		T24	13		T28	100397
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	547310	1			T23	16		T24	15		T28	7159
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1394389	1			T24	10		T28	65000		T29	96
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5222171	1			T22	876		T23	21		T24	43
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	4038090	1			T22	813		T23	45		T24	44
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1410421	1			T23	2		T24	4		T28	66181
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1705547	1			T23	1		T24	11		T28	99588
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	547318	1			T23	14		T24	7		T28	7385
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1404326	1			T23	3		T24	6		T28	66102
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5225550	1			T22	845		T23	6		T24	35
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	4038199	1			T22	844		T23	47		T24	31
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1416123	1			T23	2		T28	66914		T29	135
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1701621	1			T23	9		T24	21		T28	100163
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	547605	1			T23	21		T24	23		T28	7312
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1398775	1			T23	1		T24	5		T28	65378
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5232889	1			T22	821		T23	15		T24	40
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	4030317	1			T22	868		T23	63		T24	28
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1417414	1			T23	8		T24	6		T28	67189
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1701421	1			T24	20		T28	99591		T29	166
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	549931	1			T24	15		T28	7078		T30	69
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1395901	1			T24	6		T28	65676		T29	117
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5228540	1			T22	782		T23	17		T24	51
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	4027603	1			T22	907		T23	63		T24	40
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1417398	1			T23	6		T28	65797		T29	110
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1703837	1			T24	19		T28	99644		T29	134
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	546505	1			T24	3		T28	7217		T30	59
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1403990	1			T24	2		T28	66432		T29	142

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal