Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[1]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[2]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[3]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[4]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[5]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[6]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[7]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[8]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[9]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[10]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[11]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[12]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[13]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[14]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[15]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[16]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[17]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[18]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[19]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[20]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[21]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[22]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[23]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[24]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[25]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[26]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[27]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[28]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[29]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[30]	14327873	1			T22	1689		T23	86		T24	115
bins_for_gpio_bits[31]	14327873	1			T22	1689		T23	86		T24	115

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

266950797

1

T22

27132

T23

717

T24

2000

auto[1]

191541139

1

T22

26916

T23

2035

T24

1680

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

266945818

1

T22

27132

T23

717

T24

2003

auto[1]

191546118

1

T22

26916

T23

2035

T24

1677

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8088775	1			T22	914		T23	20		T24	45
bins_for_gpio_bits[0]	auto[0]	auto[1]	251668	1			T23	2		T28	11641		T29	32
bins_for_gpio_bits[0]	auto[1]	auto[0]	251826	1			T23	2		T28	11641		T29	33
bins_for_gpio_bits[0]	auto[1]	auto[1]	5735604	1			T22	775		T23	62		T24	70
bins_for_gpio_bits[1]	auto[0]	auto[0]	8085604	1			T22	945		T23	26		T24	37
bins_for_gpio_bits[1]	auto[0]	auto[1]	250927	1			T23	1		T28	11631		T29	32
bins_for_gpio_bits[1]	auto[1]	auto[0]	251057	1			T23	1		T28	11631		T29	32
bins_for_gpio_bits[1]	auto[1]	auto[1]	5740285	1			T22	744		T23	58		T24	78
bins_for_gpio_bits[2]	auto[0]	auto[0]	8090417	1			T22	804		T23	17		T24	66
bins_for_gpio_bits[2]	auto[0]	auto[1]	250272	1			T23	3		T28	11595		T29	37
bins_for_gpio_bits[2]	auto[1]	auto[0]	250400	1			T23	3		T28	11596		T29	37
bins_for_gpio_bits[2]	auto[1]	auto[1]	5736784	1			T22	885		T23	63		T24	49
bins_for_gpio_bits[3]	auto[0]	auto[0]	8087657	1			T22	777		T23	28		T24	65
bins_for_gpio_bits[3]	auto[0]	auto[1]	251974	1			T23	1		T24	1		T28	11624
bins_for_gpio_bits[3]	auto[1]	auto[0]	252189	1			T23	1		T28	11625		T29	31
bins_for_gpio_bits[3]	auto[1]	auto[1]	5736053	1			T22	912		T23	56		T24	49
bins_for_gpio_bits[4]	auto[0]	auto[0]	8078354	1			T22	764		T23	19		T24	95
bins_for_gpio_bits[4]	auto[0]	auto[1]	252127	1			T23	1		T28	11845		T29	33
bins_for_gpio_bits[4]	auto[1]	auto[0]	252270	1			T23	1		T28	11848		T29	33
bins_for_gpio_bits[4]	auto[1]	auto[1]	5745122	1			T22	925		T23	65		T24	20
bins_for_gpio_bits[5]	auto[0]	auto[0]	8085351	1			T22	746		T23	25		T24	82
bins_for_gpio_bits[5]	auto[0]	auto[1]	251313	1			T23	2		T28	11762		T29	30
bins_for_gpio_bits[5]	auto[1]	auto[0]	251471	1			T23	2		T28	11762		T29	30
bins_for_gpio_bits[5]	auto[1]	auto[1]	5739738	1			T22	943		T23	57		T24	33
bins_for_gpio_bits[6]	auto[0]	auto[0]	8081781	1			T22	899		T23	26		T24	63
bins_for_gpio_bits[6]	auto[0]	auto[1]	250506	1			T23	1		T28	11697		T29	33
bins_for_gpio_bits[6]	auto[1]	auto[0]	250642	1			T23	1		T28	11698		T29	34
bins_for_gpio_bits[6]	auto[1]	auto[1]	5744944	1			T22	790		T23	58		T24	52
bins_for_gpio_bits[7]	auto[0]	auto[0]	8086889	1			T22	902		T23	20		T24	57
bins_for_gpio_bits[7]	auto[0]	auto[1]	251429	1			T23	3		T28	11764		T29	32
bins_for_gpio_bits[7]	auto[1]	auto[0]	251565	1			T23	3		T28	11764		T29	32
bins_for_gpio_bits[7]	auto[1]	auto[1]	5737990	1			T22	787		T23	60		T24	58
bins_for_gpio_bits[8]	auto[0]	auto[0]	8085590	1			T22	724		T23	22		T24	72
bins_for_gpio_bits[8]	auto[0]	auto[1]	251041	1			T23	3		T28	11697		T29	31
bins_for_gpio_bits[8]	auto[1]	auto[0]	251205	1			T23	3		T28	11699		T29	32
bins_for_gpio_bits[8]	auto[1]	auto[1]	5740037	1			T22	965		T23	58		T24	43
bins_for_gpio_bits[9]	auto[0]	auto[0]	8084269	1			T22	739		T23	25		T24	34
bins_for_gpio_bits[9]	auto[0]	auto[1]	251871	1			T23	3		T28	11723		T29	33
bins_for_gpio_bits[9]	auto[1]	auto[0]	252044	1			T23	3		T28	11725		T29	33
bins_for_gpio_bits[9]	auto[1]	auto[1]	5739689	1			T22	950		T23	55		T24	81
bins_for_gpio_bits[10]	auto[0]	auto[0]	8087749	1			T22	891		T23	24		T24	83
bins_for_gpio_bits[10]	auto[0]	auto[1]	251471	1			T23	2		T28	11699		T29	28
bins_for_gpio_bits[10]	auto[1]	auto[0]	251617	1			T23	2		T28	11700		T29	28
bins_for_gpio_bits[10]	auto[1]	auto[1]	5737036	1			T22	798		T23	58		T24	32
bins_for_gpio_bits[11]	auto[0]	auto[0]	8087690	1			T22	888		T23	12		T24	92
bins_for_gpio_bits[11]	auto[0]	auto[1]	250537	1			T28	11760		T29	29		T30	2
bins_for_gpio_bits[11]	auto[1]	auto[0]	250727	1			T28	11761		T29	30		T30	2
bins_for_gpio_bits[11]	auto[1]	auto[1]	5738919	1			T22	801		T23	74		T24	23
bins_for_gpio_bits[12]	auto[0]	auto[0]	8093671	1			T22	872		T23	18		T24	49
bins_for_gpio_bits[12]	auto[0]	auto[1]	251082	1			T23	1		T28	11647		T29	34
bins_for_gpio_bits[12]	auto[1]	auto[0]	251248	1			T23	1		T28	11648		T29	34
bins_for_gpio_bits[12]	auto[1]	auto[1]	5731872	1			T22	817		T23	66		T24	66
bins_for_gpio_bits[13]	auto[0]	auto[0]	8090663	1			T22	911		T23	14		T24	50
bins_for_gpio_bits[13]	auto[0]	auto[1]	251610	1			T23	1		T28	11714		T29	34
bins_for_gpio_bits[13]	auto[1]	auto[0]	251770	1			T23	1		T28	11715		T29	35
bins_for_gpio_bits[13]	auto[1]	auto[1]	5733830	1			T22	778		T23	70		T24	65
bins_for_gpio_bits[14]	auto[0]	auto[0]	8092001	1			T22	842		T23	19		T24	63
bins_for_gpio_bits[14]	auto[0]	auto[1]	250887	1			T23	2		T28	11769		T29	36
bins_for_gpio_bits[14]	auto[1]	auto[0]	251016	1			T23	2		T28	11771		T29	36
bins_for_gpio_bits[14]	auto[1]	auto[1]	5733969	1			T22	847		T23	63		T24	52
bins_for_gpio_bits[15]	auto[0]	auto[0]	8099109	1			T22	832		T23	22		T24	73
bins_for_gpio_bits[15]	auto[0]	auto[1]	251420	1			T23	2		T28	11655		T29	33
bins_for_gpio_bits[15]	auto[1]	auto[0]	251572	1			T23	2		T28	11658		T29	33
bins_for_gpio_bits[15]	auto[1]	auto[1]	5725772	1			T22	857		T23	60		T24	42
bins_for_gpio_bits[16]	auto[0]	auto[0]	8077717	1			T22	768		T23	29		T24	58
bins_for_gpio_bits[16]	auto[0]	auto[1]	251363	1			T23	2		T28	11817		T29	32
bins_for_gpio_bits[16]	auto[1]	auto[0]	251529	1			T23	2		T28	11817		T29	32
bins_for_gpio_bits[16]	auto[1]	auto[1]	5747264	1			T22	921		T23	53		T24	57
bins_for_gpio_bits[17]	auto[0]	auto[0]	8094925	1			T22	863		T23	18		T24	54
bins_for_gpio_bits[17]	auto[0]	auto[1]	251216	1			T23	3		T28	11596		T29	31
bins_for_gpio_bits[17]	auto[1]	auto[0]	251355	1			T23	3		T28	11596		T29	31
bins_for_gpio_bits[17]	auto[1]	auto[1]	5730377	1			T22	826		T23	62		T24	61
bins_for_gpio_bits[18]	auto[0]	auto[0]	8102964	1			T22	853		T23	15		T24	48
bins_for_gpio_bits[18]	auto[0]	auto[1]	250984	1			T23	3		T28	11738		T29	26
bins_for_gpio_bits[18]	auto[1]	auto[0]	251173	1			T23	3		T28	11739		T29	26
bins_for_gpio_bits[18]	auto[1]	auto[1]	5722752	1			T22	836		T23	65		T24	67
bins_for_gpio_bits[19]	auto[0]	auto[0]	8081218	1			T22	943		T23	19		T24	69
bins_for_gpio_bits[19]	auto[0]	auto[1]	251638	1			T23	2		T28	11547		T29	32
bins_for_gpio_bits[19]	auto[1]	auto[0]	251786	1			T23	2		T28	11547		T29	32
bins_for_gpio_bits[19]	auto[1]	auto[1]	5743231	1			T22	746		T23	63		T24	46
bins_for_gpio_bits[20]	auto[0]	auto[0]	8102362	1			T22	876		T23	23		T24	34
bins_for_gpio_bits[20]	auto[0]	auto[1]	250985	1			T23	2		T28	11826		T29	30
bins_for_gpio_bits[20]	auto[1]	auto[0]	251142	1			T23	2		T28	11828		T29	30
bins_for_gpio_bits[20]	auto[1]	auto[1]	5723384	1			T22	813		T23	59		T24	81
bins_for_gpio_bits[21]	auto[0]	auto[0]	8092984	1			T22	890		T23	22		T24	57
bins_for_gpio_bits[21]	auto[0]	auto[1]	251498	1			T23	2		T24	1		T28	11808
bins_for_gpio_bits[21]	auto[1]	auto[0]	251661	1			T23	2		T28	11808		T29	32
bins_for_gpio_bits[21]	auto[1]	auto[1]	5731730	1			T22	799		T23	60		T24	57
bins_for_gpio_bits[22]	auto[0]	auto[0]	8092385	1			T22	850		T23	25		T24	100
bins_for_gpio_bits[22]	auto[0]	auto[1]	251327	1			T23	2		T28	11722		T29	31
bins_for_gpio_bits[22]	auto[1]	auto[0]	251497	1			T23	2		T28	11724		T29	31
bins_for_gpio_bits[22]	auto[1]	auto[1]	5732664	1			T22	839		T23	57		T24	15
bins_for_gpio_bits[23]	auto[0]	auto[0]	8089174	1			T22	893		T23	11		T24	56
bins_for_gpio_bits[23]	auto[0]	auto[1]	251856	1			T28	11719		T29	26		T30	3
bins_for_gpio_bits[23]	auto[1]	auto[0]	251965	1			T28	11720		T29	27		T30	3
bins_for_gpio_bits[23]	auto[1]	auto[1]	5734878	1			T22	796		T23	75		T24	59
bins_for_gpio_bits[24]	auto[0]	auto[0]	8104569	1			T22	912		T23	26		T24	58
bins_for_gpio_bits[24]	auto[0]	auto[1]	251611	1			T23	4		T24	1		T28	11687
bins_for_gpio_bits[24]	auto[1]	auto[0]	251737	1			T23	4		T28	11689		T29	43
bins_for_gpio_bits[24]	auto[1]	auto[1]	5719956	1			T22	777		T23	52		T24	56
bins_for_gpio_bits[25]	auto[0]	auto[0]	8081496	1			T22	832		T23	16		T24	102
bins_for_gpio_bits[25]	auto[0]	auto[1]	251613	1			T23	1		T28	11694		T29	33
bins_for_gpio_bits[25]	auto[1]	auto[0]	251773	1			T23	1		T28	11697		T29	33
bins_for_gpio_bits[25]	auto[1]	auto[1]	5742991	1			T22	857		T23	68		T24	13
bins_for_gpio_bits[26]	auto[0]	auto[0]	8106621	1			T22	836		T23	21		T24	43
bins_for_gpio_bits[26]	auto[0]	auto[1]	251205	1			T23	2		T28	11743		T29	34
bins_for_gpio_bits[26]	auto[1]	auto[0]	251394	1			T23	2		T28	11744		T29	34
bins_for_gpio_bits[26]	auto[1]	auto[1]	5718653	1			T22	853		T23	61		T24	72
bins_for_gpio_bits[27]	auto[0]	auto[0]	8094818	1			T22	842		T23	16		T24	45
bins_for_gpio_bits[27]	auto[0]	auto[1]	251249	1			T23	1		T28	11654		T29	24
bins_for_gpio_bits[27]	auto[1]	auto[0]	251431	1			T23	1		T28	11656		T29	24
bins_for_gpio_bits[27]	auto[1]	auto[1]	5730375	1			T22	847		T23	68		T24	70
bins_for_gpio_bits[28]	auto[0]	auto[0]	8086667	1			T22	876		T23	23		T24	58
bins_for_gpio_bits[28]	auto[0]	auto[1]	251348	1			T23	1		T28	11700		T29	32
bins_for_gpio_bits[28]	auto[1]	auto[0]	251472	1			T23	1		T28	11703		T29	32
bins_for_gpio_bits[28]	auto[1]	auto[1]	5738386	1			T22	813		T23	61		T24	57
bins_for_gpio_bits[29]	auto[0]	auto[0]	8092352	1			T22	845		T23	16		T24	56
bins_for_gpio_bits[29]	auto[0]	auto[1]	250794	1			T23	1		T28	11682		T29	35
bins_for_gpio_bits[29]	auto[1]	auto[0]	250942	1			T23	1		T28	11683		T29	35
bins_for_gpio_bits[29]	auto[1]	auto[1]	5733785	1			T22	844		T23	68		T24	59
bins_for_gpio_bits[30]	auto[0]	auto[0]	8100580	1			T22	821		T23	19		T24	66
bins_for_gpio_bits[30]	auto[0]	auto[1]	251008	1			T23	4		T28	11697		T29	31
bins_for_gpio_bits[30]	auto[1]	auto[0]	251144	1			T23	4		T28	11697		T29	32
bins_for_gpio_bits[30]	auto[1]	auto[1]	5725141	1			T22	868		T23	59		T24	49
bins_for_gpio_bits[31]	auto[0]	auto[0]	8098337	1			T22	782		T23	20		T24	70
bins_for_gpio_bits[31]	auto[0]	auto[1]	251249	1			T23	3		T28	11641		T29	34
bins_for_gpio_bits[31]	auto[1]	auto[0]	251438	1			T23	3		T28	11642		T29	34
bins_for_gpio_bits[31]	auto[1]	auto[1]	5726849	1			T22	907		T23	60		T24	45