Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8442129 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
52 |
| auto[1] |
6146043 |
1 |
|
|
T24 |
41 |
|
T25 |
1340 |
|
T27 |
142 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13791157 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
92 |
| auto[1] |
797015 |
1 |
|
|
T24 |
1 |
|
T25 |
186 |
|
T27 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8364275 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
69 |
| auto[1] |
6223897 |
1 |
|
|
T24 |
24 |
|
T25 |
905 |
|
T27 |
100 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2721075 |
1 |
|
|
T24 |
15 |
|
T25 |
375 |
|
T27 |
32 |
| auto[1] |
auto[0] |
auto[1] |
400536 |
1 |
|
|
T25 |
96 |
|
T27 |
3 |
|
T28 |
19094 |
| auto[1] |
auto[1] |
auto[0] |
2705807 |
1 |
|
|
T24 |
8 |
|
T25 |
344 |
|
T27 |
64 |
| auto[1] |
auto[1] |
auto[1] |
396479 |
1 |
|
|
T24 |
1 |
|
T25 |
90 |
|
T27 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8411290 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
57 |
| auto[1] |
6176882 |
1 |
|
|
T24 |
36 |
|
T25 |
1288 |
|
T27 |
110 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13800078 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
92 |
| auto[1] |
788094 |
1 |
|
|
T24 |
1 |
|
T25 |
200 |
|
T27 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8410478 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
70 |
| auto[1] |
6177694 |
1 |
|
|
T24 |
23 |
|
T25 |
1061 |
|
T27 |
102 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2696722 |
1 |
|
|
T24 |
14 |
|
T25 |
382 |
|
T27 |
48 |
| auto[1] |
auto[0] |
auto[1] |
394855 |
1 |
|
|
T24 |
1 |
|
T25 |
87 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2692878 |
1 |
|
|
T24 |
8 |
|
T25 |
479 |
|
T27 |
48 |
| auto[1] |
auto[1] |
auto[1] |
393239 |
1 |
|
|
T25 |
113 |
|
T27 |
2 |
|
T28 |
18696 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8426509 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
50 |
| auto[1] |
6161663 |
1 |
|
|
T24 |
43 |
|
T25 |
1308 |
|
T27 |
76 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13802471 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
785701 |
1 |
|
|
T25 |
236 |
|
T27 |
3 |
|
T28 |
37207 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8424892 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
69 |
| auto[1] |
6163280 |
1 |
|
|
T24 |
24 |
|
T25 |
1190 |
|
T27 |
102 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2707221 |
1 |
|
|
T24 |
8 |
|
T25 |
539 |
|
T27 |
61 |
| auto[1] |
auto[0] |
auto[1] |
395821 |
1 |
|
|
T25 |
143 |
|
T27 |
2 |
|
T28 |
17938 |
| auto[1] |
auto[1] |
auto[0] |
2670358 |
1 |
|
|
T24 |
16 |
|
T25 |
415 |
|
T27 |
38 |
| auto[1] |
auto[1] |
auto[1] |
389880 |
1 |
|
|
T25 |
93 |
|
T27 |
1 |
|
T28 |
19269 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8431622 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
77 |
| auto[1] |
6156550 |
1 |
|
|
T24 |
16 |
|
T25 |
1360 |
|
T27 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13802624 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
785548 |
1 |
|
|
T25 |
239 |
|
T27 |
4 |
|
T28 |
38719 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8425852 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
71 |
| auto[1] |
6162320 |
1 |
|
|
T24 |
22 |
|
T25 |
1219 |
|
T27 |
96 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2693279 |
1 |
|
|
T24 |
13 |
|
T25 |
443 |
|
T27 |
49 |
| auto[1] |
auto[0] |
auto[1] |
394202 |
1 |
|
|
T25 |
101 |
|
T27 |
3 |
|
T28 |
20014 |
| auto[1] |
auto[1] |
auto[0] |
2683493 |
1 |
|
|
T24 |
9 |
|
T25 |
537 |
|
T27 |
43 |
| auto[1] |
auto[1] |
auto[1] |
391346 |
1 |
|
|
T25 |
138 |
|
T27 |
1 |
|
T28 |
18705 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8404611 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
69 |
| auto[1] |
6183561 |
1 |
|
|
T24 |
24 |
|
T25 |
1266 |
|
T27 |
76 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13801575 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
92 |
| auto[1] |
786597 |
1 |
|
|
T24 |
1 |
|
T25 |
243 |
|
T27 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8426891 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
51 |
| auto[1] |
6161281 |
1 |
|
|
T24 |
42 |
|
T25 |
1269 |
|
T27 |
106 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2682310 |
1 |
|
|
T24 |
31 |
|
T25 |
482 |
|
T27 |
59 |
| auto[1] |
auto[0] |
auto[1] |
391986 |
1 |
|
|
T25 |
111 |
|
T27 |
2 |
|
T28 |
19030 |
| auto[1] |
auto[1] |
auto[0] |
2692374 |
1 |
|
|
T24 |
10 |
|
T25 |
544 |
|
T27 |
43 |
| auto[1] |
auto[1] |
auto[1] |
394611 |
1 |
|
|
T24 |
1 |
|
T25 |
132 |
|
T27 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8407839 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
45 |
| auto[1] |
6180333 |
1 |
|
|
T24 |
48 |
|
T25 |
1348 |
|
T27 |
106 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13801603 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
92 |
| auto[1] |
786569 |
1 |
|
|
T24 |
1 |
|
T25 |
264 |
|
T27 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8424622 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
60 |
| auto[1] |
6163550 |
1 |
|
|
T24 |
33 |
|
T25 |
1289 |
|
T27 |
98 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2685959 |
1 |
|
|
T24 |
6 |
|
T25 |
465 |
|
T27 |
44 |
| auto[1] |
auto[0] |
auto[1] |
392116 |
1 |
|
|
T25 |
114 |
|
T27 |
1 |
|
T28 |
18483 |
| auto[1] |
auto[1] |
auto[0] |
2691022 |
1 |
|
|
T24 |
26 |
|
T25 |
560 |
|
T27 |
49 |
| auto[1] |
auto[1] |
auto[1] |
394453 |
1 |
|
|
T24 |
1 |
|
T25 |
150 |
|
T27 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8434960 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
53 |
| auto[1] |
6153212 |
1 |
|
|
T24 |
40 |
|
T25 |
1563 |
|
T27 |
137 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13804866 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
783306 |
1 |
|
|
T25 |
193 |
|
T27 |
8 |
|
T28 |
37682 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8444119 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
74 |
| auto[1] |
6144053 |
1 |
|
|
T24 |
19 |
|
T25 |
980 |
|
T27 |
134 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2686921 |
1 |
|
|
T24 |
12 |
|
T25 |
259 |
|
T27 |
35 |
| auto[1] |
auto[0] |
auto[1] |
392238 |
1 |
|
|
T25 |
62 |
|
T27 |
4 |
|
T28 |
18746 |
| auto[1] |
auto[1] |
auto[0] |
2673826 |
1 |
|
|
T24 |
7 |
|
T25 |
528 |
|
T27 |
91 |
| auto[1] |
auto[1] |
auto[1] |
391068 |
1 |
|
|
T25 |
131 |
|
T27 |
4 |
|
T28 |
18936 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435281 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
62 |
| auto[1] |
6152891 |
1 |
|
|
T24 |
31 |
|
T25 |
1452 |
|
T27 |
151 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13801085 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
92 |
| auto[1] |
787087 |
1 |
|
|
T24 |
1 |
|
T25 |
285 |
|
T27 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8422400 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
62 |
| auto[1] |
6165772 |
1 |
|
|
T24 |
31 |
|
T25 |
1450 |
|
T27 |
119 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2707370 |
1 |
|
|
T24 |
14 |
|
T25 |
553 |
|
T27 |
26 |
| auto[1] |
auto[0] |
auto[1] |
396601 |
1 |
|
|
T24 |
1 |
|
T25 |
141 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2671315 |
1 |
|
|
T24 |
16 |
|
T25 |
612 |
|
T27 |
87 |
| auto[1] |
auto[1] |
auto[1] |
390486 |
1 |
|
|
T25 |
144 |
|
T27 |
5 |
|
T28 |
18890 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8453008 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
72 |
| auto[1] |
6135164 |
1 |
|
|
T24 |
21 |
|
T25 |
1075 |
|
T27 |
96 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13800771 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
92 |
| auto[1] |
787401 |
1 |
|
|
T24 |
1 |
|
T25 |
239 |
|
T27 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8425751 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
77 |
| auto[1] |
6162421 |
1 |
|
|
T24 |
16 |
|
T25 |
1239 |
|
T27 |
110 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2708894 |
1 |
|
|
T24 |
9 |
|
T25 |
596 |
|
T27 |
51 |
| auto[1] |
auto[0] |
auto[1] |
396890 |
1 |
|
|
T24 |
1 |
|
T25 |
143 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2666126 |
1 |
|
|
T24 |
6 |
|
T25 |
404 |
|
T27 |
54 |
| auto[1] |
auto[1] |
auto[1] |
390511 |
1 |
|
|
T25 |
96 |
|
T27 |
1 |
|
T28 |
18429 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8398974 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
69 |
| auto[1] |
6189198 |
1 |
|
|
T24 |
24 |
|
T25 |
1329 |
|
T27 |
95 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13810915 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
777257 |
1 |
|
|
T25 |
287 |
|
T27 |
4 |
|
T28 |
37440 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8474315 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
77 |
| auto[1] |
6113857 |
1 |
|
|
T24 |
16 |
|
T25 |
1414 |
|
T27 |
93 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2665290 |
1 |
|
|
T25 |
525 |
|
T27 |
57 |
|
T28 |
127103 |
| auto[1] |
auto[0] |
auto[1] |
387866 |
1 |
|
|
T25 |
132 |
|
T27 |
3 |
|
T28 |
18345 |
| auto[1] |
auto[1] |
auto[0] |
2671310 |
1 |
|
|
T24 |
16 |
|
T25 |
602 |
|
T27 |
32 |
| auto[1] |
auto[1] |
auto[1] |
389391 |
1 |
|
|
T25 |
155 |
|
T27 |
1 |
|
T28 |
19095 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8377069 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
60 |
| auto[1] |
6211103 |
1 |
|
|
T24 |
33 |
|
T25 |
1463 |
|
T27 |
96 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13805417 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
782755 |
1 |
|
|
T25 |
273 |
|
T27 |
3 |
|
T28 |
36924 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8455033 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
69 |
| auto[1] |
6133139 |
1 |
|
|
T24 |
24 |
|
T25 |
1343 |
|
T27 |
90 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2663084 |
1 |
|
|
T24 |
6 |
|
T25 |
459 |
|
T27 |
55 |
| auto[1] |
auto[0] |
auto[1] |
389136 |
1 |
|
|
T25 |
115 |
|
T27 |
2 |
|
T28 |
18721 |
| auto[1] |
auto[1] |
auto[0] |
2687300 |
1 |
|
|
T24 |
18 |
|
T25 |
611 |
|
T27 |
32 |
| auto[1] |
auto[1] |
auto[1] |
393619 |
1 |
|
|
T25 |
158 |
|
T27 |
1 |
|
T28 |
18203 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437801 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
85 |
| auto[1] |
6150371 |
1 |
|
|
T24 |
8 |
|
T25 |
1101 |
|
T27 |
102 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13805985 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
782187 |
1 |
|
|
T25 |
276 |
|
T27 |
6 |
|
T28 |
37037 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8461059 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
89 |
| auto[1] |
6127113 |
1 |
|
|
T24 |
4 |
|
T25 |
1322 |
|
T27 |
121 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2676239 |
1 |
|
|
T24 |
4 |
|
T25 |
628 |
|
T27 |
53 |
| auto[1] |
auto[0] |
auto[1] |
392289 |
1 |
|
|
T25 |
165 |
|
T27 |
1 |
|
T28 |
19049 |
| auto[1] |
auto[1] |
auto[0] |
2668687 |
1 |
|
|
T25 |
418 |
|
T27 |
62 |
|
T28 |
123072 |
| auto[1] |
auto[1] |
auto[1] |
389898 |
1 |
|
|
T25 |
111 |
|
T27 |
5 |
|
T28 |
17988 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8445615 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
82 |
| auto[1] |
6142557 |
1 |
|
|
T24 |
11 |
|
T25 |
1386 |
|
T27 |
82 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13801749 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
91 |
| auto[1] |
786423 |
1 |
|
|
T24 |
2 |
|
T25 |
246 |
|
T27 |
7 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8422535 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
63 |
| auto[1] |
6165637 |
1 |
|
|
T24 |
30 |
|
T25 |
1252 |
|
T27 |
156 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2704109 |
1 |
|
|
T24 |
19 |
|
T25 |
475 |
|
T27 |
91 |
| auto[1] |
auto[0] |
auto[1] |
395964 |
1 |
|
|
T24 |
2 |
|
T25 |
120 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[0] |
2675105 |
1 |
|
|
T24 |
9 |
|
T25 |
531 |
|
T27 |
58 |
| auto[1] |
auto[1] |
auto[1] |
390459 |
1 |
|
|
T25 |
126 |
|
T27 |
3 |
|
T28 |
19214 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8427721 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
59 |
| auto[1] |
6160451 |
1 |
|
|
T24 |
34 |
|
T25 |
1262 |
|
T27 |
127 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13802858 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
92 |
| auto[1] |
785314 |
1 |
|
|
T24 |
1 |
|
T25 |
268 |
|
T27 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8444504 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
73 |
| auto[1] |
6143668 |
1 |
|
|
T24 |
20 |
|
T25 |
1359 |
|
T27 |
88 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2688143 |
1 |
|
|
T24 |
5 |
|
T25 |
558 |
|
T27 |
19 |
| auto[1] |
auto[0] |
auto[1] |
394030 |
1 |
|
|
T25 |
129 |
|
T27 |
1 |
|
T28 |
19431 |
| auto[1] |
auto[1] |
auto[0] |
2670211 |
1 |
|
|
T24 |
14 |
|
T25 |
533 |
|
T27 |
65 |
| auto[1] |
auto[1] |
auto[1] |
391284 |
1 |
|
|
T24 |
1 |
|
T25 |
139 |
|
T27 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8440820 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
78 |
| auto[1] |
6147352 |
1 |
|
|
T24 |
15 |
|
T25 |
1235 |
|
T27 |
135 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13797331 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
91 |
| auto[1] |
790841 |
1 |
|
|
T24 |
2 |
|
T25 |
296 |
|
T27 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8403242 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
66 |
| auto[1] |
6184930 |
1 |
|
|
T24 |
27 |
|
T25 |
1428 |
|
T27 |
127 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2700900 |
1 |
|
|
T24 |
19 |
|
T25 |
606 |
|
T27 |
48 |
| auto[1] |
auto[0] |
auto[1] |
395810 |
1 |
|
|
T24 |
1 |
|
T25 |
154 |
|
T27 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2693189 |
1 |
|
|
T24 |
6 |
|
T25 |
526 |
|
T27 |
74 |
| auto[1] |
auto[1] |
auto[1] |
395031 |
1 |
|
|
T24 |
1 |
|
T25 |
142 |
|
T27 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8462977 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
68 |
| auto[1] |
6125195 |
1 |
|
|
T24 |
25 |
|
T25 |
1379 |
|
T27 |
141 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13800950 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
787222 |
1 |
|
|
T25 |
293 |
|
T27 |
3 |
|
T28 |
38162 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8426884 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
57 |
| auto[1] |
6161288 |
1 |
|
|
T24 |
36 |
|
T25 |
1524 |
|
T27 |
96 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2714552 |
1 |
|
|
T24 |
26 |
|
T25 |
569 |
|
T27 |
16 |
| auto[1] |
auto[0] |
auto[1] |
397917 |
1 |
|
|
T25 |
146 |
|
T28 |
18569 |
|
T31 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2659514 |
1 |
|
|
T24 |
10 |
|
T25 |
662 |
|
T27 |
77 |
| auto[1] |
auto[1] |
auto[1] |
389305 |
1 |
|
|
T25 |
147 |
|
T27 |
3 |
|
T28 |
19593 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8437543 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
53 |
| auto[1] |
6150629 |
1 |
|
|
T24 |
40 |
|
T25 |
1006 |
|
T27 |
76 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13797149 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
92 |
| auto[1] |
791023 |
1 |
|
|
T24 |
1 |
|
T25 |
258 |
|
T27 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8403518 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
58 |
| auto[1] |
6184654 |
1 |
|
|
T24 |
35 |
|
T25 |
1275 |
|
T27 |
91 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2693385 |
1 |
|
|
T24 |
11 |
|
T25 |
595 |
|
T27 |
60 |
| auto[1] |
auto[0] |
auto[1] |
393995 |
1 |
|
|
T25 |
163 |
|
T27 |
2 |
|
T28 |
19054 |
| auto[1] |
auto[1] |
auto[0] |
2700246 |
1 |
|
|
T24 |
23 |
|
T25 |
422 |
|
T27 |
27 |
| auto[1] |
auto[1] |
auto[1] |
397028 |
1 |
|
|
T24 |
1 |
|
T25 |
95 |
|
T27 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8388631 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
75 |
| auto[1] |
6199541 |
1 |
|
|
T24 |
18 |
|
T25 |
1169 |
|
T27 |
86 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13799730 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
91 |
| auto[1] |
788442 |
1 |
|
|
T24 |
2 |
|
T25 |
268 |
|
T27 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8412562 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
70 |
| auto[1] |
6175610 |
1 |
|
|
T24 |
23 |
|
T25 |
1364 |
|
T27 |
106 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2691791 |
1 |
|
|
T24 |
10 |
|
T25 |
626 |
|
T27 |
53 |
| auto[1] |
auto[0] |
auto[1] |
394166 |
1 |
|
|
T24 |
1 |
|
T25 |
159 |
|
T27 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2695377 |
1 |
|
|
T24 |
11 |
|
T25 |
470 |
|
T27 |
48 |
| auto[1] |
auto[1] |
auto[1] |
394276 |
1 |
|
|
T24 |
1 |
|
T25 |
109 |
|
T27 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8435791 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
72 |
| auto[1] |
6152381 |
1 |
|
|
T24 |
21 |
|
T25 |
1571 |
|
T27 |
98 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13804883 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
92 |
| auto[1] |
783289 |
1 |
|
|
T24 |
1 |
|
T25 |
216 |
|
T27 |
8 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8447226 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
65 |
| auto[1] |
6140946 |
1 |
|
|
T24 |
28 |
|
T25 |
1134 |
|
T27 |
109 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2680821 |
1 |
|
|
T24 |
16 |
|
T25 |
345 |
|
T27 |
51 |
| auto[1] |
auto[0] |
auto[1] |
391050 |
1 |
|
|
T24 |
1 |
|
T25 |
81 |
|
T27 |
2 |
| auto[1] |
auto[1] |
auto[0] |
2676836 |
1 |
|
|
T24 |
11 |
|
T25 |
573 |
|
T27 |
50 |
| auto[1] |
auto[1] |
auto[1] |
392239 |
1 |
|
|
T25 |
135 |
|
T27 |
6 |
|
T28 |
18678 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8380152 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
78 |
| auto[1] |
6208020 |
1 |
|
|
T24 |
15 |
|
T25 |
1163 |
|
T27 |
107 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13802215 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
785957 |
1 |
|
|
T25 |
251 |
|
T27 |
6 |
|
T28 |
39752 |