Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8395413 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
45 |
| auto[1] |
6192759 |
1 |
|
|
T24 |
48 |
|
T25 |
1025 |
|
T27 |
105 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13799540 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
788632 |
1 |
|
|
T25 |
263 |
|
T27 |
6 |
|
T28 |
39126 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8410167 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
53 |
| auto[1] |
6178005 |
1 |
|
|
T24 |
40 |
|
T25 |
1406 |
|
T27 |
99 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2693345 |
1 |
|
|
T24 |
11 |
|
T25 |
718 |
|
T27 |
39 |
| auto[1] |
auto[0] |
auto[1] |
394554 |
1 |
|
|
T25 |
158 |
|
T27 |
2 |
|
T28 |
20327 |
| auto[1] |
auto[1] |
auto[0] |
2696028 |
1 |
|
|
T24 |
29 |
|
T25 |
425 |
|
T27 |
54 |
| auto[1] |
auto[1] |
auto[1] |
394078 |
1 |
|
|
T25 |
105 |
|
T27 |
4 |
|
T28 |
18799 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |