Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8414002 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
45 |
| auto[1] |
6174170 |
1 |
|
|
T24 |
48 |
|
T25 |
1050 |
|
T27 |
70 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13801924 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
786248 |
1 |
|
|
T25 |
227 |
|
T27 |
7 |
|
T28 |
38351 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8427728 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
52 |
| auto[1] |
6160444 |
1 |
|
|
T24 |
41 |
|
T25 |
1166 |
|
T27 |
129 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2684469 |
1 |
|
|
T24 |
7 |
|
T25 |
559 |
|
T27 |
73 |
| auto[1] |
auto[0] |
auto[1] |
393350 |
1 |
|
|
T25 |
144 |
|
T27 |
4 |
|
T28 |
19711 |
| auto[1] |
auto[1] |
auto[0] |
2689727 |
1 |
|
|
T24 |
34 |
|
T25 |
380 |
|
T27 |
49 |
| auto[1] |
auto[1] |
auto[1] |
392898 |
1 |
|
|
T25 |
83 |
|
T27 |
3 |
|
T28 |
18640 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |