Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8425674 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
66 |
| auto[1] |
6162498 |
1 |
|
|
T24 |
27 |
|
T25 |
1165 |
|
T27 |
111 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13801054 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
787118 |
1 |
|
|
T25 |
224 |
|
T27 |
3 |
|
T28 |
39009 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8423902 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
80 |
| auto[1] |
6164270 |
1 |
|
|
T24 |
13 |
|
T25 |
1216 |
|
T27 |
90 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2703985 |
1 |
|
|
T24 |
8 |
|
T25 |
555 |
|
T27 |
40 |
| auto[1] |
auto[0] |
auto[1] |
395841 |
1 |
|
|
T25 |
123 |
|
T27 |
2 |
|
T28 |
19944 |
| auto[1] |
auto[1] |
auto[0] |
2673167 |
1 |
|
|
T24 |
5 |
|
T25 |
437 |
|
T27 |
47 |
| auto[1] |
auto[1] |
auto[1] |
391277 |
1 |
|
|
T25 |
101 |
|
T27 |
1 |
|
T28 |
19065 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |