Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8392656 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
84 |
| auto[1] |
6195516 |
1 |
|
|
T24 |
9 |
|
T25 |
1346 |
|
T27 |
122 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13792790 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
92 |
| auto[1] |
795382 |
1 |
|
|
T24 |
1 |
|
T25 |
240 |
|
T27 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8363345 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
74 |
| auto[1] |
6224827 |
1 |
|
|
T24 |
19 |
|
T25 |
1276 |
|
T27 |
100 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2711306 |
1 |
|
|
T24 |
18 |
|
T25 |
487 |
|
T27 |
49 |
| auto[1] |
auto[0] |
auto[1] |
397183 |
1 |
|
|
T24 |
1 |
|
T25 |
116 |
|
T27 |
3 |
| auto[1] |
auto[1] |
auto[0] |
2718139 |
1 |
|
|
T25 |
549 |
|
T27 |
47 |
|
T28 |
133951 |
| auto[1] |
auto[1] |
auto[1] |
398199 |
1 |
|
|
T25 |
124 |
|
T27 |
1 |
|
T28 |
19560 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |