Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8387684 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
86 |
| auto[1] |
6200488 |
1 |
|
|
T24 |
7 |
|
T25 |
1571 |
|
T27 |
119 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13794900 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
93 |
| auto[1] |
793272 |
1 |
|
|
T25 |
242 |
|
T27 |
6 |
|
T28 |
39772 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8389309 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
71 |
| auto[1] |
6198863 |
1 |
|
|
T24 |
22 |
|
T25 |
1227 |
|
T27 |
121 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2688744 |
1 |
|
|
T24 |
22 |
|
T25 |
344 |
|
T27 |
46 |
| auto[1] |
auto[0] |
auto[1] |
394540 |
1 |
|
|
T25 |
83 |
|
T27 |
3 |
|
T28 |
19381 |
| auto[1] |
auto[1] |
auto[0] |
2716847 |
1 |
|
|
T25 |
641 |
|
T27 |
69 |
|
T28 |
137003 |
| auto[1] |
auto[1] |
auto[1] |
398732 |
1 |
|
|
T25 |
159 |
|
T27 |
3 |
|
T28 |
20391 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |