Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8442129 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
52 |
| auto[1] |
6146043 |
1 |
|
|
T24 |
41 |
|
T25 |
1340 |
|
T27 |
142 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11974865 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
69 |
| auto[1] |
2613307 |
1 |
|
|
T24 |
24 |
|
T25 |
604 |
|
T27 |
51 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8428022 |
1 |
|
|
T22 |
1689 |
|
T23 |
49 |
|
T24 |
66 |
| auto[1] |
6160150 |
1 |
|
|
T24 |
27 |
|
T25 |
1298 |
|
T27 |
76 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1766998 |
1 |
|
|
T25 |
328 |
|
T27 |
2 |
|
T28 |
94422 |
| auto[1] |
auto[0] |
auto[1] |
1301763 |
1 |
|
|
T24 |
6 |
|
T25 |
295 |
|
T27 |
25 |
| auto[1] |
auto[1] |
auto[0] |
1779845 |
1 |
|
|
T24 |
3 |
|
T25 |
366 |
|
T27 |
23 |
| auto[1] |
auto[1] |
auto[1] |
1311544 |
1 |
|
|
T24 |
18 |
|
T25 |
309 |
|
T27 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |